Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	57712	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	59297	1		T1	700		T2	41		T3	368

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	71556	1		T1	172		T2	219		T3	92
values[0x0]	22252	1		T1	283		T2	32		T3	144
values[0x1]	23201	1		T1	345		T2	19		T3	220

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	39947	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	77062	1		T1	755		T2	125		T3	430

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	404	1		T1	4		T7	1		T20	18
valid_sources[0x01]	366	1		T1	3		T7	2		T20	19
valid_sources[0x02]	361	1		T1	4		T8	1		T20	11
valid_sources[0x03]	429	1		T1	2		T3	1		T7	2
valid_sources[0x04]	312	1		T1	6		T2	1		T3	2
valid_sources[0x05]	478	1		T1	2		T3	4		T20	8
valid_sources[0x06]	492	1		T1	1		T3	1		T7	3
valid_sources[0x07]	556	1		T1	3		T3	3		T7	1
valid_sources[0x08]	588	1		T1	2		T3	2		T7	4
valid_sources[0x09]	410	1		T1	2		T2	1		T3	2
valid_sources[0x0a]	568	1		T1	6		T2	1		T3	1
valid_sources[0x0b]	425	1		T1	2		T3	2		T7	2
valid_sources[0x0c]	292	1		T2	11		T3	1		T7	2
valid_sources[0x0d]	452	1		T1	1		T2	8		T3	2
valid_sources[0x0e]	335	1		T1	3		T3	4		T7	2
valid_sources[0x0f]	360	1		T1	6		T2	3		T8	1
valid_sources[0x10]	416	1		T1	3		T3	3		T7	1
valid_sources[0x11]	320	1		T1	1		T2	6		T3	3
valid_sources[0x12]	873	1		T1	1		T2	1		T3	1
valid_sources[0x13]	454	1		T1	2		T3	3		T7	4
valid_sources[0x14]	479	1		T1	4		T3	4		T7	1
valid_sources[0x15]	547	1		T1	1		T3	3		T7	2
valid_sources[0x16]	334	1		T1	1		T3	1		T7	1
valid_sources[0x17]	316	1		T1	5		T2	1		T3	3
valid_sources[0x18]	348	1		T1	3		T3	1		T7	3
valid_sources[0x19]	446	1		T1	2		T2	1		T3	2
valid_sources[0x1a]	434	1		T1	4		T2	1		T3	1
valid_sources[0x1b]	478	1		T1	2		T3	1		T7	1
valid_sources[0x1c]	610	1		T1	6		T3	2		T7	1
valid_sources[0x1d]	539	1		T1	2		T3	1		T7	1
valid_sources[0x1e]	475	1		T1	3		T3	1		T7	2
valid_sources[0x1f]	469	1		T1	6		T3	1		T20	13
valid_sources[0x20]	592	1		T1	2		T3	1		T7	1
valid_sources[0x21]	401	1		T1	2		T2	3		T3	1
valid_sources[0x22]	714	1		T1	2		T2	5		T3	4
valid_sources[0x23]	572	1		T1	4		T3	2		T7	3
valid_sources[0x24]	482	1		T1	1		T3	4		T7	6
valid_sources[0x25]	435	1		T1	2		T7	2		T8	2
valid_sources[0x26]	483	1		T3	2		T7	6		T20	23
valid_sources[0x27]	407	1		T1	5		T3	1		T7	3
valid_sources[0x28]	452	1		T1	2		T3	2		T8	1
valid_sources[0x29]	338	1		T1	2		T3	4		T8	1
valid_sources[0x2a]	335	1		T1	1		T3	3		T7	1
valid_sources[0x2b]	346	1		T1	3		T2	1		T7	2
valid_sources[0x2c]	479	1		T1	8		T3	4		T7	2
valid_sources[0x2d]	367	1		T1	6		T2	7		T3	1
valid_sources[0x2e]	453	1		T1	1		T3	3		T7	1
valid_sources[0x2f]	450	1		T1	3		T3	3		T7	2
valid_sources[0x30]	418	1		T1	2		T8	4		T20	18
valid_sources[0x31]	440	1		T1	3		T2	1		T3	3
valid_sources[0x32]	559	1		T3	1		T7	2		T8	1
valid_sources[0x33]	454	1		T1	1		T3	4		T7	4
valid_sources[0x34]	489	1		T1	5		T3	5		T8	1
valid_sources[0x35]	346	1		T1	3		T3	1		T7	4
valid_sources[0x36]	383	1		T1	2		T3	1		T7	2
valid_sources[0x37]	247	1		T1	6		T3	1		T7	1
valid_sources[0x38]	383	1		T1	1		T20	15		T21	2
valid_sources[0x39]	472	1		T1	2		T3	1		T7	1
valid_sources[0x3a]	404	1		T1	5		T2	3		T3	3
valid_sources[0x3b]	291	1		T1	5		T20	7		T21	1
valid_sources[0x3c]	336	1		T1	3		T2	3		T3	5
valid_sources[0x3d]	357	1		T1	3		T3	1		T7	1
valid_sources[0x3e]	343	1		T1	5		T3	5		T7	3
valid_sources[0x3f]	341	1		T1	5		T7	1		T14	1
valid_sources[0x40]	488	1		T1	3		T3	2		T20	10
valid_sources[0x41]	440	1		T3	4		T7	1		T20	10
valid_sources[0x42]	620	1		T1	3		T3	3		T7	1
valid_sources[0x43]	385	1		T1	4		T3	1		T7	3
valid_sources[0x44]	411	1		T1	3		T3	2		T7	3
valid_sources[0x45]	499	1		T1	4		T3	3		T7	2
valid_sources[0x46]	442	1		T1	2		T7	1		T8	1
valid_sources[0x47]	566	1		T1	2		T3	2		T7	1
valid_sources[0x48]	378	1		T1	5		T3	2		T7	3
valid_sources[0x49]	461	1		T1	9		T3	1		T7	1
valid_sources[0x4a]	525	1		T1	3		T7	1		T20	26
valid_sources[0x4b]	483	1		T1	4		T3	2		T7	2
valid_sources[0x4c]	280	1		T1	3		T3	3		T20	10
valid_sources[0x4d]	369	1		T1	1		T3	2		T7	3
valid_sources[0x4e]	338	1		T1	2		T3	1		T7	3
valid_sources[0x4f]	352	1		T1	6		T2	5		T8	2
valid_sources[0x50]	563	1		T1	2		T3	2		T7	3
valid_sources[0x51]	538	1		T1	2		T3	1		T7	2
valid_sources[0x52]	364	1		T1	6		T3	1		T7	2
valid_sources[0x53]	566	1		T1	6		T3	1		T7	1
valid_sources[0x54]	498	1		T1	6		T3	3		T7	3
valid_sources[0x55]	406	1		T1	3		T3	3		T7	1
valid_sources[0x56]	421	1		T1	2		T2	5		T7	1
valid_sources[0x57]	576	1		T1	2		T3	6		T7	3
valid_sources[0x58]	569	1		T1	3		T7	3		T20	8
valid_sources[0x59]	524	1		T1	3		T3	1		T7	4
valid_sources[0x5a]	411	1		T1	1		T3	2		T8	2
valid_sources[0x5b]	677	1		T1	4		T3	2		T7	2
valid_sources[0x5c]	454	1		T1	2		T2	12		T3	1
valid_sources[0x5d]	565	1		T1	5		T3	2		T7	3
valid_sources[0x5e]	291	1		T1	6		T2	11		T8	3
valid_sources[0x5f]	299	1		T1	5		T3	2		T7	2
valid_sources[0x60]	439	1		T1	6		T3	2		T7	2
valid_sources[0x61]	491	1		T1	3		T2	10		T3	1
valid_sources[0x62]	364	1		T1	2		T2	3		T3	3
valid_sources[0x63]	535	1		T1	5		T3	2		T7	4
valid_sources[0x64]	333	1		T1	5		T3	3		T8	2
valid_sources[0x65]	484	1		T1	2		T3	4		T20	14
valid_sources[0x66]	481	1		T1	4		T7	2		T14	1
valid_sources[0x67]	425	1		T1	1		T3	3		T8	2
valid_sources[0x68]	422	1		T1	3		T3	1		T7	1
valid_sources[0x69]	724	1		T1	1		T7	2		T8	2
valid_sources[0x6a]	527	1		T3	1		T7	2		T20	9
valid_sources[0x6b]	398	1		T1	1		T2	1		T3	1
valid_sources[0x6c]	525	1		T3	1		T20	7		T4	11
valid_sources[0x6d]	327	1		T1	3		T2	7		T7	4
valid_sources[0x6e]	523	1		T3	3		T7	1		T20	8
valid_sources[0x6f]	1891	1		T1	5		T2	1		T3	1
valid_sources[0x70]	410	1		T1	4		T3	3		T7	1
valid_sources[0x71]	528	1		T1	2		T3	4		T7	3
valid_sources[0x72]	520	1		T3	1		T8	2		T20	7
valid_sources[0x73]	442	1		T1	2		T3	1		T7	1
valid_sources[0x74]	302	1		T1	3		T2	3		T3	1
valid_sources[0x75]	536	1		T1	2		T3	5		T8	3
valid_sources[0x76]	334	1		T1	2		T7	2		T8	1
valid_sources[0x77]	361	1		T1	1		T3	2		T7	1
valid_sources[0x78]	680	1		T1	4		T7	2		T8	1
valid_sources[0x79]	364	1		T1	5		T3	3		T7	2
valid_sources[0x7a]	302	1		T1	5		T2	1		T3	2
valid_sources[0x7b]	417	1		T1	4		T7	2		T20	11
valid_sources[0x7c]	477	1		T1	3		T3	2		T7	1
valid_sources[0x7d]	398	1		T1	2		T3	1		T20	7
valid_sources[0x7e]	519	1		T1	2		T2	6		T7	1
valid_sources[0x7f]	708	1		T1	4		T3	3		T7	2
valid_sources[0x80]	550	1		T1	2		T3	1		T7	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24058

1

T1

163

T2

13

T3

85

values[0x0]

all_enables

biggest_size

18702

1

T1

274

T2

23

T3

136

values[0x1]

all_enables

biggest_size

16537

1

T1

263

T2

5

T3

147