Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	72460	1		T1	1069		T2	229		T3	919
full_word	60327	1		T1	755		T2	41		T3	399

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	132517	1		T1	1824		T2	270		T3	1318
auto[TlIntgErrCmd]	98	1		T4	8		T30	3		T26	4
auto[TlIntgErrData]	80	1		T4	6		T30	2		T26	2
auto[TlIntgErrBoth]	92	1		T4	6		T30	5		T26	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	73409	1		T1	255		T2	219		T3	152
auto[1]	59378	1		T1	1569		T2	51		T3	1166

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	49059	1		T1	81		T2	206		T3	59
auto[TlIntgErrNone]	partial	auto[1]	23155	1		T1	988		T2	23		T3	860
auto[TlIntgErrNone]	full_word	auto[0]	24236	1		T1	174		T2	13		T3	93
auto[TlIntgErrNone]	full_word	auto[1]	36067	1		T1	581		T2	28		T3	306
auto[TlIntgErrCmd]	partial	auto[0]	36	1		T4	1		T30	1		T26	1
auto[TlIntgErrCmd]	partial	auto[1]	50	1		T4	6		T30	1		T26	1
auto[TlIntgErrCmd]	full_word	auto[0]	7	1		T4	1		T30	1		T26	2
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T28	1		T29	1		T79	1
auto[TlIntgErrData]	partial	auto[0]	36	1		T4	4		T27	2		T28	1
auto[TlIntgErrData]	partial	auto[1]	40	1		T4	2		T30	1		T26	2
auto[TlIntgErrData]	full_word	auto[0]	1	1		T80	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	3	1		T30	1		T81	1		T82	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1		T4	4		T30	2		T27	5
auto[TlIntgErrBoth]	partial	auto[1]	54	1		T4	1		T30	2		T26	4
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T28	1		T79	1		T82	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T4	1		T30	1		T78	1