Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
22.84	0.00	0.00	91.36		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1822462	11871	0	0
ep_in_enable_rd_A	1822462	3031	0	0
ep_out_enable_rd_A	1822462	3232	0	0
in_iso_rd_A	1822462	3042	0	0
intr_enable_rd_A	1822462	4451	0	0
out_iso_rd_A	1822462	2908	0	0
phy_config_rd_A	1822462	1987	0	0
phy_pins_drive_rd_A	1822462	2627	0	0
rxenable_setup_rd_A	1822462	3020	0	0
set_nak_out_rd_A	1822462	2859	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1822462	11871	0	0
T1	6928	978	0	0
T2	3901	0	0	0
T3	12967	556	0	0
T4	0	7	0	0
T5	0	27	0	0
T7	12306	657	0	0
T8	4733	0	0	0
T13	3587	0	0	0
T14	2344	0	0	0
T15	3251	0	0	0
T20	9809	0	0	0
T21	9170	324	0	0
T22	0	526	0	0
T26	0	3	0	0
T27	0	5	0	0
T30	0	1	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1822462	3031	0	0
T2	3901	75	0	0
T3	12967	0	0	0
T4	34427	0	0	0
T7	12306	0	0	0
T8	4733	19	0	0
T11	0	5	0	0
T13	3587	0	0	0
T14	2344	0	0	0
T15	3251	0	0	0
T20	9809	0	0	0
T21	9170	0	0	0
T26	0	324	0	0
T27	0	286	0	0
T33	0	5	0	0
T35	0	2	0	0
T46	0	21	0	0
T47	0	50	0	0
T62	0	57	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1822462	3232	0	0
T2	3901	30	0	0
T3	12967	0	0	0
T4	34427	0	0	0
T7	12306	0	0	0
T8	4733	2	0	0
T11	0	21	0	0
T13	3587	0	0	0
T14	2344	0	0	0
T15	3251	0	0	0
T20	9809	0	0	0
T21	9170	0	0	0
T25	0	12	0	0
T26	0	356	0	0
T27	0	305	0	0
T33	0	11	0	0
T46	0	4	0	0
T47	0	32	0	0
T62	0	121	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1822462	3042	0	0
T2	3901	10	0	0
T3	12967	1	0	0
T4	34427	0	0	0
T7	12306	0	0	0
T8	4733	15	0	0
T11	0	8	0	0
T13	3587	0	0	0
T14	2344	0	0	0
T15	3251	0	0	0
T20	9809	0	0	0
T21	9170	0	0	0
T26	0	117	0	0
T27	0	219	0	0
T33	0	34	0	0
T46	0	33	0	0
T47	0	22	0	0
T62	0	241	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1822462	4451	0	0
T2	3901	67	0	0
T3	12967	0	0	0
T4	34427	0	0	0
T7	12306	0	0	0
T8	4733	1	0	0
T11	0	10	0	0
T13	3587	0	0	0
T14	2344	11	0	0
T15	3251	0	0	0
T20	9809	0	0	0
T21	9170	0	0	0
T26	0	459	0	0
T27	0	473	0	0
T33	0	35	0	0
T37	0	15	0	0
T46	0	29	0	0
T47	0	34	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1822462	2908	0	0
T2	3901	64	0	0
T3	12967	0	0	0
T4	34427	0	0	0
T7	12306	0	0	0
T8	4733	12	0	0
T11	0	1	0	0
T13	3587	0	0	0
T14	2344	0	0	0
T15	3251	0	0	0
T20	9809	0	0	0
T21	9170	0	0	0
T25	0	9	0	0
T26	0	142	0	0
T27	0	430	0	0
T33	0	11	0	0
T35	0	20	0	0
T47	0	59	0	0
T62	0	38	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1822462	1987	0	0
T2	3901	41	0	0
T3	12967	0	0	0
T4	34427	0	0	0
T7	12306	0	0	0
T8	4733	0	0	0
T11	0	8	0	0
T13	3587	0	0	0
T14	2344	0	0	0
T15	3251	0	0	0
T20	9809	0	0	0
T21	9170	0	0	0
T25	0	11	0	0
T26	0	138	0	0
T27	0	196	0	0
T33	0	3	0	0
T35	0	2	0	0
T46	0	5	0	0
T47	0	28	0	0
T62	0	88	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1822462	2627	0	0
T2	3901	27	0	0
T3	12967	0	0	0
T4	34427	0	0	0
T7	12306	0	0	0
T8	4733	9	0	0
T13	3587	0	0	0
T14	2344	0	0	0
T15	3251	0	0	0
T20	9809	0	0	0
T21	9170	0	0	0
T25	0	6	0	0
T26	0	167	0	0
T27	0	243	0	0
T33	0	27	0	0
T35	0	37	0	0
T46	0	38	0	0
T47	0	27	0	0
T62	0	83	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1822462	3020	0	0
T2	3901	50	0	0
T3	12967	0	0	0
T4	34427	0	0	0
T7	12306	0	0	0
T8	4733	3	0	0
T13	3587	0	0	0
T14	2344	0	0	0
T15	3251	0	0	0
T20	9809	0	0	0
T21	9170	0	0	0
T25	0	38	0	0
T26	0	215	0	0
T27	0	276	0	0
T33	0	27	0	0
T35	0	5	0	0
T46	0	45	0	0
T47	0	35	0	0
T62	0	123	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1822462	2859	0	0
T2	3901	23	0	0
T3	12967	5	0	0
T4	34427	0	0	0
T7	12306	0	0	0
T8	4733	17	0	0
T13	3587	0	0	0
T14	2344	0	0	0
T15	3251	0	0	0
T20	9809	0	0	0
T21	9170	0	0	0
T26	0	251	0	0
T27	0	210	0	0
T33	0	62	0	0
T35	0	13	0	0
T46	0	12	0	0
T47	0	65	0	0
T62	0	138	0	0