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Module Instance : tb.dut.usbdev_avsetupfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
22.84 0.00 0.00 91.36 0.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 0.00 0.00 0.00 0.00


Module Instance : tb.dut.usbdev_avoutfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
22.84 0.00 0.00 91.36 0.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 0.00 0.00 0.00 0.00


Module Instance : tb.dut.usbdev_rxfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
22.84 0.00 0.00 91.36 0.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 0.00 0.00 0.00 0.00


Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
0.00 0.00 0.00 0.00 gen_no_stubbed_memory.u_tlul2sram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 0.00 0.00 0.00 0.00


Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
0.00 0.00 0.00 0.00 gen_no_stubbed_memory.u_tlul2sram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 0.00 0.00 0.00 0.00


Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
0.00 0.00 0.00 0.00 gen_no_stubbed_memory.u_tlul2sram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 0.00 0.00 0.00 0.00

Go back
Module Instances:
tb.dut.usbdev_avsetupfifo
tb.dut.usbdev_avoutfifo
tb.dut.usbdev_rxfifo
tb.dut.u_reg.u_socket.fifo_h.reqfifo
tb.dut.u_reg.u_socket.fifo_h.rspfifo
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo
Line Coverage for Instance : tb.dut.usbdev_avsetupfifo
Line No.TotalCoveredPercent
TOTAL1400.00
ALWAYS69400.00
CONT_ASSIGN81100.00
CONT_ASSIGN82100.00
CONT_ASSIGN100100.00
CONT_ASSIGN101100.00
CONT_ASSIGN120100.00
ALWAYS123200.00
CONT_ASSIGN133100.00
CONT_ASSIGN134100.00
CONT_ASSIGN140100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 0 1
70 0 1
71 0 1
72 0 1
==> MISSING_ELSE
81 0 1
82 0 1
100 0 1
101 0 1
120 0 1
123 0 1
124 0 1
==> MISSING_ELSE
133 0 1
134 0 1
140 0 1


Cond Coverage for Instance : tb.dut.usbdev_avsetupfifo
TotalCoveredPercent
Conditions1400.00
Logical1400.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo
Line No.TotalCoveredPercent
Branches 5 0 0.00
IF 69 3 0 0.00
IF 123 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

Line Coverage for Instance : tb.dut.usbdev_avoutfifo
Line No.TotalCoveredPercent
TOTAL1400.00
ALWAYS69400.00
CONT_ASSIGN81100.00
CONT_ASSIGN82100.00
CONT_ASSIGN100100.00
CONT_ASSIGN101100.00
CONT_ASSIGN120100.00
ALWAYS123200.00
CONT_ASSIGN133100.00
CONT_ASSIGN134100.00
CONT_ASSIGN140100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 0 1
70 0 1
71 0 1
72 0 1
==> MISSING_ELSE
81 0 1
82 0 1
100 0 1
101 0 1
120 0 1
123 0 1
124 0 1
==> MISSING_ELSE
133 0 1
134 0 1
140 0 1


Cond Coverage for Instance : tb.dut.usbdev_avoutfifo
TotalCoveredPercent
Conditions1400.00
Logical1400.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

Branch Coverage for Instance : tb.dut.usbdev_avoutfifo
Line No.TotalCoveredPercent
Branches 5 0 0.00
IF 69 3 0 0.00
IF 123 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

Line Coverage for Instance : tb.dut.usbdev_rxfifo
Line No.TotalCoveredPercent
TOTAL1400.00
ALWAYS69400.00
CONT_ASSIGN81100.00
CONT_ASSIGN82100.00
CONT_ASSIGN100100.00
CONT_ASSIGN101100.00
CONT_ASSIGN120100.00
ALWAYS123200.00
CONT_ASSIGN133100.00
CONT_ASSIGN134100.00
CONT_ASSIGN138100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 0 1
70 0 1
71 0 1
72 0 1
==> MISSING_ELSE
81 0 1
82 0 1
100 0 1
101 0 1
120 0 1
123 0 1
124 0 1
==> MISSING_ELSE
133 0 1
134 0 1
138 0 1


Cond Coverage for Instance : tb.dut.usbdev_rxfifo
TotalCoveredPercent
Conditions1600.00
Logical1600.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1Not Covered

Branch Coverage for Instance : tb.dut.usbdev_rxfifo
Line No.TotalCoveredPercent
Branches 7 0 0.00
TERNARY 138 2 0 0.00
IF 69 3 0 0.00
IF 123 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 1822462 386907 0 0
DepthKnown_A 1822462 1767782 0 0
RvalidKnown_A 1822462 1767782 0 0
WreadyKnown_A 1822462 1767782 0 0
gen_passthru_fifo.paramCheckPass 175 175 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1822462 386907 0 0
T1 6928 3639 0 0
T2 3901 609 0 0
T3 12967 3123 0 0
T7 12306 2339 0 0
T8 4733 591 0 0
T13 3587 40 0 0
T14 2344 40 0 0
T15 3251 22 0 0
T20 9809 3073 0 0
T21 9170 1577 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1822462 1767782 0 0
T1 6928 6869 0 0
T2 3901 3817 0 0
T3 12967 12902 0 0
T7 12306 12210 0 0
T8 4733 4655 0 0
T13 3587 3495 0 0
T14 2344 2247 0 0
T15 3251 3177 0 0
T20 9809 9711 0 0
T21 9170 9096 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1822462 1767782 0 0
T1 6928 6869 0 0
T2 3901 3817 0 0
T3 12967 12902 0 0
T7 12306 12210 0 0
T8 4733 4655 0 0
T13 3587 3495 0 0
T14 2344 2247 0 0
T15 3251 3177 0 0
T20 9809 9711 0 0
T21 9170 9096 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1822462 1767782 0 0
T1 6928 6869 0 0
T2 3901 3817 0 0
T3 12967 12902 0 0
T7 12306 12210 0 0
T8 4733 4655 0 0
T13 3587 3495 0 0
T14 2344 2247 0 0
T15 3251 3177 0 0
T20 9809 9711 0 0
T21 9170 9096 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 175 175 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 1822462 284123 0 0
DepthKnown_A 1822462 1767782 0 0
RvalidKnown_A 1822462 1767782 0 0
WreadyKnown_A 1822462 1767782 0 0
gen_passthru_fifo.paramCheckPass 175 175 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1822462 284123 0 0
T1 6928 1824 0 0
T2 3901 1252 0 0
T3 12967 6515 0 0
T7 12306 4012 0 0
T8 4733 831 0 0
T13 3587 40 0 0
T14 2344 168 0 0
T15 3251 22 0 0
T20 9809 3073 0 0
T21 9170 2697 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1822462 1767782 0 0
T1 6928 6869 0 0
T2 3901 3817 0 0
T3 12967 12902 0 0
T7 12306 12210 0 0
T8 4733 4655 0 0
T13 3587 3495 0 0
T14 2344 2247 0 0
T15 3251 3177 0 0
T20 9809 9711 0 0
T21 9170 9096 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1822462 1767782 0 0
T1 6928 6869 0 0
T2 3901 3817 0 0
T3 12967 12902 0 0
T7 12306 12210 0 0
T8 4733 4655 0 0
T13 3587 3495 0 0
T14 2344 2247 0 0
T15 3251 3177 0 0
T20 9809 9711 0 0
T21 9170 9096 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1822462 1767782 0 0
T1 6928 6869 0 0
T2 3901 3817 0 0
T3 12967 12902 0 0
T7 12306 12210 0 0
T8 4733 4655 0 0
T13 3587 3495 0 0
T14 2344 2247 0 0
T15 3251 3177 0 0
T20 9809 9711 0 0
T21 9170 9096 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 175 175 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 1822462 34654 0 0
DepthKnown_A 1822462 1767782 0 0
RvalidKnown_A 1822462 1767782 0 0
WreadyKnown_A 1822462 1767782 0 0
gen_passthru_fifo.paramCheckPass 175 175 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1822462 34654 0 0
T1 6928 473 0 0
T2 3901 0 0 0
T3 12967 371 0 0
T5 0 863 0 0
T7 12306 778 0 0
T8 4733 0 0 0
T13 3587 0 0 0
T14 2344 0 0 0
T15 3251 0 0 0
T20 9809 3070 0 0
T21 9170 328 0 0
T22 0 289 0 0
T23 0 920 0 0
T24 0 410 0 0
T25 0 286 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1822462 1767782 0 0
T1 6928 6869 0 0
T2 3901 3817 0 0
T3 12967 12902 0 0
T7 12306 12210 0 0
T8 4733 4655 0 0
T13 3587 3495 0 0
T14 2344 2247 0 0
T15 3251 3177 0 0
T20 9809 9711 0 0
T21 9170 9096 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1822462 1767782 0 0
T1 6928 6869 0 0
T2 3901 3817 0 0
T3 12967 12902 0 0
T7 12306 12210 0 0
T8 4733 4655 0 0
T13 3587 3495 0 0
T14 2344 2247 0 0
T15 3251 3177 0 0
T20 9809 9711 0 0
T21 9170 9096 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1822462 1767782 0 0
T1 6928 6869 0 0
T2 3901 3817 0 0
T3 12967 12902 0 0
T7 12306 12210 0 0
T8 4733 4655 0 0
T13 3587 3495 0 0
T14 2344 2247 0 0
T15 3251 3177 0 0
T20 9809 9711 0 0
T21 9170 9096 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 175 175 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 1822462 51525 0 0
DepthKnown_A 1822462 1767782 0 0
RvalidKnown_A 1822462 1767782 0 0
WreadyKnown_A 1822462 1767782 0 0
gen_passthru_fifo.paramCheckPass 175 175 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1822462 51525 0 0
T1 6928 400 0 0
T2 3901 0 0 0
T3 12967 1525 0 0
T5 0 476 0 0
T7 12306 1748 0 0
T8 4733 0 0 0
T13 3587 0 0 0
T14 2344 0 0 0
T15 3251 0 0 0
T20 9809 3070 0 0
T21 9170 784 0 0
T22 0 285 0 0
T23 0 1615 0 0
T24 0 381 0 0
T25 0 663 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1822462 1767782 0 0
T1 6928 6869 0 0
T2 3901 3817 0 0
T3 12967 12902 0 0
T7 12306 12210 0 0
T8 4733 4655 0 0
T13 3587 3495 0 0
T14 2344 2247 0 0
T15 3251 3177 0 0
T20 9809 9711 0 0
T21 9170 9096 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1822462 1767782 0 0
T1 6928 6869 0 0
T2 3901 3817 0 0
T3 12967 12902 0 0
T7 12306 12210 0 0
T8 4733 4655 0 0
T13 3587 3495 0 0
T14 2344 2247 0 0
T15 3251 3177 0 0
T20 9809 9711 0 0
T21 9170 9096 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1822462 1767782 0 0
T1 6928 6869 0 0
T2 3901 3817 0 0
T3 12967 12902 0 0
T7 12306 12210 0 0
T8 4733 4655 0 0
T13 3587 3495 0 0
T14 2344 2247 0 0
T15 3251 3177 0 0
T20 9809 9711 0 0
T21 9170 9096 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 175 175 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 1822462 341869 0 0
DepthKnown_A 1822462 1767782 0 0
RvalidKnown_A 1822462 1767782 0 0
WreadyKnown_A 1822462 1767782 0 0
gen_passthru_fifo.paramCheckPass 175 175 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1822462 341869 0 0
T1 6928 2525 0 0
T2 3901 609 0 0
T3 12967 2084 0 0
T7 12306 1029 0 0
T8 4733 591 0 0
T13 3587 40 0 0
T14 2344 40 0 0
T15 3251 22 0 0
T20 9809 3 0 0
T21 9170 1000 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1822462 1767782 0 0
T1 6928 6869 0 0
T2 3901 3817 0 0
T3 12967 12902 0 0
T7 12306 12210 0 0
T8 4733 4655 0 0
T13 3587 3495 0 0
T14 2344 2247 0 0
T15 3251 3177 0 0
T20 9809 9711 0 0
T21 9170 9096 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1822462 1767782 0 0
T1 6928 6869 0 0
T2 3901 3817 0 0
T3 12967 12902 0 0
T7 12306 12210 0 0
T8 4733 4655 0 0
T13 3587 3495 0 0
T14 2344 2247 0 0
T15 3251 3177 0 0
T20 9809 9711 0 0
T21 9170 9096 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1822462 1767782 0 0
T1 6928 6869 0 0
T2 3901 3817 0 0
T3 12967 12902 0 0
T7 12306 12210 0 0
T8 4733 4655 0 0
T13 3587 3495 0 0
T14 2344 2247 0 0
T15 3251 3177 0 0
T20 9809 9711 0 0
T21 9170 9096 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 175 175 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 1822462 232598 0 0
DepthKnown_A 1822462 1767782 0 0
RvalidKnown_A 1822462 1767782 0 0
WreadyKnown_A 1822462 1767782 0 0
gen_passthru_fifo.paramCheckPass 175 175 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1822462 232598 0 0
T1 6928 1424 0 0
T2 3901 1252 0 0
T3 12967 4990 0 0
T7 12306 2264 0 0
T8 4733 831 0 0
T13 3587 40 0 0
T14 2344 168 0 0
T15 3251 22 0 0
T20 9809 3 0 0
T21 9170 1913 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1822462 1767782 0 0
T1 6928 6869 0 0
T2 3901 3817 0 0
T3 12967 12902 0 0
T7 12306 12210 0 0
T8 4733 4655 0 0
T13 3587 3495 0 0
T14 2344 2247 0 0
T15 3251 3177 0 0
T20 9809 9711 0 0
T21 9170 9096 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1822462 1767782 0 0
T1 6928 6869 0 0
T2 3901 3817 0 0
T3 12967 12902 0 0
T7 12306 12210 0 0
T8 4733 4655 0 0
T13 3587 3495 0 0
T14 2344 2247 0 0
T15 3251 3177 0 0
T20 9809 9711 0 0
T21 9170 9096 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1822462 1767782 0 0
T1 6928 6869 0 0
T2 3901 3817 0 0
T3 12967 12902 0 0
T7 12306 12210 0 0
T8 4733 4655 0 0
T13 3587 3495 0 0
T14 2344 2247 0 0
T15 3251 3177 0 0
T20 9809 9711 0 0
T21 9170 9096 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 175 175 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo
Line No.TotalCoveredPercent
TOTAL1500.00
ALWAYS69400.00
CONT_ASSIGN81100.00
CONT_ASSIGN82100.00
CONT_ASSIGN100100.00
CONT_ASSIGN101100.00
CONT_ASSIGN108100.00
ALWAYS111200.00
CONT_ASSIGN116100.00
CONT_ASSIGN133100.00
CONT_ASSIGN134100.00
CONT_ASSIGN138100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 0 1
70 0 1
71 0 1
72 0 1
==> MISSING_ELSE
81 0 1
82 0 1
100 0 1
101 0 1
108 0 1
111 0 1
112 0 1
==> MISSING_ELSE
116 0 1
133 0 1
134 0 1
138 0 1


Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo
TotalCoveredPercent
Conditions1600.00
Logical1600.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1Not Covered

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo
Line No.TotalCoveredPercent
Branches 7 0 0.00
TERNARY 138 2 0 0.00
IF 69 3 0 0.00
IF 123 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo
Line No.TotalCoveredPercent
TOTAL1500.00
ALWAYS69400.00
CONT_ASSIGN81100.00
CONT_ASSIGN82100.00
CONT_ASSIGN100100.00
CONT_ASSIGN101100.00
CONT_ASSIGN108100.00
ALWAYS111200.00
CONT_ASSIGN116100.00
CONT_ASSIGN133100.00
CONT_ASSIGN134100.00
CONT_ASSIGN138100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 0 1
70 0 1
71 0 1
72 0 1
==> MISSING_ELSE
81 0 1
82 0 1
100 0 1
101 0 1
108 0 1
111 0 1
112 0 1
==> MISSING_ELSE
116 0 1
133 0 1
134 0 1
138 0 1


Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo
TotalCoveredPercent
Conditions1600.00
Logical1600.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1Not Covered

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo
Line No.TotalCoveredPercent
Branches 7 0 0.00
TERNARY 138 2 0 0.00
IF 69 3 0 0.00
IF 123 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo
Line No.TotalCoveredPercent
TOTAL1500.00
ALWAYS69400.00
CONT_ASSIGN81100.00
CONT_ASSIGN82100.00
CONT_ASSIGN100100.00
CONT_ASSIGN101100.00
CONT_ASSIGN108100.00
ALWAYS111200.00
CONT_ASSIGN116100.00
CONT_ASSIGN130100.00
CONT_ASSIGN131100.00
CONT_ASSIGN138100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 0 1
70 0 1
71 0 1
72 0 1
==> MISSING_ELSE
81 0 1
82 0 1
100 0 1
101 0 1
108 0 1
111 0 1
112 0 1
==> MISSING_ELSE
116 0 1
130 0 1
131 0 1
138 0 1


Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo
TotalCoveredPercent
Conditions2400.00
Logical2400.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1Not Covered

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo
Line No.TotalCoveredPercent
Branches 9 0 0.00
TERNARY 130 2 0 0.00
TERNARY 138 2 0 0.00
IF 69 3 0 0.00
IF 111 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%