e9ae10fb42| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | usbdev_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | usbdev_csr_hw_reset | 0.990s | 230.417us | 5 | 5 | 100.00 |
| V1 | csr_rw | usbdev_csr_rw | 1.100s | 111.180us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | usbdev_csr_bit_bash | 9.480s | 1.872ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | usbdev_csr_aliasing | 3.540s | 297.921us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | usbdev_csr_mem_rw_with_rand_reset | 2.880s | 107.961us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | usbdev_csr_rw | 1.100s | 111.180us | 20 | 20 | 100.00 |
| usbdev_csr_aliasing | 3.540s | 297.921us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | usbdev_mem_walk | 3.860s | 171.260us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | usbdev_mem_partial_access | 2.380s | 168.584us | 5 | 5 | 100.00 |
| V1 | TOTAL | 65 | 115 | 56.52 | |||
| V2 | in_trans | usbdev_in_trans | 0 | 50 | 0.00 | ||
| V2 | data_toggle_clear | usbdev_data_toggle_clear | 0 | 50 | 0.00 | ||
| V2 | phy_pins_sense | usbdev_phy_pins_sense | 0 | 50 | 0.00 | ||
| V2 | av_buffer | usbdev_av_buffer | 0 | 50 | 0.00 | ||
| V2 | rx_fifo | usbdev_pkt_buffer | 0 | 50 | 0.00 | ||
| V2 | phy_config_tx_osc_test_mode | usbdev_phy_config_tx_osc_test_mode | 0 | 1 | 0.00 | ||
| V2 | phy_config_eop_single_bit_handling | usbdev_phy_config_eop_single_bit_handling | 0 | 1 | 0.00 | ||
| V2 | phy_config_pinflip | usbdev_phy_config_pinflip | 0 | 50 | 0.00 | ||
| V2 | phy_config_rand_bus_type | usbdev_phy_config_rand_bus_type | 0 | 5 | 0.00 | ||
| V2 | phy_config_rx_dp_dn | usbdev_phy_config_rx_dp_dn | 0 | 1 | 0.00 | ||
| V2 | phy_config_tx_use_d_se0 | usbdev_phy_config_tx_use_d_se0 | 0 | 1 | 0.00 | ||
| V2 | phy_config_usb_ref_disable | usbdev_phy_config_usb_ref_disable | 0 | 50 | 0.00 | ||
| V2 | max_length_out_transaction | usbdev_max_length_out_transaction | 0 | 50 | 0.00 | ||
| V2 | max_length_in_transaction | usbdev_max_length_in_transaction | 0 | 50 | 0.00 | ||
| V2 | min_length_out_transaction | usbdev_min_length_out_transaction | 0 | 50 | 0.00 | ||
| V2 | min_length_in_transaction | usbdev_min_length_in_transaction | 0 | 50 | 0.00 | ||
| V2 | random_length_out_transaction | usbdev_random_length_out_transaction | 0 | 50 | 0.00 | ||
| V2 | random_length_in_transaction | usbdev_random_length_in_transaction | 0 | 50 | 0.00 | ||
| V2 | out_stall | usbdev_out_stall | 0 | 50 | 0.00 | ||
| V2 | in_stall | usbdev_in_stall | 0 | 50 | 0.00 | ||
| V2 | out_iso | usbdev_out_iso | 0 | 50 | 0.00 | ||
| V2 | in_iso | usbdev_in_iso | 0 | 50 | 0.00 | ||
| V2 | pkt_received | usbdev_pkt_received | 0 | 50 | 0.00 | ||
| V2 | pkt_sent | usbdev_pkt_sent | 0 | 50 | 0.00 | ||
| V2 | disconnected | usbdev_disconnected | 0 | 50 | 0.00 | ||
| V2 | host_lost | usbdev_host_lost | 0 | 1 | 0.00 | ||
| V2 | link_reset | usbdev_link_reset | 0 | 1 | 0.00 | ||
| V2 | link_suspend | usbdev_link_suspend | 0 | 50 | 0.00 | ||
| V2 | link_resume | usbdev_link_resume | 0 | 50 | 0.00 | ||
| V2 | av_empty | usbdev_av_empty | 0 | 5 | 0.00 | ||
| V2 | rx_full | usbdev_rx_full | 0 | 1 | 0.00 | ||
| V2 | av_overflow | usbdev_av_overflow | 0 | 5 | 0.00 | ||
| V2 | link_in_err | usbdev_link_in_err | 0 | 50 | 0.00 | ||
| V2 | rx_crc_err | usbdev_rx_crc_err | 0 | 50 | 0.00 | ||
| V2 | rx_pid_err | usbdev_rx_pid_err | 0 | 5 | 0.00 | ||
| V2 | rx_bitstuff_err | usbdev_bitstuff_err | 0 | 50 | 0.00 | ||
| V2 | link_out_err | usbdev_link_out_err | 0 | 1 | 0.00 | ||
| V2 | enable | usbdev_enable | 0 | 50 | 0.00 | ||
| V2 | resume_link_active | usbdev_resume_link_active | 0 | 1 | 0.00 | ||
| V2 | device_address | usbdev_device_address | 0 | 50 | 0.00 | ||
| V2 | invalid_data1_data0_toggle_test | usbdev_invalid_data1_data0_toggle_test | 0 | 1 | 0.00 | ||
| V2 | setup_stage | usbdev_setup_stage | 0 | 50 | 0.00 | ||
| V2 | endpoint_access | usbdev_endpoint_access | 0 | 50 | 0.00 | ||
| V2 | disable_endpoint | usbdev_disable_endpoint | 0 | 50 | 0.00 | ||
| V2 | out_trans_nak | usbdev_out_trans_nak | 0 | 50 | 0.00 | ||
| V2 | setup_trans_ignored | usbdev_setup_trans_ignored | 0 | 50 | 0.00 | ||
| V2 | nak_trans | usbdev_nak_trans | 0 | 50 | 0.00 | ||
| V2 | stall_trans | usbdev_stall_trans | 0 | 50 | 0.00 | ||
| V2 | setup_priority_over_stall_response | usbdev_setup_priority_over_stall_response | 0 | 5 | 0.00 | ||
| V2 | stall_priority_over_nak | usbdev_stall_priority_over_nak | 0 | 50 | 0.00 | ||
| V2 | pending_in_trans | usbdev_pending_in_trans | 0 | 50 | 0.00 | ||
| V2 | streaming_test | usbdev_streaming_out | 0 | 50 | 0.00 | ||
| V2 | max_clock_error_untracked | max_clock_error_untracked | 0 | 0 | -- | ||
| V2 | max_clock_error_tracking | max_clock_error_tracking | 0 | 0 | -- | ||
| V2 | max_phase_error | max_phase_error | 0 | 0 | -- | ||
| V2 | min_inter_pkt_delay | usbdev_min_inter_pkt_delay | 0 | 50 | 0.00 | ||
| V2 | max_inter_pkt_delay | usbdev_max_inter_pkt_delay | 0 | 50 | 0.00 | ||
| V2 | device_timeout_missing_host_handshake | device_timeout_missing_host_handshake | 0 | 0 | -- | ||
| V2 | device_timeout | device_timeout | 0 | 0 | -- | ||
| V2 | packet_buffer | usbdev_pkt_buffer | 0 | 50 | 0.00 | ||
| V2 | nak_to_out_trans_when_avbuffer_empty_rxfifo_full | usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full | 0 | 1 | 0.00 | ||
| V2 | aon_wake_resume | usbdev_aon_wake_resume | 0 | 50 | 0.00 | ||
| V2 | aon_wake_reset | usbdev_aon_wake_reset | 0 | 50 | 0.00 | ||
| V2 | aon_wake_disconnect | usbdev_aon_wake_disconnect | 0 | 50 | 0.00 | ||
| V2 | invalid_sync | usbdev_invalid_sync | 0 | 50 | 0.00 | ||
| V2 | spurious_pids_ignored | usbdev_spurious_pids_ignored | 0 | 50 | 0.00 | ||
| V2 | low_speed_traffic | usbdev_low_speed_traffic | 0 | 50 | 0.00 | ||
| V2 | rand_bus_resets | usbdev_rand_bus_resets | 0 | 10 | 0.00 | ||
| V2 | rand_disconnects | usbdev_rand_bus_disconnects | 0 | 10 | 0.00 | ||
| V2 | rand_suspends | usbdev_rand_suspends | 0 | 10 | 0.00 | ||
| V2 | max_usb_traffic | usbdev_max_usb_traffic | 0 | 50 | 0.00 | ||
| V2 | stress_usb_traffic | usbdev_stress_usb_traffic | 0 | 5 | 0.00 | ||
| V2 | in_packet_retraction | in_packet_retraction | 0 | 0 | -- | ||
| V2 | data_toggle_restore | usbdev_data_toggle_restore | 0 | 50 | 0.00 | ||
| V2 | setup_priority | usbdev_setup_priority | 0 | 5 | 0.00 | ||
| V2 | fifo_resets | usbdev_fifo_rst | 0 | 50 | 0.00 | ||
| V2 | intr_test | usbdev_intr_test | 0.790s | 73.617us | 50 | 50 | 100.00 |
| V2 | alert_test | usbdev_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | usbdev_tl_errors | 3.540s | 370.179us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | usbdev_tl_errors | 3.540s | 370.179us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | usbdev_csr_hw_reset | 0.990s | 230.417us | 5 | 5 | 100.00 |
| usbdev_csr_rw | 1.100s | 111.180us | 20 | 20 | 100.00 | ||
| usbdev_csr_aliasing | 3.540s | 297.921us | 5 | 5 | 100.00 | ||
| usbdev_same_csr_outstanding | 1.870s | 267.753us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | usbdev_csr_hw_reset | 0.990s | 230.417us | 5 | 5 | 100.00 |
| usbdev_csr_rw | 1.100s | 111.180us | 20 | 20 | 100.00 | ||
| usbdev_csr_aliasing | 3.540s | 297.921us | 5 | 5 | 100.00 | ||
| usbdev_same_csr_outstanding | 1.870s | 267.753us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 90 | 2616 | 3.44 | |||
| V2S | tl_intg_err | usbdev_sec_cm | 0 | 5 | 0.00 | ||
| usbdev_tl_intg_err | 5.800s | 1.407ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | usbdev_tl_intg_err | 5.800s | 1.407ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 20 | 25 | 80.00 | |||
| V3 | dpi_config_host | usbdev_dpi_config_host | 0 | 1 | 0.00 | ||
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| Unmapped tests | usbdev_stress_all_with_rand_reset | 0 | 10 | 0.00 | |||
| usbdev_stress_all | 0 | 50 | 0.00 | ||||
| TOTAL | 175 | 2817 | 6.21 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 2 | 2 | 0 | 0.00 |
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 79 | 73 | 3 | 3.80 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 67.93 | 65.32 | 59.60 | 86.78 | 0.00 | 69.84 | 97.77 | 96.22 |
launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = The service is currently unavailable. has 1321 failures:
0.usbdev_aon_wake_disconnect.76900261391211058533652580213171999089432588102490507400509829093440497276559
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_aon_wake_disconnect/latest/run.log
2.usbdev_aon_wake_disconnect.34349269610494231055937641567070714912717482024923720113392710176823221506039
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/2.usbdev_aon_wake_disconnect/latest/run.log
... and 23 more failures.
0.usbdev_aon_wake_resume.22622301085121897483036451306764357297251859466538901050039487093111592409409
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_aon_wake_resume/latest/run.log
2.usbdev_aon_wake_resume.53964932078710213651932974754418186045180075504748733560262525508966937780210
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/2.usbdev_aon_wake_resume/latest/run.log
... and 23 more failures.
0.usbdev_av_empty.104080445856927929221085635927055372700324456025129077425037326661121926178520
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_av_empty/latest/run.log
2.usbdev_av_empty.33318506955386396323967365042195492756798112687339248191595240701363831323103
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/2.usbdev_av_empty/latest/run.log
... and 1 more failures.
0.usbdev_bitstuff_err.22836362711733276372618018975797267734010716238484183093262268756855712033199
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_bitstuff_err/latest/run.log
2.usbdev_bitstuff_err.106527418966665437280280104785344478584455003484671348581033597076362180426327
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/2.usbdev_bitstuff_err/latest/run.log
... and 23 more failures.
0.usbdev_data_toggle_restore.61869232112988932607763482392883422955637322397169068841369654987701629487899
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_data_toggle_restore/latest/run.log
2.usbdev_data_toggle_restore.82470534451529926201550086812063620988688534893550389978109037470301985528281
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/2.usbdev_data_toggle_restore/latest/run.log
... and 23 more failures.
Job killed most likely because its dependent job failed. has 1321 failures:
0.usbdev_aon_wake_reset.40410320752801510619912760067922652868551053068996956291211897297856546751856
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_aon_wake_reset/latest/run.log
2.usbdev_aon_wake_reset.93416585939717508225082762723693809477980605354687965064301562606961720645109
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/2.usbdev_aon_wake_reset/latest/run.log
... and 23 more failures.
0.usbdev_av_buffer.14440761185453737282512233067695407982030467634996142556693425709948749630175
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_av_buffer/latest/run.log
2.usbdev_av_buffer.84455005959674133469107378436081761330456729159082201212743863890609731916669
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/2.usbdev_av_buffer/latest/run.log
... and 23 more failures.
0.usbdev_av_overflow.98462935861233480360186735202923431577221398837038713276067573447624301801403
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_av_overflow/latest/run.log
2.usbdev_av_overflow.29353802672640707279762552432440946332962776197753509944696549078633582374618
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/2.usbdev_av_overflow/latest/run.log
... and 1 more failures.
0.usbdev_data_toggle_clear.76520477492177922972235026925180630574249957629981159915602854115455050231130
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_data_toggle_clear/latest/run.log
2.usbdev_data_toggle_clear.97785546535818969028183185557734462002687215912380259898514744130409273254817
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/2.usbdev_data_toggle_clear/latest/run.log
... and 23 more failures.
0.usbdev_device_address.84721916435587935687078823744950244888724474647813319253748897281861014064582
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_device_address/latest/run.log
2.usbdev_device_address.19548458423059852221498938295384951543178077810836822830131279074652574750049
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/2.usbdev_device_address/latest/run.log
... and 23 more failures.