c8985d6745| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | usbdev_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | usbdev_csr_hw_reset | 0.900s | 160.396us | 5 | 5 | 100.00 |
| V1 | csr_rw | usbdev_csr_rw | 1.060s | 100.422us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | usbdev_csr_bit_bash | 7.390s | 979.414us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | usbdev_csr_aliasing | 3.390s | 322.214us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | usbdev_csr_mem_rw_with_rand_reset | 2.900s | 109.980us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | usbdev_csr_rw | 1.060s | 100.422us | 20 | 20 | 100.00 |
| usbdev_csr_aliasing | 3.390s | 322.214us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | usbdev_mem_walk | 4.300s | 542.484us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | usbdev_mem_partial_access | 2.340s | 215.184us | 5 | 5 | 100.00 |
| V1 | TOTAL | 65 | 115 | 56.52 | |||
| V2 | in_trans | usbdev_in_trans | 0 | 50 | 0.00 | ||
| V2 | data_toggle_clear | usbdev_data_toggle_clear | 0 | 50 | 0.00 | ||
| V2 | phy_pins_sense | usbdev_phy_pins_sense | 0 | 50 | 0.00 | ||
| V2 | av_buffer | usbdev_av_buffer | 0 | 50 | 0.00 | ||
| V2 | rx_fifo | usbdev_pkt_buffer | 0 | 50 | 0.00 | ||
| V2 | phy_config_tx_osc_test_mode | usbdev_phy_config_tx_osc_test_mode | 0 | 1 | 0.00 | ||
| V2 | phy_config_eop_single_bit_handling | usbdev_phy_config_eop_single_bit_handling | 0 | 1 | 0.00 | ||
| V2 | phy_config_pinflip | usbdev_phy_config_pinflip | 0 | 50 | 0.00 | ||
| V2 | phy_config_rand_bus_type | usbdev_phy_config_rand_bus_type | 0 | 5 | 0.00 | ||
| V2 | phy_config_rx_dp_dn | usbdev_phy_config_rx_dp_dn | 0 | 1 | 0.00 | ||
| V2 | phy_config_tx_use_d_se0 | usbdev_phy_config_tx_use_d_se0 | 0 | 1 | 0.00 | ||
| V2 | phy_config_usb_ref_disable | usbdev_phy_config_usb_ref_disable | 0 | 50 | 0.00 | ||
| V2 | max_length_out_transaction | usbdev_max_length_out_transaction | 0 | 50 | 0.00 | ||
| usbdev_stream_len_max | 0 | 50 | 0.00 | ||||
| V2 | max_length_in_transaction | usbdev_max_length_in_transaction | 0 | 50 | 0.00 | ||
| V2 | min_length_out_transaction | usbdev_min_length_out_transaction | 0 | 50 | 0.00 | ||
| V2 | min_length_in_transaction | usbdev_min_length_in_transaction | 0 | 50 | 0.00 | ||
| V2 | random_length_out_transaction | usbdev_random_length_out_transaction | 0 | 50 | 0.00 | ||
| V2 | random_length_in_transaction | usbdev_random_length_in_transaction | 0 | 50 | 0.00 | ||
| V2 | out_stall | usbdev_out_stall | 0 | 50 | 0.00 | ||
| V2 | in_stall | usbdev_in_stall | 0 | 50 | 0.00 | ||
| V2 | out_iso | usbdev_out_iso | 0 | 50 | 0.00 | ||
| V2 | in_iso | usbdev_in_iso | 0 | 50 | 0.00 | ||
| V2 | pkt_received | usbdev_pkt_received | 0 | 50 | 0.00 | ||
| V2 | pkt_sent | usbdev_pkt_sent | 0 | 50 | 0.00 | ||
| V2 | disconnected | usbdev_disconnected | 0 | 50 | 0.00 | ||
| V2 | host_lost | usbdev_host_lost | 0 | 1 | 0.00 | ||
| V2 | link_reset | usbdev_link_reset | 0 | 1 | 0.00 | ||
| V2 | link_suspend | usbdev_link_suspend | 0 | 50 | 0.00 | ||
| V2 | link_resume | usbdev_link_resume | 0 | 50 | 0.00 | ||
| V2 | av_empty | usbdev_av_empty | 0 | 5 | 0.00 | ||
| V2 | rx_full | usbdev_rx_full | 0 | 50 | 0.00 | ||
| V2 | av_overflow | usbdev_av_overflow | 0 | 5 | 0.00 | ||
| V2 | link_in_err | usbdev_link_in_err | 0 | 50 | 0.00 | ||
| V2 | rx_crc_err | usbdev_rx_crc_err | 0 | 50 | 0.00 | ||
| V2 | rx_pid_err | usbdev_rx_pid_err | 0 | 5 | 0.00 | ||
| V2 | rx_bitstuff_err | usbdev_bitstuff_err | 0 | 50 | 0.00 | ||
| V2 | link_out_err | usbdev_link_out_err | 0 | 1 | 0.00 | ||
| V2 | enable | usbdev_enable | 0 | 50 | 0.00 | ||
| V2 | resume_link_active | usbdev_resume_link_active | 0 | 1 | 0.00 | ||
| V2 | device_address | usbdev_device_address | 0 | 50 | 0.00 | ||
| V2 | invalid_data1_data0_toggle_test | usbdev_invalid_data1_data0_toggle_test | 0 | 1 | 0.00 | ||
| V2 | setup_stage | usbdev_setup_stage | 0 | 50 | 0.00 | ||
| V2 | endpoint_access | usbdev_endpoint_access | 0 | 50 | 0.00 | ||
| V2 | disable_endpoint | usbdev_disable_endpoint | 0 | 50 | 0.00 | ||
| V2 | endpoint_types | usbdev_endpoint_types | 0 | 200 | 0.00 | ||
| V2 | out_trans_nak | usbdev_out_trans_nak | 0 | 50 | 0.00 | ||
| V2 | setup_trans_ignored | usbdev_setup_trans_ignored | 0 | 50 | 0.00 | ||
| V2 | nak_trans | usbdev_nak_trans | 0 | 50 | 0.00 | ||
| V2 | stall_trans | usbdev_stall_trans | 0 | 50 | 0.00 | ||
| V2 | setup_priority_over_stall_response | usbdev_setup_priority_over_stall_response | 0 | 5 | 0.00 | ||
| V2 | stall_priority_over_nak | usbdev_stall_priority_over_nak | 0 | 50 | 0.00 | ||
| V2 | pending_in_trans | usbdev_pending_in_trans | 0 | 50 | 0.00 | ||
| V2 | streaming_test | usbdev_streaming_out | 0 | 50 | 0.00 | ||
| V2 | max_clock_error_untracked | usbdev_freq_hiclk | 0 | 5 | 0.00 | ||
| usbdev_freq_loclk | 0 | 5 | 0.00 | ||||
| V2 | max_clock_error_tracking | usbdev_freq_hiclk_max | 0 | 5 | 0.00 | ||
| usbdev_freq_loclk_max | 0 | 5 | 0.00 | ||||
| V2 | max_phase_error | usbdev_freq_phase | 0 | 5 | 0.00 | ||
| V2 | min_inter_pkt_delay | usbdev_min_inter_pkt_delay | 0 | 50 | 0.00 | ||
| V2 | max_inter_pkt_delay | usbdev_max_inter_pkt_delay | 0 | 50 | 0.00 | ||
| V2 | device_timeout_missing_host_handshake | usbdev_timeout_missing_host_handshake | 0 | 50 | 0.00 | ||
| V2 | device_timeout | usbdev_device_timeout | 0 | 50 | 0.00 | ||
| V2 | packet_buffer | usbdev_pkt_buffer | 0 | 50 | 0.00 | ||
| V2 | nak_to_out_trans_when_avbuffer_empty_rxfifo_full | usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full | 0 | 1 | 0.00 | ||
| V2 | aon_wake_resume | usbdev_aon_wake_resume | 0 | 50 | 0.00 | ||
| V2 | aon_wake_reset | usbdev_aon_wake_reset | 0 | 50 | 0.00 | ||
| V2 | aon_wake_disconnect | usbdev_aon_wake_disconnect | 0 | 50 | 0.00 | ||
| V2 | invalid_sync | usbdev_invalid_sync | 0 | 50 | 0.00 | ||
| V2 | spurious_pids_ignored | usbdev_spurious_pids_ignored | 0 | 50 | 0.00 | ||
| V2 | low_speed_traffic | usbdev_low_speed_traffic | 0 | 50 | 0.00 | ||
| V2 | rand_bus_resets | usbdev_rand_bus_resets | 0 | 10 | 0.00 | ||
| V2 | rand_disconnects | usbdev_rand_bus_disconnects | 0 | 10 | 0.00 | ||
| V2 | rand_suspends | usbdev_rand_suspends | 0 | 10 | 0.00 | ||
| V2 | max_usb_traffic | usbdev_max_non_iso_usb_traffic | 0 | 25 | 0.00 | ||
| usbdev_max_usb_traffic | 0 | 15 | 0.00 | ||||
| V2 | stress_usb_traffic | usbdev_stress_usb_traffic | 0 | 5 | 0.00 | ||
| V2 | in_packet_retraction | usbdev_iso_retraction | 0 | 50 | 0.00 | ||
| V2 | data_toggle_restore | usbdev_data_toggle_restore | 0 | 50 | 0.00 | ||
| V2 | setup_priority | usbdev_setup_priority | 0 | 5 | 0.00 | ||
| V2 | fifo_resets | usbdev_fifo_rst | 0 | 50 | 0.00 | ||
| V2 | intr_test | usbdev_intr_test | 0.870s | 54.439us | 50 | 50 | 100.00 |
| V2 | alert_test | usbdev_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | usbdev_tl_errors | 3.580s | 363.995us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | usbdev_tl_errors | 3.580s | 363.995us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | usbdev_csr_hw_reset | 0.900s | 160.396us | 5 | 5 | 100.00 |
| usbdev_csr_rw | 1.060s | 100.422us | 20 | 20 | 100.00 | ||
| usbdev_csr_aliasing | 3.390s | 322.214us | 5 | 5 | 100.00 | ||
| usbdev_same_csr_outstanding | 1.830s | 273.199us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | usbdev_csr_hw_reset | 0.900s | 160.396us | 5 | 5 | 100.00 |
| usbdev_csr_rw | 1.060s | 100.422us | 20 | 20 | 100.00 | ||
| usbdev_csr_aliasing | 3.390s | 322.214us | 5 | 5 | 100.00 | ||
| usbdev_same_csr_outstanding | 1.830s | 273.199us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 90 | 3080 | 2.92 | |||
| V2S | tl_intg_err | usbdev_sec_cm | 0 | 5 | 0.00 | ||
| usbdev_tl_intg_err | 5.200s | 826.883us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | usbdev_tl_intg_err | 5.200s | 826.883us | 20 | 20 | 100.00 |
| V2S | TOTAL | 20 | 25 | 80.00 | |||
| V3 | dpi_config_host | usbdev_dpi_config_host | 0 | 1 | 0.00 | ||
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| Unmapped tests | usbdev_stress_all_with_rand_reset | 0 | 10 | 0.00 | |||
| usbdev_stress_all | 0 | 50 | 0.00 | ||||
| TOTAL | 175 | 3281 | 5.33 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 2 | 2 | 0 | 0.00 |
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 84 | 84 | 3 | 3.57 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 60.90 | 65.32 | 59.58 | 86.57 | 0.00 | 69.84 | 97.77 | 47.24 |
launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = The service is currently unavailable. has 1553 failures:
0.usbdev_aon_wake_disconnect.79932504794921899968125940234147104309885459097992590655486849356284896727636
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_aon_wake_disconnect/latest/run.log
1.usbdev_aon_wake_disconnect.114913652659178070583807481374844186230507950856068266515237784821667454961624
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/1.usbdev_aon_wake_disconnect/latest/run.log
... and 41 more failures.
0.usbdev_aon_wake_resume.44067393557333275009236757868071899157433473894306744996902056268734819190832
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_aon_wake_resume/latest/run.log
1.usbdev_aon_wake_resume.23871810941659573395932980027204940121415503696604695332234128823541056226267
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/1.usbdev_aon_wake_resume/latest/run.log
... and 41 more failures.
0.usbdev_av_empty.90471029002311379890358635863350111067380253210975262906000240444119423834169
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_av_empty/latest/run.log
1.usbdev_av_empty.30474311405681489720856264837425012857088489408659129752685863763560537371165
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/1.usbdev_av_empty/latest/run.log
... and 1 more failures.
0.usbdev_bitstuff_err.104467497969259083548661223695232590265575045175631395234612017336794160286006
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_bitstuff_err/latest/run.log
1.usbdev_bitstuff_err.8938608371566229123151352380899203793780076540491526569736827611297281431480
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/1.usbdev_bitstuff_err/latest/run.log
... and 41 more failures.
0.usbdev_data_toggle_restore.53423197620567995172424736343136887942473805143193123284760707289461272952583
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_data_toggle_restore/latest/run.log
1.usbdev_data_toggle_restore.10092600438118725947823314263657361341340776803245534069703513501596940573342
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/1.usbdev_data_toggle_restore/latest/run.log
... and 41 more failures.
Job killed most likely because its dependent job failed. has 1553 failures:
0.usbdev_aon_wake_reset.41325733016329605438254201216026105283460194174694463880567810067296088755534
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_aon_wake_reset/latest/run.log
1.usbdev_aon_wake_reset.68157955833437819921610872284711189370608273753565315519404963721965128712067
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/1.usbdev_aon_wake_reset/latest/run.log
... and 41 more failures.
0.usbdev_av_buffer.115044931385296685750209803617520761971907980004383635647093387512053657241566
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_av_buffer/latest/run.log
1.usbdev_av_buffer.79764749056990555568116389157438024518554329904565687300011004788168811064572
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/1.usbdev_av_buffer/latest/run.log
... and 41 more failures.
0.usbdev_av_overflow.71288177436191777431384873538820214025668957262141624127388821765519763872687
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_av_overflow/latest/run.log
1.usbdev_av_overflow.39294904952430548262277914629126773547279473714436767419835830499676345130521
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/1.usbdev_av_overflow/latest/run.log
... and 1 more failures.
0.usbdev_data_toggle_clear.13426591014686863151195237993497212399789547096945910202536835621768918365034
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_data_toggle_clear/latest/run.log
1.usbdev_data_toggle_clear.16485636899292097734168031734140000503578449948385501090892921505816955984498
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/1.usbdev_data_toggle_clear/latest/run.log
... and 41 more failures.
0.usbdev_device_address.4171754107441531940197190386570967652965443410056700983214692217553818276982
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_device_address/latest/run.log
1.usbdev_device_address.52898308849867132754600364978779177814283757183352905518236186468117438700130
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/1.usbdev_device_address/latest/run.log
... and 41 more failures.