Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	58611	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

62642

1

T1

25

T2

56

T3

41

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	74043	1			T1	20		T2	41		T3	248
values[0x0]	23446	1			T1	11		T2	23		T3	32
values[0x1]	23764	1			T1	9		T2	18		T3	19

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	40763	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

80490

1

T1

31

T2

64

T3

116

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	406	1			T7	15		T4	2		T5	5
valid_sources[0x01]	556	1			T3	2		T7	19		T10	8
valid_sources[0x02]	347	1			T7	18		T4	1		T5	4
valid_sources[0x03]	423	1			T3	1		T4	15		T5	4
valid_sources[0x04]	437	1			T2	1		T3	1		T10	1
valid_sources[0x05]	449	1			T9	1		T7	7		T10	4
valid_sources[0x06]	388	1			T3	4		T7	2		T10	2
valid_sources[0x07]	441	1			T3	3		T7	2		T4	3
valid_sources[0x08]	416	1			T2	1		T3	1		T10	2
valid_sources[0x09]	572	1			T2	1		T3	2		T7	6
valid_sources[0x0a]	388	1			T3	1		T9	1		T7	2
valid_sources[0x0b]	414	1			T3	2		T7	14		T10	3
valid_sources[0x0c]	400	1			T3	1		T7	8		T10	5
valid_sources[0x0d]	442	1			T2	3		T3	4		T7	7
valid_sources[0x0e]	457	1			T3	1		T7	20		T4	1
valid_sources[0x0f]	1061	1			T2	1		T3	1		T7	1
valid_sources[0x10]	393	1			T2	1		T3	3		T7	2
valid_sources[0x11]	527	1			T5	2		T14	4		T15	10
valid_sources[0x12]	532	1			T3	2		T7	5		T4	5
valid_sources[0x13]	439	1			T2	1		T7	5		T4	8
valid_sources[0x14]	477	1			T2	1		T7	7		T10	3
valid_sources[0x15]	439	1			T3	3		T7	2		T10	8
valid_sources[0x16]	641	1			T10	1		T5	3		T14	5
valid_sources[0x17]	424	1			T3	4		T10	1		T4	6
valid_sources[0x18]	438	1			T2	1		T3	1		T7	1
valid_sources[0x19]	1157	1			T5	3		T14	4		T17	2
valid_sources[0x1a]	589	1			T2	1		T3	4		T5	1
valid_sources[0x1b]	586	1			T7	2		T4	5		T14	10
valid_sources[0x1c]	412	1			T7	3		T10	6		T5	6
valid_sources[0x1d]	432	1			T2	1		T3	1		T4	1
valid_sources[0x1e]	465	1			T5	2		T14	11		T44	1
valid_sources[0x1f]	413	1			T3	3		T7	4		T10	3
valid_sources[0x20]	577	1			T3	1		T9	2		T7	1
valid_sources[0x21]	461	1			T3	1		T7	6		T10	3
valid_sources[0x22]	510	1			T7	7		T4	7		T5	6
valid_sources[0x23]	457	1			T3	1		T7	19		T4	13
valid_sources[0x24]	502	1			T9	2		T7	13		T4	4
valid_sources[0x25]	399	1			T4	12		T5	4		T14	14
valid_sources[0x26]	409	1			T2	1		T3	2		T7	19
valid_sources[0x27]	412	1			T3	1		T7	5		T10	1
valid_sources[0x28]	443	1			T9	1		T7	3		T4	17
valid_sources[0x29]	355	1			T3	1		T10	1		T5	1
valid_sources[0x2a]	464	1			T2	2		T7	6		T5	4
valid_sources[0x2b]	450	1			T7	1		T4	2		T5	2
valid_sources[0x2c]	480	1			T3	1		T7	12		T5	1
valid_sources[0x2d]	487	1			T2	1		T3	1		T7	4
valid_sources[0x2e]	449	1			T3	3		T7	5		T4	4
valid_sources[0x2f]	516	1			T3	1		T7	4		T10	5
valid_sources[0x30]	465	1			T3	1		T7	2		T10	3
valid_sources[0x31]	403	1			T3	1		T7	4		T4	13
valid_sources[0x32]	398	1			T4	3		T5	1		T14	13
valid_sources[0x33]	465	1			T1	5		T7	2		T10	5
valid_sources[0x34]	432	1			T2	1		T3	2		T7	2
valid_sources[0x35]	444	1			T3	1		T7	6		T4	2
valid_sources[0x36]	432	1			T3	1		T7	1		T10	2
valid_sources[0x37]	755	1			T2	4		T9	2		T7	9
valid_sources[0x38]	400	1			T3	2		T7	7		T10	3
valid_sources[0x39]	454	1			T2	1		T3	3		T7	3
valid_sources[0x3a]	609	1			T5	5		T14	11		T15	6
valid_sources[0x3b]	564	1			T3	1		T4	6		T5	3
valid_sources[0x3c]	467	1			T2	2		T3	1		T7	30
valid_sources[0x3d]	421	1			T3	1		T7	13		T14	17
valid_sources[0x3e]	427	1			T3	2		T7	4		T5	3
valid_sources[0x3f]	389	1			T3	1		T7	6		T10	2
valid_sources[0x40]	689	1			T7	15		T10	2		T5	1
valid_sources[0x41]	513	1			T2	1		T3	1		T7	6
valid_sources[0x42]	580	1			T3	2		T7	5		T5	2
valid_sources[0x43]	453	1			T3	2		T7	2		T4	6
valid_sources[0x44]	520	1			T3	2		T7	26		T5	6
valid_sources[0x45]	495	1			T3	3		T7	3		T10	4
valid_sources[0x46]	418	1			T7	1		T10	3		T5	3
valid_sources[0x47]	670	1			T3	1		T7	1		T10	5
valid_sources[0x48]	411	1			T3	2		T9	1		T7	9
valid_sources[0x49]	422	1			T2	2		T3	1		T7	7
valid_sources[0x4a]	353	1			T7	22		T10	2		T5	1
valid_sources[0x4b]	540	1			T7	6		T10	3		T4	10
valid_sources[0x4c]	457	1			T3	4		T7	1		T8	81
valid_sources[0x4d]	382	1			T9	1		T7	5		T10	10
valid_sources[0x4e]	440	1			T3	2		T7	6		T4	3
valid_sources[0x4f]	681	1			T2	1		T7	9		T5	4
valid_sources[0x50]	532	1			T3	1		T7	14		T10	4
valid_sources[0x51]	444	1			T7	2		T4	10		T5	7
valid_sources[0x52]	506	1			T7	10		T4	1		T14	17
valid_sources[0x53]	433	1			T2	2		T3	1		T7	5
valid_sources[0x54]	385	1			T2	1		T3	3		T7	11
valid_sources[0x55]	436	1			T1	1		T3	2		T7	17
valid_sources[0x56]	355	1			T3	1		T7	6		T10	2
valid_sources[0x57]	370	1			T3	1		T7	7		T4	1
valid_sources[0x58]	568	1			T3	4		T7	2		T4	1
valid_sources[0x59]	440	1			T3	1		T7	6		T4	3
valid_sources[0x5a]	391	1			T3	2		T7	6		T5	6
valid_sources[0x5b]	678	1			T1	3		T7	8		T10	3
valid_sources[0x5c]	454	1			T2	1		T3	1		T5	1
valid_sources[0x5d]	507	1			T2	1		T3	1		T9	1
valid_sources[0x5e]	429	1			T3	1		T7	14		T14	7
valid_sources[0x5f]	500	1			T3	2		T7	18		T4	2
valid_sources[0x60]	329	1			T3	1		T7	1		T8	10
valid_sources[0x61]	455	1			T3	4		T7	9		T10	2
valid_sources[0x62]	364	1			T3	3		T4	4		T5	3
valid_sources[0x63]	426	1			T3	1		T7	4		T4	2
valid_sources[0x64]	746	1			T3	1		T7	3		T4	2
valid_sources[0x65]	390	1			T7	1		T4	1		T5	2
valid_sources[0x66]	446	1			T3	1		T4	2		T5	1
valid_sources[0x67]	432	1			T3	2		T10	5		T4	4
valid_sources[0x68]	482	1			T2	1		T3	1		T5	6
valid_sources[0x69]	406	1			T3	1		T7	2		T10	2
valid_sources[0x6a]	448	1			T7	3		T4	2		T5	2
valid_sources[0x6b]	568	1			T1	2		T10	6		T4	7
valid_sources[0x6c]	392	1			T2	1		T7	1		T10	1
valid_sources[0x6d]	511	1			T7	9		T4	7		T5	4
valid_sources[0x6e]	438	1			T3	4		T10	1		T5	3
valid_sources[0x6f]	420	1			T2	1		T3	2		T7	20
valid_sources[0x70]	432	1			T3	2		T7	7		T10	8
valid_sources[0x71]	392	1			T4	2		T5	6		T14	26
valid_sources[0x72]	423	1			T7	17		T5	2		T14	11
valid_sources[0x73]	411	1			T7	8		T4	11		T5	6
valid_sources[0x74]	498	1			T2	2		T3	1		T7	3
valid_sources[0x75]	483	1			T2	1		T3	1		T7	1
valid_sources[0x76]	571	1			T3	1		T7	5		T4	5
valid_sources[0x77]	412	1			T3	1		T7	7		T10	1
valid_sources[0x78]	428	1			T3	2		T7	6		T4	2
valid_sources[0x79]	464	1			T3	2		T7	11		T4	1
valid_sources[0x7a]	453	1			T2	1		T3	2		T6	7
valid_sources[0x7b]	449	1			T3	2		T7	2		T5	2
valid_sources[0x7c]	431	1			T3	1		T7	7		T10	1
valid_sources[0x7d]	427	1			T7	5		T10	1		T4	6
valid_sources[0x7e]	406	1			T3	2		T7	8		T10	5
valid_sources[0x7f]	391	1			T3	1		T7	6		T4	1
valid_sources[0x80]	547	1			T3	3		T7	2		T10	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25051

1

T1

10

T2

30

T3

13

values[0x0]

all_enables

biggest_size

20094

1

T1

11

T2

16

T3

18

values[0x1]

all_enables

biggest_size

17497

1

T1

4

T2

10

T3

10