Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

73959

1

T1

15

T2

26

T3

258

full_word

63736

1

T1

25

T2

56

T3

41

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	137405	1			T1	40		T2	82		T3	299
auto[TlIntgErrCmd]	99	1			T15	8		T27	2		T48	7
auto[TlIntgErrData]	83	1			T15	5		T27	2		T48	5
auto[TlIntgErrBoth]	108	1			T15	7		T27	6		T48	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

76040

1

T1

20

T2

41

T3

248

auto[1]

61655

1

T1

20

T2

41

T3

51

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	50673	1			T1	10		T2	11		T3	235
auto[TlIntgErrNone]	partial	auto[1]	23022	1			T1	5		T2	15		T3	23
auto[TlIntgErrNone]	full_word	auto[0]	25234	1			T1	10		T2	30		T3	13
auto[TlIntgErrNone]	full_word	auto[1]	38476	1			T1	15		T2	26		T3	28
auto[TlIntgErrCmd]	partial	auto[0]	35	1			T15	2		T27	2		T48	5
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T15	5		T48	2		T54	4
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T15	1		T65	1		T69	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T54	2		T70	1		T71	1
auto[TlIntgErrData]	partial	auto[0]	44	1			T15	1		T48	3		T54	4
auto[TlIntgErrData]	partial	auto[1]	30	1			T15	2		T27	2		T48	2
auto[TlIntgErrData]	full_word	auto[0]	3	1			T15	1		T72	1		T73	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T15	1		T69	1		T73	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T15	3		T27	3		T48	2
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T15	4		T27	3		T48	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T48	2		T68	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T67	1		T70	1		T74	1