Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
22.61	0.00	0.00	90.45		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1821104	12769	0	0
ep_in_enable_rd_A	1821104	3638	0	0
ep_out_enable_rd_A	1821104	3266	0	0
in_iso_rd_A	1821104	3196	0	0
intr_enable_rd_A	1821104	4998	0	0
out_iso_rd_A	1821104	3184	0	0
phy_config_rd_A	1821104	1877	0	0
phy_pins_drive_rd_A	1821104	2477	0	0
rxenable_setup_rd_A	1821104	3208	0	0
set_nak_out_rd_A	1821104	3097	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1821104	12769	0	0
T4	8713	16	0	0
T5	9586	13	0	0
T6	6063	288	0	0
T7	12574	0	0	0
T8	13353	858	0	0
T10	6480	0	0	0
T14	25187	0	0	0
T15	0	4	0	0
T16	0	20	0	0
T17	3326	0	0	0
T18	2108	0	0	0
T19	2091	0	0	0
T24	0	19	0	0
T25	0	10	0	0
T26	0	1018	0	0
T27	0	3	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1821104	3638	0	0
T5	9586	18	0	0
T14	25187	0	0	0
T15	63222	0	0	0
T17	3326	18	0	0
T19	2091	0	0	0
T20	3725	0	0	0
T21	2034	0	0	0
T25	0	6	0	0
T26	0	3	0	0
T30	2377	0	0	0
T31	0	107	0	0
T39	0	44	0	0
T44	2573	0	0	0
T45	5283	0	0	0
T52	0	13	0	0
T53	0	74	0	0
T54	0	366	0	0
T55	0	27	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1821104	3266	0	0
T5	9586	49	0	0
T14	25187	0	0	0
T15	63222	0	0	0
T17	3326	1	0	0
T19	2091	0	0	0
T20	3725	0	0	0
T21	2034	0	0	0
T25	0	54	0	0
T26	0	5	0	0
T28	0	5	0	0
T30	2377	0	0	0
T31	0	94	0	0
T44	2573	0	0	0
T45	5283	0	0	0
T52	0	18	0	0
T53	0	103	0	0
T54	0	285	0	0
T55	0	50	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1821104	3196	0	0
T5	9586	76	0	0
T14	25187	0	0	0
T15	63222	0	0	0
T17	3326	25	0	0
T19	2091	0	0	0
T20	3725	0	0	0
T21	2034	0	0	0
T25	0	90	0	0
T30	2377	0	0	0
T31	0	125	0	0
T39	0	41	0	0
T40	0	196	0	0
T44	2573	0	0	0
T45	5283	0	0	0
T51	0	110	0	0
T52	0	21	0	0
T53	0	15	0	0
T54	0	174	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1821104	4998	0	0
T5	9586	76	0	0
T14	25187	0	0	0
T15	63222	0	0	0
T17	3326	18	0	0
T19	2091	0	0	0
T20	3725	13	0	0
T21	2034	0	0	0
T25	0	13	0	0
T30	2377	0	0	0
T31	0	156	0	0
T44	2573	0	0	0
T45	5283	0	0	0
T56	0	1	0	0
T57	0	20	0	0
T58	0	19	0	0
T59	0	4	0	0
T60	0	1	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1821104	3184	0	0
T5	9586	90	0	0
T14	25187	0	0	0
T15	63222	0	0	0
T17	3326	1	0	0
T19	2091	0	0	0
T20	3725	0	0	0
T21	2034	0	0	0
T25	0	64	0	0
T30	2377	0	0	0
T31	0	140	0	0
T39	0	85	0	0
T40	0	246	0	0
T44	2573	0	0	0
T45	5283	0	0	0
T52	0	40	0	0
T53	0	17	0	0
T54	0	225	0	0
T55	0	47	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1821104	1877	0	0
T5	9586	20	0	0
T14	25187	0	0	0
T15	63222	0	0	0
T17	3326	8	0	0
T19	2091	0	0	0
T20	3725	0	0	0
T21	2034	0	0	0
T25	0	3	0	0
T30	2377	0	0	0
T31	0	126	0	0
T39	0	37	0	0
T40	0	195	0	0
T44	2573	0	0	0
T45	5283	0	0	0
T52	0	20	0	0
T53	0	35	0	0
T54	0	129	0	0
T55	0	16	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1821104	2477	0	0
T5	9586	20	0	0
T14	25187	0	0	0
T15	63222	0	0	0
T17	3326	39	0	0
T19	2091	0	0	0
T20	3725	0	0	0
T21	2034	0	0	0
T25	0	12	0	0
T30	2377	0	0	0
T31	0	74	0	0
T39	0	7	0	0
T40	0	225	0	0
T44	2573	0	0	0
T45	5283	0	0	0
T52	0	16	0	0
T53	0	79	0	0
T54	0	170	0	0
T55	0	28	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1821104	3208	0	0
T5	9586	60	0	0
T14	25187	0	0	0
T15	63222	0	0	0
T17	3326	13	0	0
T19	2091	0	0	0
T20	3725	0	0	0
T21	2034	0	0	0
T25	0	67	0	0
T26	0	9	0	0
T30	2377	0	0	0
T31	0	124	0	0
T39	0	92	0	0
T44	2573	0	0	0
T45	5283	0	0	0
T52	0	41	0	0
T53	0	57	0	0
T54	0	303	0	0
T55	0	22	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1821104	3097	0	0
T5	9586	13	0	0
T14	25187	0	0	0
T15	63222	0	0	0
T17	3326	19	0	0
T19	2091	0	0	0
T20	3725	0	0	0
T21	2034	0	0	0
T25	0	50	0	0
T30	2377	0	0	0
T31	0	144	0	0
T39	0	52	0	0
T40	0	249	0	0
T44	2573	0	0	0
T45	5283	0	0	0
T52	0	60	0	0
T53	0	68	0	0
T54	0	300	0	0
T55	0	8	0	0