Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_fifo_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
29.17 16.67 0.00 0.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.usbdev_avsetupfifo 0.00 0.00 0.00 0.00
tb.dut.usbdev_avoutfifo 0.00 0.00 0.00 0.00
tb.dut.usbdev_rxfifo 0.00 0.00 0.00 0.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo 0.00 0.00 0.00 0.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo 0.00 0.00 0.00 0.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo 0.00 0.00 0.00 0.00
tb.dut.u_reg.u_socket.fifo_h.reqfifo 100.00 100.00 100.00
tb.dut.u_reg.u_socket.fifo_h.rspfifo 100.00 100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo 100.00 100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo 100.00 100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo 100.00 100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo 100.00 100.00 100.00

Line Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Line Coverage for Module self-instances :
SCORELINE
0.00 0.00
tb.dut.usbdev_avsetupfifo

SCORELINE
0.00 0.00
tb.dut.usbdev_avoutfifo

Line No.TotalCoveredPercent
TOTAL1400.00
ALWAYS69400.00
CONT_ASSIGN81100.00
CONT_ASSIGN82100.00
CONT_ASSIGN100100.00
CONT_ASSIGN101100.00
CONT_ASSIGN120100.00
ALWAYS123200.00
CONT_ASSIGN133100.00
CONT_ASSIGN134100.00
CONT_ASSIGN140100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 0 1
70 0 1
71 0 1
72 0 1
==> MISSING_ELSE
81 0 1
82 0 1
100 0 1
101 0 1
120 0 1
123 0 1
124 0 1
==> MISSING_ELSE
133 0 1
134 0 1
140 0 1

Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Line Coverage for Module self-instances :
SCORELINE
0.00 0.00
tb.dut.usbdev_rxfifo

Line No.TotalCoveredPercent
TOTAL1400.00
ALWAYS69400.00
CONT_ASSIGN81100.00
CONT_ASSIGN82100.00
CONT_ASSIGN100100.00
CONT_ASSIGN101100.00
CONT_ASSIGN120100.00
ALWAYS123200.00
CONT_ASSIGN133100.00
CONT_ASSIGN134100.00
CONT_ASSIGN138100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 0 1
70 0 1
71 0 1
72 0 1
==> MISSING_ELSE
81 0 1
82 0 1
100 0 1
101 0 1
120 0 1
123 0 1
124 0 1
==> MISSING_ELSE
133 0 1
134 0 1
138 0 1

Line Coverage for Module : prim_fifo_sync ( parameter Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.fifo_h.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.fifo_h.rspfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable

Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
0.00 0.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

Line No.TotalCoveredPercent
TOTAL1500.00
ALWAYS69400.00
CONT_ASSIGN81100.00
CONT_ASSIGN82100.00
CONT_ASSIGN100100.00
CONT_ASSIGN101100.00
CONT_ASSIGN108100.00
ALWAYS111200.00
CONT_ASSIGN116100.00
CONT_ASSIGN133100.00
CONT_ASSIGN134100.00
CONT_ASSIGN138100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 0 1
70 0 1
71 0 1
72 0 1
==> MISSING_ELSE
81 0 1
82 0 1
100 0 1
101 0 1
108 0 1
111 0 1
112 0 1
==> MISSING_ELSE
116 0 1
133 0 1
134 0 1
138 0 1

Line Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
0.00 0.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

Line No.TotalCoveredPercent
TOTAL1500.00
ALWAYS69400.00
CONT_ASSIGN81100.00
CONT_ASSIGN82100.00
CONT_ASSIGN100100.00
CONT_ASSIGN101100.00
CONT_ASSIGN108100.00
ALWAYS111200.00
CONT_ASSIGN116100.00
CONT_ASSIGN133100.00
CONT_ASSIGN134100.00
CONT_ASSIGN138100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 0 1
70 0 1
71 0 1
72 0 1
==> MISSING_ELSE
81 0 1
82 0 1
100 0 1
101 0 1
108 0 1
111 0 1
112 0 1
==> MISSING_ELSE
116 0 1
133 0 1
134 0 1
138 0 1

Line Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
0.00 0.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

Line No.TotalCoveredPercent
TOTAL1500.00
ALWAYS69400.00
CONT_ASSIGN81100.00
CONT_ASSIGN82100.00
CONT_ASSIGN100100.00
CONT_ASSIGN101100.00
CONT_ASSIGN108100.00
ALWAYS111200.00
CONT_ASSIGN116100.00
CONT_ASSIGN130100.00
CONT_ASSIGN131100.00
CONT_ASSIGN138100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 0 1
70 0 1
71 0 1
72 0 1
==> MISSING_ELSE
81 0 1
82 0 1
100 0 1
101 0 1
108 0 1
111 0 1
112 0 1
==> MISSING_ELSE
116 0 1
130 0 1
131 0 1
138 0 1

Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
0.00 0.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

TotalCoveredPercent
Conditions1600.00
Logical1600.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered 

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered 

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1Not Covered
Cond Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
0.00 0.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

TotalCoveredPercent
Conditions2400.00
Logical2400.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered 

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered 

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1Not Covered
Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Cond Coverage for Module self-instances :
SCORECOND
0.00 0.00
tb.dut.usbdev_avsetupfifo

SCORECOND
0.00 0.00
tb.dut.usbdev_avoutfifo

TotalCoveredPercent
Conditions1400.00
Logical1400.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered 

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered
Cond Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 + Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
0.00 0.00
tb.dut.usbdev_rxfifo

SCORECOND
0.00 0.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

TotalCoveredPercent
Conditions1600.00
Logical1600.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered 

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered 

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1Not Covered
Branch Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Branch Coverage for Module self-instances :
SCOREBRANCH
0.00 0.00
tb.dut.usbdev_avsetupfifo

SCOREBRANCH
0.00 0.00
tb.dut.usbdev_avoutfifo

Line No.TotalCoveredPercent
Branches 5 0 0.00
IF 69 3 0 0.00
IF 123 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered 



	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

Branch Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
SCOREBRANCH
0.00 0.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

Line No.TotalCoveredPercent
Branches 9 0 0.00
TERNARY 130 2 0 0.00
TERNARY 138 2 0 0.00
IF 69 3 0 0.00
IF 111 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered 



	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

Branch Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 + Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
SCOREBRANCH
0.00 0.00
tb.dut.usbdev_rxfifo

SCOREBRANCH
0.00 0.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

SCOREBRANCH
0.00 0.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

Line No.TotalCoveredPercent
Branches 7 0 0.00
TERNARY 138 2 0 0.00
IF 69 3 0 0.00
IF 123 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered 



	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

Assert Coverage for Module : prim_fifo_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 10926624 1330477 0 0
DepthKnown_A 10926624 10686576 0 0
RvalidKnown_A 10926624 10686576 0 0
WreadyKnown_A 10926624 10686576 0 0
gen_passthru_fifo.paramCheckPass 1050 1050 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10926624 1330477 0 0
T1 6748 160 0 0
T2 18532 482 0 0
T3 14144 2822 0 0
T4 52278 3740 0 0
T5 19172 2863 0 0
T6 36378 2400 0 0
T7 75444 6152 0 0
T8 80118 8035 0 0
T9 13788 88 0 0
T10 38880 4852 0 0
T14 50374 0 0 0
T16 0 1962 0 0
T17 6652 0 0 0
T18 12648 88 0 0
T19 4182 0 0 0
T22 0 3070 0 0
T23 0 1058 0 0
T24 0 2257 0 0
T25 0 890 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10926624 10686576 0 0
T1 10122 9648 0 0
T2 27798 26862 0 0
T3 21216 20634 0 0
T4 52278 49530 0 0
T6 36378 35940 0 0
T7 75444 74880 0 0
T8 80118 79806 0 0
T9 20682 20274 0 0
T10 38880 38454 0 0
T18 12648 12120 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10926624 10686576 0 0
T1 10122 9648 0 0
T2 27798 26862 0 0
T3 21216 20634 0 0
T4 52278 49530 0 0
T6 36378 35940 0 0
T7 75444 74880 0 0
T8 80118 79806 0 0
T9 20682 20274 0 0
T10 38880 38454 0 0
T18 12648 12120 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10926624 10686576 0 0
T1 10122 9648 0 0
T2 27798 26862 0 0
T3 21216 20634 0 0
T4 52278 49530 0 0
T6 36378 35940 0 0
T7 75444 74880 0 0
T8 80118 79806 0 0
T9 20682 20274 0 0
T10 38880 38454 0 0
T18 12648 12120 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1050 1050 0 0
T1 6 6 0 0
T2 6 6 0 0
T3 6 6 0 0
T4 6 6 0 0
T6 6 6 0 0
T7 6 6 0 0
T8 6 6 0 0
T9 6 6 0 0
T10 6 6 0 0
T18 6 6 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%