Unified Coverage Report :: Module :: usbdev_counter

Module : usbdev_counter

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_ctr_out	0.00	0.00	0.00			0.00
tb.dut.u_ctr_in	0.00	0.00	0.00			0.00
tb.dut.u_ctr_nodata_in	0.00	0.00	0.00			0.00
tb.dut.u_ctr_errors	0.00	0.00	0.00			0.00

---

Module Instance : tb.dut.u_ctr_out

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
22.61	0.00	0.00	90.45		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctr_in

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
22.61	0.00	0.00	90.45		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctr_nodata_in

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
22.61	0.00	0.00	90.45		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctr_errors

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
22.61	0.00	0.00	90.45		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : usbdev_counter ( parameter NEndpoints=12,NEvents=4,Width=8,EpW=4 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.u_ctr_out

	Line No.	Total	Covered	Percent
TOTAL		19	0	0.00
ALWAYS	45	7	0	0.00
CONT_ASSIGN	58	1	0	0.00
ALWAYS	70	8	0	0.00
CONT_ASSIGN	84	1	0	0.00
CONT_ASSIGN	85	1	0	0.00
CONT_ASSIGN	86	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	0	1
46	0	1
47	0	1
50	0	2
			==> MISSING_ELSE
51	0	2
			==> MISSING_ELSE
58	0	1
70	0	1
71	0	1
72	0	1
73	0	1
74	0	1
78	0	2
			==> MISSING_ELSE
80	0	1
84	0	1
85	0	1
86	0	1

---

Line Coverage for Module : usbdev_counter ( parameter NEndpoints=1,NEvents=4,Width=8,EpW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.u_ctr_errors

	Line No.	Total	Covered	Percent
TOTAL		19	0	0.00
ALWAYS	45	7	0	0.00
CONT_ASSIGN	61	0	0
CONT_ASSIGN	62	1	0	0.00
ALWAYS	70	8	0	0.00
CONT_ASSIGN	84	1	0	0.00
CONT_ASSIGN	85	1	0	0.00
CONT_ASSIGN	86	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	0	1
46	0	1
47	0	1
50	0	2
			==> MISSING_ELSE
51	0	2
			==> MISSING_ELSE
61		unreachable
62	0	1
70	0	1
71	0	1
72	0	1
73	0	1
74	0	1
78	0	2
			==> MISSING_ELSE
80	0	1
84	0	1
85	0	1
86	0	1

---

Line Coverage for Module : usbdev_counter ( parameter NEndpoints=12,NEvents=3,Width=8,EpW=4 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.u_ctr_in

	Line No.	Total	Covered	Percent
TOTAL		19	0	0.00
ALWAYS	45	7	0	0.00
CONT_ASSIGN	58	1	0	0.00
ALWAYS	70	8	0	0.00
CONT_ASSIGN	84	1	0	0.00
CONT_ASSIGN	85	1	0	0.00
CONT_ASSIGN	86	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	0	1
46	0	1
47	0	1
50	0	2
			==> MISSING_ELSE
51	0	2
			==> MISSING_ELSE
58	0	1
70	0	1
71	0	1
72	0	1
73	0	1
74	0	1
78	0	2
			==> MISSING_ELSE
80	0	1
84	0	1
85	0	1
86	0	1

---

Line Coverage for Module : usbdev_counter ( parameter NEndpoints=12,NEvents=1,Width=8,EpW=4 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.u_ctr_nodata_in

	Line No.	Total	Covered	Percent
TOTAL		19	0	0.00
ALWAYS	45	7	0	0.00
CONT_ASSIGN	58	1	0	0.00
ALWAYS	70	8	0	0.00
CONT_ASSIGN	84	1	0	0.00
CONT_ASSIGN	85	1	0	0.00
CONT_ASSIGN	86	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	0	1
46	0	1
47	0	1
50	0	2
			==> MISSING_ELSE
51	0	2
			==> MISSING_ELSE
58	0	1
70	0	1
71	0	1
72	0	1
73	0	1
74	0	1
78	0	2
			==> MISSING_ELSE
80	0	1
84	0	1
85	0	1
86	0	1

---

Cond Coverage for Module : usbdev_counter ( parameter NEndpoints=12,NEvents=4,Width=8,EpW=4 + NEndpoints=12,NEvents=3,Width=8,EpW=4 + NEndpoints=12,NEvents=1,Width=8,EpW=4 )
Cond Coverage for Module self-instances :

SCORE	COND
0.00	0.00

tb.dut.u_ctr_out

SCORE	COND
0.00	0.00

tb.dut.u_ctr_in

SCORE	COND
0.00	0.00

tb.dut.u_ctr_nodata_in

	Total	Covered	Percent
Conditions	5	0	0.00
Logical	5	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION ((ep_i < 4'(NEndpoints)) ? endpoints[ep_i] : 1'b0)
             -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       78
 EXPRESSION (((|((ev_enables & event_i) & (~event_q)))) & ep_enabled)
             ---------------------1--------------------   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Cond Coverage for Module : usbdev_counter ( parameter NEndpoints=1,NEvents=4,Width=8,EpW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
0.00	0.00

tb.dut.u_ctr_errors

	Total	Covered	Percent
Conditions	3	0	0.00
Logical	3	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       78
 EXPRESSION (((|((ev_enables & event_i) & (~event_q)))) & ep_enabled)
             ---------------------1--------------------   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Module : usbdev_counter ( parameter NEndpoints=12,NEvents=4,Width=8,EpW=4 + NEndpoints=12,NEvents=3,Width=8,EpW=4 + NEndpoints=12,NEvents=1,Width=8,EpW=4 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
0.00	0.00

tb.dut.u_ctr_out

SCORE	BRANCH
0.00	0.00

tb.dut.u_ctr_in

SCORE	BRANCH
0.00	0.00

tb.dut.u_ctr_nodata_in

	Line No.	Total	Covered	Percent
Branches		11	0	0.00
TERNARY	58	2	0	0.00
IF	45	5	0	0.00
IF	70	4	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	58	((ep_i < 4'(NEndpoints))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	45	if ((!rst_ni))
-2-:	50	if (endp_qe_i)
-3-:	51	if (ev_qe_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	-	Not Covered
0	-	1	Not Covered
0	-	0	Not Covered

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	73	if (reset_i)
-3-:	78	if (((|((ev_enables & event_i) & (~event_q))) & ep_enabled))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

---

Branch Coverage for Module : usbdev_counter ( parameter NEndpoints=1,NEvents=4,Width=8,EpW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
0.00	0.00

tb.dut.u_ctr_errors

	Line No.	Total	Covered	Percent
Branches		9	0	0.00
IF	45	5	0	0.00
IF	70	4	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	45	if ((!rst_ni))
-2-:	50	if (endp_qe_i)
-3-:	51	if (ev_qe_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	-	Not Covered
0	-	1	Not Covered
0	-	0	Not Covered

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	73	if (reset_i)
-3-:	78	if (((|((ev_enables & event_i) & (~event_q))) & ep_enabled))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

Line Coverage for Instance : tb.dut.u_ctr_out

	Line No.	Total	Covered	Percent
TOTAL		19	0	0.00
ALWAYS	45	7	0	0.00
CONT_ASSIGN	58	1	0	0.00
ALWAYS	70	8	0	0.00
CONT_ASSIGN	84	1	0	0.00
CONT_ASSIGN	85	1	0	0.00
CONT_ASSIGN	86	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	0	1
46	0	1
47	0	1
50	0	2
			==> MISSING_ELSE
51	0	2
			==> MISSING_ELSE
58	0	1
70	0	1
71	0	1
72	0	1
73	0	1
74	0	1
78	0	2
			==> MISSING_ELSE
80	0	1
84	0	1
85	0	1
86	0	1

---

Cond Coverage for Instance : tb.dut.u_ctr_out

	Total	Covered	Percent
Conditions	4	0	0.00
Logical	4	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION ((ep_i < 4'(NEndpoints)) ? endpoints[ep_i] : 1'b0)
             -----------1-----------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Not Covered

 LINE       78
 EXPRESSION (((|((ev_enables & event_i) & (~event_q)))) & ep_enabled)
             ---------------------1--------------------   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_ctr_out

	Line No.	Total	Covered	Percent
Branches		10	0	0.00
TERNARY	58	1	0	0.00
IF	45	5	0	0.00
IF	70	4	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	58	((ep_i < 4'(NEndpoints))) ? 

Branches:

-1-	Status	Tests	Exclude Annotation
1	Not Covered
0	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	45	if ((!rst_ni))
-2-:	50	if (endp_qe_i)
-3-:	51	if (ev_qe_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	-	Not Covered
0	-	1	Not Covered
0	-	0	Not Covered

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	73	if (reset_i)
-3-:	78	if (((|((ev_enables & event_i) & (~event_q))) & ep_enabled))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

Line Coverage for Instance : tb.dut.u_ctr_in

	Line No.	Total	Covered	Percent
TOTAL		19	0	0.00
ALWAYS	45	7	0	0.00
CONT_ASSIGN	58	1	0	0.00
ALWAYS	70	8	0	0.00
CONT_ASSIGN	84	1	0	0.00
CONT_ASSIGN	85	1	0	0.00
CONT_ASSIGN	86	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	0	1
46	0	1
47	0	1
50	0	2
			==> MISSING_ELSE
51	0	2
			==> MISSING_ELSE
58	0	1
70	0	1
71	0	1
72	0	1
73	0	1
74	0	1
78	0	2
			==> MISSING_ELSE
80	0	1
84	0	1
85	0	1
86	0	1

---

Cond Coverage for Instance : tb.dut.u_ctr_in

	Total	Covered	Percent
Conditions	4	0	0.00
Logical	4	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION ((ep_i < 4'(NEndpoints)) ? endpoints[ep_i] : 1'b0)
             -----------1-----------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Not Covered

 LINE       78
 EXPRESSION (((|((ev_enables & event_i) & (~event_q)))) & ep_enabled)
             ---------------------1--------------------   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_ctr_in

	Line No.	Total	Covered	Percent
Branches		10	0	0.00
TERNARY	58	1	0	0.00
IF	45	5	0	0.00
IF	70	4	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	58	((ep_i < 4'(NEndpoints))) ? 

Branches:

-1-	Status	Tests	Exclude Annotation
1	Not Covered
0	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	45	if ((!rst_ni))
-2-:	50	if (endp_qe_i)
-3-:	51	if (ev_qe_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	-	Not Covered
0	-	1	Not Covered
0	-	0	Not Covered

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	73	if (reset_i)
-3-:	78	if (((|((ev_enables & event_i) & (~event_q))) & ep_enabled))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

Line Coverage for Instance : tb.dut.u_ctr_nodata_in

	Line No.	Total	Covered	Percent
TOTAL		19	0	0.00
ALWAYS	45	7	0	0.00
CONT_ASSIGN	58	1	0	0.00
ALWAYS	70	8	0	0.00
CONT_ASSIGN	84	1	0	0.00
CONT_ASSIGN	85	1	0	0.00
CONT_ASSIGN	86	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	0	1
46	0	1
47	0	1
50	0	2
			==> MISSING_ELSE
51	0	2
			==> MISSING_ELSE
58	0	1
70	0	1
71	0	1
72	0	1
73	0	1
74	0	1
78	0	2
			==> MISSING_ELSE
80	0	1
84	0	1
85	0	1
86	0	1

---

Cond Coverage for Instance : tb.dut.u_ctr_nodata_in

	Total	Covered	Percent
Conditions	4	0	0.00
Logical	4	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION ((ep_i < 4'(NEndpoints)) ? endpoints[ep_i] : 1'b0)
             -----------1-----------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Not Covered

 LINE       78
 EXPRESSION (((|((ev_enables & event_i) & (~event_q)))) & ep_enabled)
             ---------------------1--------------------   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_ctr_nodata_in

	Line No.	Total	Covered	Percent
Branches		9	0	0.00
TERNARY	58	1	0	0.00
IF	45	4	0	0.00
IF	70	4	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	58	((ep_i < 4'(NEndpoints))) ? 

Branches:

-1-	Status	Tests	Exclude Annotation
1	Not Covered
0	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	45	if ((!rst_ni))
-2-:	50	if (endp_qe_i)
-3-:	51	if (ev_qe_i)

Branches:

-1-	-2-	-3-	Status	Tests	Exclude Annotation
1	-	-	Not Covered
0	1	-	Not Covered
0	0	-	Not Covered
0	-	1	Not Covered
0	-	0	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	73	if (reset_i)
-3-:	78	if (((|((ev_enables & event_i) & (~event_q))) & ep_enabled))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

Line Coverage for Instance : tb.dut.u_ctr_errors

	Line No.	Total	Covered	Percent
TOTAL		19	0	0.00
ALWAYS	45	7	0	0.00
CONT_ASSIGN	61	0	0
CONT_ASSIGN	62	1	0	0.00
ALWAYS	70	8	0	0.00
CONT_ASSIGN	84	1	0	0.00
CONT_ASSIGN	85	1	0	0.00
CONT_ASSIGN	86	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	0	1
46	0	1
47	0	1
50	0	2
			==> MISSING_ELSE
51	0	2
			==> MISSING_ELSE
61		unreachable
62	0	1
70	0	1
71	0	1
72	0	1
73	0	1
74	0	1
78	0	2
			==> MISSING_ELSE
80	0	1
84	0	1
85	0	1
86	0	1

---

Cond Coverage for Instance : tb.dut.u_ctr_errors

	Total	Covered	Percent
Conditions	2	0	0.00
Logical	2	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       78
 EXPRESSION (((|((ev_enables & event_i) & (~event_q)))) & ep_enabled)
             ---------------------1--------------------   -----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Not Covered
1	0	Excluded		VC_COV_UNR
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_ctr_errors

	Line No.	Total	Covered	Percent
Branches		8	0	0.00
IF	45	4	0	0.00
IF	70	4	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	45	if ((!rst_ni))
-2-:	50	if (endp_qe_i)
-3-:	51	if (ev_qe_i)

Branches:

-1-	-2-	-3-	Status	Tests	Exclude Annotation
1	-	-	Not Covered
0	1	-	Not Covered
0	0	-	Excluded		VC_COV_UNR
0	-	1	Not Covered
0	-	0	Not Covered

	LineNo.	Expression
-1-:	70	if ((!rst_ni))
-2-:	73	if (reset_i)
-3-:	78	if (((|((ev_enables & event_i) & (~event_q))) & ep_enabled))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered