Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.99	97.53	92.86	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	588426952	11630	0	0
ep_in_enable_rd_A	588426952	3419	0	0
ep_out_enable_rd_A	588426952	3631	0	0
in_iso_rd_A	588426952	3500	0	0
intr_enable_rd_A	588426952	4233	0	0
out_iso_rd_A	588426952	3401	0	0
phy_config_rd_A	588426952	2252	0	0
phy_pins_drive_rd_A	588426952	2914	0	0
rxenable_setup_rd_A	588426952	3017	0	0
set_nak_out_rd_A	588426952	3499	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588426952	11630	0	0
T214	7138	315	0	0
T215	4563	6	0	0
T216	8891	387	0	0
T235	15844	2	0	0
T245	59048	4	0	0
T246	35521	2	0	0
T248	5410	260	0	0
T251	4518	11	0	0
T258	5540	6	0	0
T259	5802	12	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588426952	3419	0	0
T236	3864	4	0	0
T237	10227	72	0	0
T258	5540	5	0	0
T260	21403	353	0	0
T270	17555	210	0	0
T272	4406	43	0	0
T276	46151	218	0	0
T279	14261	49	0	0
T288	4995	4	0	0
T289	3830	78	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588426952	3631	0	0
T236	3864	10	0	0
T237	10227	28	0	0
T258	5540	6	0	0
T260	21403	218	0	0
T270	17555	185	0	0
T272	4406	95	0	0
T276	46151	211	0	0
T279	14261	50	0	0
T288	4995	8	0	0
T290	4476	2	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588426952	3500	0	0
T236	3864	3	0	0
T237	10227	28	0	0
T258	5540	28	0	0
T260	21403	252	0	0
T270	17555	212	0	0
T272	4406	54	0	0
T276	46151	193	0	0
T279	14261	31	0	0
T288	4995	3	0	0
T290	4476	5	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588426952	4233	0	0
T221	2109	20	0	0
T236	3864	4	0	0
T237	10227	51	0	0
T260	21403	331	0	0
T270	17555	197	0	0
T272	4406	8	0	0
T276	46151	237	0	0
T279	14261	61	0	0
T288	4995	11	0	0
T290	4476	1	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588426952	3401	0	0
T236	3864	30	0	0
T237	10227	27	0	0
T258	5540	17	0	0
T260	21403	381	0	0
T270	17555	195	0	0
T272	4406	10	0	0
T276	46151	161	0	0
T279	14261	56	0	0
T288	4995	9	0	0
T290	4476	6	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588426952	2252	0	0
T237	10227	32	0	0
T258	5540	4	0	0
T260	21403	151	0	0
T270	17555	188	0	0
T272	4406	59	0	0
T276	46151	177	0	0
T279	14261	13	0	0
T288	4995	9	0	0
T289	3830	9	0	0
T290	4476	7	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588426952	2914	0	0
T236	3864	7	0	0
T237	10227	86	0	0
T258	5540	16	0	0
T260	21403	208	0	0
T270	17555	185	0	0
T272	4406	36	0	0
T276	46151	214	0	0
T279	14261	39	0	0
T288	4995	10	0	0
T290	4476	6	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588426952	3017	0	0
T237	10227	18	0	0
T252	14815	7	0	0
T260	21403	211	0	0
T270	17555	200	0	0
T272	4406	51	0	0
T276	46151	221	0	0
T279	14261	42	0	0
T288	4995	3	0	0
T289	3830	54	0	0
T290	4476	5	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588426952	3499	0	0
T236	3864	24	0	0
T237	10227	59	0	0
T258	5540	5	0	0
T260	21403	390	0	0
T270	17555	169	0	0
T272	4406	74	0	0
T276	46151	215	0	0
T279	14261	1	0	0
T288	4995	9	0	0
T289	3830	60	0	0