Line Coverage for Module :
usbdev
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 162 | 158 | 97.53 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 220 | 1 | 1 | 100.00 |
| ALWAYS | 222 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 257 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 258 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 259 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 263 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 264 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 266 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 268 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 316 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 321 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 324 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 327 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 352 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 353 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 354 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 355 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 356 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 360 | 1 | 0 | 0.00 |
| ALWAYS | 383 | 0 | 0 | |
| ALWAYS | 383 | 3 | 3 | 100.00 |
| ALWAYS | 391 | 0 | 0 | |
| ALWAYS | 391 | 4 | 4 | 100.00 |
| ALWAYS | 400 | 0 | 0 | |
| ALWAYS | 400 | 3 | 3 | 100.00 |
| ALWAYS | 407 | 0 | 0 | |
| ALWAYS | 407 | 3 | 3 | 100.00 |
| ALWAYS | 414 | 0 | 0 | |
| ALWAYS | 414 | 3 | 3 | 100.00 |
| ALWAYS | 421 | 0 | 0 | |
| ALWAYS | 421 | 2 | 2 | 100.00 |
| ALWAYS | 434 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 442 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 443 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 447 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 448 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 449 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 451 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 456 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 457 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 458 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 460 | 1 | 1 | 100.00 |
| ALWAYS | 464 | 3 | 3 | 100.00 |
| ALWAYS | 471 | 0 | 0 | |
| ALWAYS | 471 | 3 | 3 | 100.00 |
| ALWAYS | 480 | 3 | 3 | 100.00 |
| ALWAYS | 492 | 3 | 3 | 100.00 |
| ALWAYS | 499 | 0 | 0 | |
| ALWAYS | 499 | 3 | 3 | 100.00 |
| ALWAYS | 506 | 10 | 10 | 100.00 |
| ALWAYS | 525 | 3 | 3 | 100.00 |
| ALWAYS | 532 | 0 | 0 | |
| ALWAYS | 532 | 3 | 3 | 100.00 |
| ALWAYS | 540 | 0 | 0 | |
| ALWAYS | 540 | 3 | 3 | 100.00 |
| ALWAYS | 549 | 0 | 0 | |
| ALWAYS | 549 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 559 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 560 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 561 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 684 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 685 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 687 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 688 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 706 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 709 | 1 | 1 | 100.00 |
| ALWAYS | 715 | 0 | 0 | |
| ALWAYS | 715 | 8 | 8 | 100.00 |
| CONT_ASSIGN | 800 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 801 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 802 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 803 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 811 | 1 | 1 | 100.00 |
| ALWAYS | 820 | 8 | 8 | 100.00 |
| CONT_ASSIGN | 834 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 835 | 0 | 0 | |
| CONT_ASSIGN | 838 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 839 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 897 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 898 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 902 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1165 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1166 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1168 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1208 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1211 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1220 | 1 | 1 | 100.00 |
| ALWAYS | 1223 | 5 | 5 | 100.00 |
| ALWAYS | 1232 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 1245 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1248 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1255 | 1 | 1 | 100.00 |
| ALWAYS | 1259 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 1266 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1271 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1273 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1281 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1283 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1285 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1287 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1297 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 1301 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 1304 | 1 | 0 | 0.00 |
122 end else begin : gen_no_stubbed_reset
123 1/1 assign rst_n = rst_ni;
Tests: T1 T2 T3
124 end
125
126 tlul_pkg::tl_h2d_t tl_sram_h2d;
127 tlul_pkg::tl_d2h_t tl_sram_d2h;
128
129 // Software access to the Packet Buffer RAM
130 logic sw_mem_a_req;
131 logic sw_mem_a_gnt;
132 logic sw_mem_a_write;
133 logic [SramAw-1:0] sw_mem_a_addr;
134 logic [SramDw-1:0] sw_mem_a_wdata;
135 logic sw_mem_a_rvalid;
136 logic [SramDw-1:0] sw_mem_a_rdata;
137 logic [1:0] sw_mem_a_rerror;
138
139 // usbdev hardware access to the Packet Buffer RAM
140 logic usb_mem_b_req;
141 logic usb_mem_b_write;
142 logic [SramAw-1:0] usb_mem_b_addr;
143 logic [SramDw-1:0] usb_mem_b_wdata;
144 logic [SramDw-1:0] usb_mem_b_rdata;
145
146 logic clr_devaddr;
147 logic event_av_setup_empty, event_av_out_empty, event_av_overflow, event_rx_full;
148 logic link_reset, link_suspend;
149 logic host_lost, link_disconnect, link_powered;
150 logic event_link_reset, event_link_suspend, event_link_resume;
151 logic event_host_lost, event_disconnect, event_powered;
152 logic event_rx_crc5_err, event_rx_crc16_err;
153 logic event_rx_crc_err, event_rx_pid_err;
154 logic event_rx_bitstuff_err;
155 logic event_in_err;
156 logic event_out_err;
157 logic event_frame, event_sof;
158 logic link_active;
159
160 // Diagnostic visibility of OUT-side exceptional events
161 logic event_ign_avsetup, event_drop_avout, event_drop_rx, event_datatog_out;
162 // Diagnostic visibility of IN-side exceptional events
163 logic event_timeout_in, event_nak_in, event_nodata_in;
164
165 // Interrupt to software reports both types of CRC error; they are separated only for the
166 // purpose of diagnostic event counting.
167 1/1 assign event_rx_crc_err = event_rx_crc5_err | event_rx_crc16_err;
Tests: T1 T2 T3
168
169 logic [10:0] frame;
170 logic [2:0] link_state;
171 logic connect_en;
172 logic resume_link_active;
173
174 // Current state of OUT data toggles
175 logic [NEndpoints-1:0] out_data_toggle;
176 // Write strobe from register interface
177 logic out_datatog_we;
178 // Write data from register interface
179 logic [NEndpoints-1:0] out_datatog_status;
180 logic [NEndpoints-1:0] out_datatog_mask;
181
182 // Current state of IN data toggles
183 logic [NEndpoints-1:0] in_data_toggle;
184 // Write strobe from register interface
185 logic in_datatog_we;
186 // Write data from register interface
187 logic [NEndpoints-1:0] in_datatog_status;
188 logic [NEndpoints-1:0] in_datatog_mask;
189
190 /////////////////////////////////
191 // USB RX after CDC & muxing //
192 /////////////////////////////////
193 logic usb_rx_d;
194 logic usb_rx_dp;
195 logic usb_rx_dn;
196 /////////////////////////////////
197 // USB TX after CDC & muxing //
198 /////////////////////////////////
199 logic usb_tx_d;
200 logic usb_tx_se0;
201 logic usb_tx_dp;
202 logic usb_tx_dn;
203 logic usb_tx_oe;
204 /////////////////////////////////
205 // USB contol pins after CDC //
206 /////////////////////////////////
207 logic usb_pwr_sense;
208 logic usb_pullup_en;
209 logic usb_dp_pullup_en;
210 logic usb_dn_pullup_en;
211
212 //////////////////////////////////
213 // Microsecond timing reference //
214 //////////////////////////////////
215 // us_tick ticks for one cycle every us, and it is based off a free-running
216 // counter.
217 logic [5:0] ns_cnt;
218 logic us_tick;
219
220 1/1 assign us_tick = (ns_cnt == 6'd47);
Tests: T1 T2 T3
221 always_ff @(posedge clk_i or negedge rst_n) begin
222 1/1 if (!rst_n) begin
Tests: T1 T2 T3
223 1/1 ns_cnt <= '0;
Tests: T1 T2 T3
224 end else begin
225 1/1 if (us_tick) begin
Tests: T1 T2 T3
226 1/1 ns_cnt <= '0;
Tests: T1 T2 T3
227 end else begin
228 1/1 ns_cnt <= ns_cnt + 1'b1;
Tests: T1 T2 T3
229 end
230 end
231 end
232
233 /////////////////////////////
234 // Receive interface fifos //
235 /////////////////////////////
236
237 logic avsetup_fifo_rst;
238 logic avsetup_fifo_wready;
239 logic avout_fifo_rst;
240 logic avout_fifo_wready;
241 logic event_pkt_received;
242 logic avsetup_rvalid, avsetup_rready;
243 logic avout_rvalid, avout_rready;
244 logic rx_fifo_rst;
245 logic rx_wvalid, rx_wready;
246 logic rx_wready_setup, rx_wready_out;
247 logic rx_fifo_rvalid;
248 logic rx_fifo_re;
249
250 logic [AVFifoWidth - 1:0] avsetup_rdata;
251 logic [AVFifoWidth - 1:0] avout_rdata;
252 logic [RXFifoWidth - 1:0] rx_wdata, rx_rdata;
253
254 logic [NEndpoints-1:0] clear_rxenable_out;
255
256 // Software reset signals
257 1/1 assign avsetup_fifo_rst = reg2hw.fifo_ctrl.avsetup_rst.qe & reg2hw.fifo_ctrl.avsetup_rst.q;
Tests: T1 T2 T3
258 1/1 assign avout_fifo_rst = reg2hw.fifo_ctrl.avout_rst.qe & reg2hw.fifo_ctrl.avout_rst.q;
Tests: T1 T2 T3
259 1/1 assign rx_fifo_rst = reg2hw.fifo_ctrl.rx_rst.qe & reg2hw.fifo_ctrl.rx_rst.q;
Tests: T1 T2 T3
260
261 // Separate 'FIFO empty' interrupts for the OUT and SETUP FIFOs because each interrupt cannot be
262 // cleared without writing a buffer into the FIFO
263 1/1 assign event_av_setup_empty = connect_en & ~avsetup_rvalid;
Tests: T1 T2 T3
264 1/1 assign event_av_out_empty = connect_en & ~avout_rvalid;
Tests: T1 T2 T3
265 // A single 'overflow' interrupt suffices since this indicates a programming error
266 1/1 assign event_av_overflow = (reg2hw.avsetupbuffer.qe & (~avsetup_fifo_wready))
Tests: T1 T2 T3
267 | (reg2hw.avoutbuffer.qe & (~avout_fifo_wready));
268 1/1 assign hw2reg.usbstat.rx_empty.d = connect_en & ~rx_fifo_rvalid;
Tests: T1 T2 T3
269
270 // Available SETUP Buffer FIFO
271 prim_fifo_sync #(
272 .Width(AVFifoWidth),
273 .Pass(1'b0),
274 .Depth(AVSetupFifoDepth),
275 .OutputZeroIfEmpty(1'b0)
276 ) usbdev_avsetupfifo (
277 .clk_i,
278 .rst_ni (rst_n),
279 .clr_i (avsetup_fifo_rst),
280
281 .wvalid_i (reg2hw.avsetupbuffer.qe),
282 .wready_o (avsetup_fifo_wready),
283 .wdata_i (reg2hw.avsetupbuffer.q),
284
285 .rvalid_o (avsetup_rvalid),
286 .rready_i (avsetup_rready),
287 .rdata_o (avsetup_rdata),
288 .full_o (hw2reg.usbstat.av_setup_full.d),
289 .depth_o (hw2reg.usbstat.av_setup_depth.d),
290 .err_o ()
291 );
292
293 // Available OUT Buffer FIFO
294 prim_fifo_sync #(
295 .Width(AVFifoWidth),
296 .Pass(1'b0),
297 .Depth(AVOutFifoDepth),
298 .OutputZeroIfEmpty(1'b0)
299 ) usbdev_avoutfifo (
300 .clk_i,
301 .rst_ni (rst_n),
302 .clr_i (avout_fifo_rst),
303
304 .wvalid_i (reg2hw.avoutbuffer.qe),
305 .wready_o (avout_fifo_wready),
306 .wdata_i (reg2hw.avoutbuffer.q),
307
308 .rvalid_o (avout_rvalid),
309 .rready_i (avout_rready),
310 .rdata_o (avout_rdata),
311 .full_o (hw2reg.usbstat.av_out_full.d),
312 .depth_o (hw2reg.usbstat.av_out_depth.d),
313 .err_o ()
314 );
315
316 1/1 assign rx_fifo_re = reg2hw.rxfifo.ep.re | reg2hw.rxfifo.setup.re |
Tests: T3 T29 T32
317 reg2hw.rxfifo.size.re | reg2hw.rxfifo.buffer.re;
318
319 // The number of used entries in the Received Buffer FIFO is presented to the software
320 logic [RXFifoDepthW-1:0] rx_depth;
321 1/1 assign hw2reg.usbstat.rx_depth.d = rx_depth;
Tests: T1 T2 T3
322
323 // We can always accept a SETUP packet if the Received Buffer FIFO is not full...
324 1/1 assign rx_wready_setup = rx_wready;
Tests: T1 T2 T3
325 // ... but regular OUT packets are not permitted to use the final entry; still qualified
326 // with 'rx_wready' for when reset is asserted.
327 1/1 assign rx_wready_out = rx_wready & (rx_depth < RXFifoDepthW'(RXFifoDepth - 1));
Tests: T1 T2 T3
328
329 // Received Buffer FIFO
330 prim_fifo_sync #(
331 .Width(RXFifoWidth),
332 .Pass(1'b0),
333 .Depth(RXFifoDepth),
334 .OutputZeroIfEmpty(1'b1)
335 ) usbdev_rxfifo (
336 .clk_i,
337 .rst_ni (rst_n),
338 .clr_i (rx_fifo_rst),
339
340 .wvalid_i (rx_wvalid),
341 .wready_o (rx_wready),
342 .wdata_i (rx_wdata),
343
344 .rvalid_o (rx_fifo_rvalid),
345 .rready_i (rx_fifo_re),
346 .rdata_o (rx_rdata),
347 .full_o (event_rx_full),
348 .depth_o (rx_depth),
349 .err_o ()
350 );
351
352 1/1 assign hw2reg.rxfifo.ep.d = rx_rdata[16:13];
Tests: T1 T2 T3
353 1/1 assign hw2reg.rxfifo.setup.d = rx_rdata[12];
Tests: T1 T2 T3
354 1/1 assign hw2reg.rxfifo.size.d = rx_rdata[11:5];
Tests: T1 T2 T3
355 1/1 assign hw2reg.rxfifo.buffer.d = rx_rdata[4:0];
Tests: T1 T2 T3
356 1/1 assign event_pkt_received = rx_fifo_rvalid;
Tests: T1 T2 T3
357
358 // The rxfifo register is hrw, but we just need the read enables.
359 logic [16:0] unused_rxfifo_q;
360 0/1 ==> assign unused_rxfifo_q = {reg2hw.rxfifo.ep.q, reg2hw.rxfifo.setup.q,
361 reg2hw.rxfifo.size.q, reg2hw.rxfifo.buffer.q};
362
363 ////////////////////////////////////
364 // IN (Transmit) interface config //
365 ////////////////////////////////////
366 logic [NBufWidth-1:0] in_buf [NEndpoints];
367 logic [SizeWidth:0] in_size [NEndpoints];
368 logic [3:0] in_endpoint;
369 logic in_endpoint_val;
370 logic [NEndpoints-1:0] in_rdy;
371 logic [NEndpoints-1:0] clear_rdybit, set_sentbit, update_pend, set_sending;
372 logic setup_received, in_ep_xact_end;
373 logic [NEndpoints-1:0] ep_out_iso, ep_in_iso;
374 logic [NEndpoints-1:0] enable_out, enable_setup, in_ep_stall, out_ep_stall;
375 logic [NEndpoints-1:0] ep_set_nak_on_out;
376 logic [NEndpoints-1:0] ep_in_enable, ep_out_enable;
377 logic [3:0] out_endpoint;
378 logic out_endpoint_val;
379 logic use_diff_rcvr, usb_diff_rx_ok;
380
381 // Endpoint enables
382 always_comb begin : proc_map_ep_enable
383 1/1 for (int i = 0; i < NEndpoints; i++) begin
Tests: T1 T2 T3
384 1/1 ep_in_enable[i] = reg2hw.ep_in_enable[i].q;
Tests: T1 T2 T3
385 1/1 ep_out_enable[i] = reg2hw.ep_out_enable[i].q;
Tests: T1 T2 T3
386 end
387 end
388
389 // RX enables
390 always_comb begin : proc_map_rxenable
391 1/1 for (int i = 0; i < NEndpoints; i++) begin
Tests: T1 T2 T3
392 1/1 enable_setup[i] = reg2hw.rxenable_setup[i].q;
Tests: T1 T2 T3
393 1/1 enable_out[i] = reg2hw.rxenable_out[i].q;
Tests: T1 T2 T3
394 1/1 ep_set_nak_on_out[i] = reg2hw.set_nak_out[i].q;
Tests: T1 T2 T3
395 end
396 end
397
398 // STALL for both directions
399 always_comb begin : proc_map_stall
400 1/1 for (int i = 0; i < NEndpoints; i++) begin
Tests: T1 T2 T3
401 1/1 in_ep_stall[i] = reg2hw.in_stall[i];
Tests: T1 T2 T3
402 1/1 out_ep_stall[i] = reg2hw.out_stall[i];
Tests: T1 T2 T3
403 end
404 end
405
406 always_comb begin : proc_map_iso
407 1/1 for (int i = 0; i < NEndpoints; i++) begin
Tests: T1 T2 T3
408 1/1 ep_out_iso[i] = reg2hw.out_iso[i].q;
Tests: T1 T2 T3
409 1/1 ep_in_iso[i] = reg2hw.in_iso[i].q;
Tests: T1 T2 T3
410 end
411 end
412
413 always_comb begin : proc_map_buf_size
414 1/1 for (int i = 0; i < NEndpoints; i++) begin
Tests: T1 T2 T3
415 1/1 in_buf[i] = reg2hw.configin[i].buffer.q;
Tests: T1 T2 T3
416 1/1 in_size[i] = reg2hw.configin[i].size.q;
Tests: T1 T2 T3
417 end
418 end
419
420 always_comb begin : proc_map_rdy_reg2hw
421 1/1 for (int i = 0; i < NEndpoints; i++) begin
Tests: T1 T2 T3
422 1/1 in_rdy[i] = reg2hw.configin[i].rdy.q;
Tests: T1 T2 T3
423 end
424 end
425
426 // Captured properties of current IN buffer, maintained throughout packet collection as
427 // protection against change during packet retraction by FW.
428 logic [NBufWidth-1:0] in_buf_q, in_buf_d;
429 logic [SizeWidth:0] in_size_q, in_size_d;
430 logic in_xact_starting;
431 logic [3:0] in_xact_start_ep;
432
433 always_ff @(posedge clk_i or negedge rst_n) begin
434 1/1 if (!rst_n) begin
Tests: T1 T2 T3
435 1/1 in_buf_q <= '0;
Tests: T1 T2 T3
436 1/1 in_size_q <= '0;
Tests: T1 T2 T3
437 end else begin
438 1/1 in_buf_q <= in_buf_d;
Tests: T1 T2 T3
439 1/1 in_size_q <= in_size_d;
Tests: T1 T2 T3
440 end
441 end
442 1/1 assign in_buf_d = in_xact_starting ? in_buf[in_xact_start_ep] : in_buf_q;
Tests: T1 T2 T3
443 1/1 assign in_size_d = in_xact_starting ? in_size[in_xact_start_ep] : in_size_q;
Tests: T1 T2 T3
444
445 // OUT data toggles are maintained with the packet engine but may be set or
446 // cleared by software
447 1/1 assign out_datatog_we = reg2hw.out_data_toggle.status.qe & reg2hw.out_data_toggle.mask.qe;
Tests: T29 T32 T37
448 1/1 assign out_datatog_status = reg2hw.out_data_toggle.status.q;
Tests: T1 T2 T3
449 1/1 assign out_datatog_mask = reg2hw.out_data_toggle.mask.q;
Tests: T1 T2 T3
450 // Software may read tham at any time
451 1/1 assign hw2reg.out_data_toggle.status.d = out_data_toggle;
Tests: T1 T2 T3
452 assign hw2reg.out_data_toggle.mask.d = {NEndpoints{1'b0}};
453
454 // IN data toggles are maintained with the packet engine but may be set or
455 // cleared by software
456 1/1 assign in_datatog_we = reg2hw.in_data_toggle.status.qe & reg2hw.in_data_toggle.mask.qe;
Tests: T29 T32 T109
457 1/1 assign in_datatog_status = reg2hw.in_data_toggle.status.q;
Tests: T1 T2 T3
458 1/1 assign in_datatog_mask = reg2hw.in_data_toggle.mask.q;
Tests: T1 T2 T3
459 // Software may read them at any time
460 1/1 assign hw2reg.in_data_toggle.status.d = in_data_toggle;
Tests: T1 T2 T3
461 assign hw2reg.in_data_toggle.mask.d = {NEndpoints{1'b0}};
462
463 always_comb begin
464 1/1 set_sentbit = '0;
Tests: T1 T2 T3
465 1/1 if (in_ep_xact_end && in_endpoint_val) begin
Tests: T1 T2 T3
466 1/1 set_sentbit[in_endpoint] = 1'b1;
Tests: T29 T32 T33
467 end
MISSING_ELSE
468 end
469
470 always_comb begin : proc_map_sent
471 1/1 for (int i = 0; i < NEndpoints; i++) begin
Tests: T29 T32 T33
472 1/1 hw2reg.in_sent[i].de = set_sentbit[i];
Tests: T29 T32 T33
473 1/1 hw2reg.in_sent[i].d = 1'b1;
Tests: T29 T32 T33
474 end
475 end
476
477 // This must be held level for the interrupt, so no sent packets are missed.
478 logic sent_event_pending;
479 always_comb begin
480 1/1 sent_event_pending = 1'b0;
Tests: T1 T2 T3
481 1/1 for (int i = 0; i < NEndpoints; i++) begin
Tests: T1 T2 T3
482 1/1 sent_event_pending |= reg2hw.in_sent[i].q;
Tests: T1 T2 T3
483 end
484 end
485
486 // Clear of rxenable_out bit
487 // If so configured, for every received transaction on a given endpoint, clear
488 // the rxenable_out bit. In this configuration, hardware defaults to NAKing
489 // any subsequent transaction, so software has time to decide the next
490 // response.
491 always_comb begin
492 1/1 clear_rxenable_out = '0;
Tests: T1 T2 T3
493 1/1 if (rx_wvalid && out_endpoint_val) begin
Tests: T1 T2 T3
494 1/1 clear_rxenable_out[out_endpoint] = ep_set_nak_on_out[out_endpoint];
Tests: T3 T28 T29
495 end
MISSING_ELSE
496 end
497
498 always_comb begin
499 1/1 for (int i = 0; i < NEndpoints; i++) begin
Tests: T72 T126 T141
500 1/1 hw2reg.rxenable_out[i].d = 1'b0;
Tests: T72 T126 T141
501 1/1 hw2reg.rxenable_out[i].de = clear_rxenable_out[i];
Tests: T72 T126 T141
502 end
503 end
504
505 always_comb begin
506 1/1 clear_rdybit = '0;
Tests: T1 T2 T3
507 1/1 update_pend = '0;
Tests: T1 T2 T3
508 1/1 if (event_link_reset) begin
Tests: T1 T2 T3
509 1/1 clear_rdybit = {NEndpoints{1'b1}};
Tests: T1 T2 T3
510 1/1 update_pend = {NEndpoints{1'b1}};
Tests: T1 T2 T3
511 end else begin
512 1/1 if (setup_received & out_endpoint_val) begin
Tests: T1 T2 T3
513 // Clear pending when a SETUP is received
514 1/1 clear_rdybit[out_endpoint] = 1'b1;
Tests: T3 T28 T30
515 1/1 update_pend[out_endpoint] = 1'b1;
Tests: T3 T28 T30
516 1/1 end else if (in_ep_xact_end & in_endpoint_val) begin
Tests: T1 T2 T3
517 // Clear rdy and sending when an IN transmission was successful
518 1/1 clear_rdybit[in_endpoint] = 1'b1;
Tests: T29 T32 T33
519 end
MISSING_ELSE
520 end
521 end
522
523 // IN transaction starting on any endpoint?
524 always_comb begin
525 1/1 set_sending = '0;
Tests: T1 T2 T3
526 2/2 if (in_xact_starting) set_sending[in_xact_start_ep] = 1'b1;
Tests: T1 T2 T3 | T29 T31 T32
MISSING_ELSE
527 end
528
529 // Clearing of rdy bit in response to successful IN packet transmission or packet cancellation
530 // through link reset or SETUP packet reception.
531 always_comb begin : proc_map_rdy_hw2reg
532 1/1 for (int i = 0; i < NEndpoints; i++) begin
Tests: T1 T2 T3
533 1/1 hw2reg.configin[i].rdy.de = clear_rdybit[i];
Tests: T1 T2 T3
534 1/1 hw2reg.configin[i].rdy.d = 1'b0;
Tests: T1 T2 T3
535 end
536 end
537
538 // Update the pending bit by copying the ready bit that is about to clear
539 always_comb begin : proc_map_pend
540 1/1 for (int i = 0; i < NEndpoints; i++) begin
Tests: T1 T2 T3
541 1/1 hw2reg.configin[i].pend.de = update_pend[i];
Tests: T1 T2 T3
542 1/1 hw2reg.configin[i].pend.d = reg2hw.configin[i].rdy.q | reg2hw.configin[i].pend.q;
Tests: T1 T2 T3
543 end
544 end
545
546 // Update the sending bit to mark that collection of the packet by the USB host has been
547 // attempted and FW shall not attempt retraction of the packet.
548 always_comb begin : proc_map_sending
549 1/1 for (int i = 0; i < NEndpoints; i++) begin
Tests: T1 T2 T3
550 1/1 hw2reg.configin[i].sending.de = set_sending[i] | set_sentbit[i] | update_pend[i];
Tests: T1 T2 T3
551 1/1 hw2reg.configin[i].sending.d = ~set_sentbit[i] & ~update_pend[i];
Tests: T1 T2 T3
552 end
553 end
554
555 ////////////////////////////////////////////////////////
556 // USB interface -- everything is in USB clock domain //
557 ////////////////////////////////////////////////////////
558 logic cfg_pinflip;
559 1/1 assign cfg_pinflip = reg2hw.phy_config.pinflip.q;
Tests: T1 T2 T3
560 1/1 assign usb_dp_pullup_en = cfg_pinflip ? 1'b0 : usb_pullup_en;
Tests: T1 T2 T3
561 1/1 assign usb_dn_pullup_en = !cfg_pinflip ? 1'b0 : usb_pullup_en;
Tests: T1 T2 T3
562
563
564 usbdev_usbif #(
565 .NEndpoints (NEndpoints),
566 .AVFifoWidth (AVFifoWidth),
567 .RXFifoWidth (RXFifoWidth),
568 .MaxPktSizeByte (MaxPktSizeByte),
569 .NBuf (NBuf),
570 .SramAw (SramAw)
571 ) usbdev_impl (
572 .clk_48mhz_i (clk_i),
573 .rst_ni (rst_n),
574
575 // Pins
576 .usb_d_i (usb_rx_d),
577 .usb_dp_i (usb_rx_dp),
578 .usb_dn_i (usb_rx_dn),
579 .usb_oe_o (usb_tx_oe),
580 .usb_d_o (usb_tx_d),
581 .usb_se0_o (usb_tx_se0),
582 .usb_dp_o (usb_tx_dp),
583 .usb_dn_o (usb_tx_dn),
584 .usb_sense_i (usb_pwr_sense),
585 .usb_pullup_en_o (usb_pullup_en),
586
587 // receive side
588 .rx_setup_i (enable_setup),
589 .rx_out_i (enable_out),
590 .rx_stall_i (out_ep_stall),
591 .avsetup_rvalid_i (avsetup_rvalid),
592 .avsetup_rready_o (avsetup_rready),
593 .avsetup_rdata_i (avsetup_rdata),
594 .avout_rvalid_i (avout_rvalid),
595 .avout_rready_o (avout_rready),
596 .avout_rdata_i (avout_rdata),
597
598 .rx_wvalid_o (rx_wvalid),
599 .rx_wready_setup_i (rx_wready_setup),
600 .rx_wready_out_i (rx_wready_out),
601 .rx_wdata_o (rx_wdata),
602 .setup_received_o (setup_received),
603 .out_endpoint_o (out_endpoint), // will be stable for several cycles
604 .out_endpoint_val_o (out_endpoint_val),
605
606 // transmit side
607 .in_xact_starting_o (in_xact_starting),
608 .in_xact_start_ep_o (in_xact_start_ep),
609 .in_buf_i (in_buf_q),
610 .in_size_i (in_size_q),
611 .in_stall_i (in_ep_stall),
612 .in_rdy_i (in_rdy),
613 .in_ep_xact_end_o (in_ep_xact_end),
614 .in_endpoint_o (in_endpoint),
615 .in_endpoint_val_o (in_endpoint_val),
616
617 // memory
618 .mem_req_o (usb_mem_b_req),
619 .mem_write_o (usb_mem_b_write),
620 .mem_addr_o (usb_mem_b_addr),
621 .mem_wdata_o (usb_mem_b_wdata),
622 .mem_rdata_i (usb_mem_b_rdata),
623
624 // time reference
625 .us_tick_i (us_tick),
626
627 // control
628 .connect_en_i (connect_en),
629 .devaddr_i (reg2hw.usbctrl.device_address.q),
630 .clr_devaddr_o (clr_devaddr),
631 .in_ep_enabled_i (ep_in_enable),
632 .out_ep_enabled_i (ep_out_enable),
633 .out_ep_iso_i (ep_out_iso),
634 .in_ep_iso_i (ep_in_iso),
635 .diff_rx_ok_i (usb_diff_rx_ok),
636 .cfg_eop_single_bit_i (reg2hw.phy_config.eop_single_bit.q), // cdc ok: quasi-static
637 .tx_osc_test_mode_i (reg2hw.phy_config.tx_osc_test_mode.q), // cdc ok: quasi-static
638 .cfg_use_diff_rcvr_i (usb_rx_enable_o),
639 .cfg_pinflip_i (cfg_pinflip),
640 .out_data_toggle_o (out_data_toggle),
641 .out_datatog_we_i (out_datatog_we),
642 .out_datatog_status_i (out_datatog_status),
643 .out_datatog_mask_i (out_datatog_mask),
644 .in_data_toggle_o (in_data_toggle),
645 .in_datatog_we_i (in_datatog_we),
646 .in_datatog_status_i (in_datatog_status),
647 .in_datatog_mask_i (in_datatog_mask),
648
649 .resume_link_active_i (resume_link_active),
650
651 // status
652 .frame_o (frame),
653 .frame_start_o (event_frame),
654 .sof_detected_o (event_sof),
655 .link_state_o (link_state),
656 .link_disconnect_o (link_disconnect),
657 .link_powered_o (link_powered),
658 .link_reset_o (link_reset),
659 .link_active_o (link_active),
660 .link_suspend_o (link_suspend),
661 .link_resume_o (event_link_resume),
662 .host_lost_o (host_lost),
663 .link_in_err_o (event_in_err),
664 .link_out_err_o (event_out_err),
665 .rx_crc5_err_o (event_rx_crc5_err),
666 .rx_crc16_err_o (event_rx_crc16_err),
667 .rx_pid_err_o (event_rx_pid_err),
668 .rx_bitstuff_err_o (event_rx_bitstuff_err),
669
670 // event counters
671 .event_ign_avsetup_o (event_ign_avsetup),
672 .event_drop_avout_o (event_drop_avout),
673 .event_drop_rx_o (event_drop_rx),
674 .event_datatog_out_o (event_datatog_out),
675 .event_timeout_in_o (event_timeout_in),
676 .event_nak_in_o (event_nak_in),
677 .event_nodata_in_o (event_nodata_in)
678 );
679
680 /////////////////////////////////
681 // Control signal / status CDC //
682 /////////////////////////////////
683
684 1/1 assign hw2reg.usbstat.link_state.d = link_state;
Tests: T1 T2 T3
685 1/1 assign hw2reg.usbstat.frame.d = frame;
Tests: T1 T2 T3
686
687 1/1 assign connect_en = reg2hw.usbctrl.enable.q;
Tests: T1 T2 T3
688 1/1 assign resume_link_active = reg2hw.usbctrl.resume_link_active.qe &
Tests: T1 T2 T3
689 reg2hw.usbctrl.resume_link_active.q;
690
691 // Just want a pulse to ensure only one interrupt for an event
692 prim_edge_detector #(
693 .Width(5),
694 .EnSync(1'b0)
695 ) gen_event (
696 .clk_i,
697 .rst_ni (rst_n),
698 .d_i ({link_disconnect, link_reset, link_suspend,
699 host_lost, link_powered}),
700 .q_sync_o (),
701 .q_posedge_pulse_o({event_disconnect, event_link_reset, event_link_suspend,
702 event_host_lost, event_powered}),
703 .q_negedge_pulse_o()
704 );
705
706 1/1 assign hw2reg.usbstat.host_lost.d = host_lost;
Tests: T1 T2 T3
707
708 // resets etc cause the device address to clear
709 1/1 assign hw2reg.usbctrl.device_address.de = clr_devaddr;
Tests: T1 T2 T3
710 assign hw2reg.usbctrl.device_address.d = '0;
711
712 // Clear the stall flag when a SETUP is received
713
714 always_comb begin : proc_stall_tieoff
715 1/1 for (int i = 0; i < NEndpoints; i++) begin
Tests: T1 T2 T3
716 1/1 hw2reg.in_stall[i].d = 1'b0;
Tests: T1 T2 T3
717 1/1 hw2reg.out_stall[i].d = 1'b0;
Tests: T1 T2 T3
718 1/1 if (setup_received && out_endpoint_val && out_endpoint == 4'(unsigned'(i))) begin
Tests: T1 T2 T3
719 1/1 hw2reg.out_stall[i].de = 1'b1;
Tests: T3 T28 T30
720 1/1 hw2reg.in_stall[i].de = 1'b1;
Tests: T3 T28 T30
721 end else begin
722 1/1 hw2reg.out_stall[i].de = 1'b0;
Tests: T1 T2 T3
723 1/1 hw2reg.in_stall[i].de = 1'b0;
Tests: T1 T2 T3
724 end
725 end
726 end
727
728 if (Stub) begin : gen_stubbed_memory
729 // Stub this window off with an error responder if stubbed.
730 tlul_err_resp u_tlul_err_resp (
731 .clk_i,
732 .rst_ni,
733 .tl_h_i(tl_sram_h2d),
734 .tl_h_o(tl_sram_d2h)
735 );
736
737 // Tie off unused signals
738 assign sw_mem_a_req = '0;
739 assign sw_mem_a_gnt = '0;
740 assign sw_mem_a_write = '0;
741 assign sw_mem_a_addr = '0;
742 assign sw_mem_a_wdata = '0;
743 assign sw_mem_a_rvalid = '0;
744 assign sw_mem_a_rdata = '0;
745 assign sw_mem_a_rerror = '0;
746
747 assign usb_mem_b_rdata = '0;
748
749 logic unused_usb_mem_b_sigs;
750 assign unused_usb_mem_b_sigs = ^{
751 ram_cfg_i,
752 usb_mem_b_req,
753 usb_mem_b_write,
754 usb_mem_b_addr,
755 usb_mem_b_wdata,
756 usb_mem_b_rdata
757 };
758 end else begin : gen_no_stubbed_memory
759 // TL-UL to SRAM adapter
760 tlul_adapter_sram #(
761 .SramAw(SramAw),
762 .ByteAccess(0)
763 ) u_tlul2sram (
764 .clk_i,
765 .rst_ni,
766
767 .tl_i (tl_sram_h2d),
768 .tl_o (tl_sram_d2h),
769 .en_ifetch_i (prim_mubi_pkg::MuBi4False),
770 .req_o (sw_mem_a_req),
771 .req_type_o (),
772 .gnt_i (sw_mem_a_gnt),
773 .we_o (sw_mem_a_write),
774 .addr_o (sw_mem_a_addr),
775 .wdata_o (sw_mem_a_wdata),
776 .wmask_o (), // Not used
777 .intg_error_o (),
778 .rdata_i (sw_mem_a_rdata),
779 .rvalid_i (sw_mem_a_rvalid),
780 .rerror_i (sw_mem_a_rerror),
781 .compound_txn_in_progress_o (),
782 .readback_en_i (prim_mubi_pkg::MuBi4False),
783 .readback_error_o (),
784 .wr_collision_i (1'b0),
785 .write_pending_i (1'b0)
786 );
787
788 // Single Port RAM implementation, which will award the `usb` port absolute priority and
789 // delay `sw` access by in the event of a collision.
790 //
791 // In practice the `usb` access to memory is sporadic (4x oversampling of bits, and read/write
792 // operations transfer 32 bits so on average the probability of collision is just 1/128 even
793 // during active USB traffic, if the TL-UL interface were active on every cycle).
794
795 // usb access has absolute priority, followed by any deferred write, and then any sw access.
796 logic mem_req;
797 logic mem_write;
798 logic [SramAw-1:0] mem_addr;
799 logic [SramDw-1:0] mem_wdata;
800 1/1 assign mem_req = usb_mem_b_req | sw_mem_a_req;
Tests: T1 T2 T3
801 1/1 assign mem_write = usb_mem_b_req ? usb_mem_b_write : sw_mem_a_write;
Tests: T1 T2 T3
802 1/1 assign mem_addr = usb_mem_b_req ? usb_mem_b_addr : sw_mem_a_addr;
Tests: T1 T2 T3
803 1/1 assign mem_wdata = usb_mem_b_req ? usb_mem_b_wdata : sw_mem_a_wdata;
Tests: T1 T2 T3
804
805 logic mem_rvalid;
806 logic [SramDw-1:0] mem_rdata;
807 logic [1:0] mem_rerror;
808 logic mem_rsteering;
809
810 // Always grant when no `usb` request.
811 1/1 assign sw_mem_a_gnt = !usb_mem_b_req;
Tests: T1 T2 T3
812
813 // `usb` relies upon its read data remaining static after read.
814 logic mem_b_read_q;
815 logic [SramDw-1:0] mem_b_rdata_q;
816
817 // Remember granted read accesses.
818 // NOTE: No pipelining within the RAM model.
819 always_ff @(posedge clk_i or negedge rst_ni) begin
820 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
821 1/1 mem_rsteering <= 1'b0;
Tests: T1 T2 T3
822 1/1 mem_b_read_q <= 1'b0;
Tests: T1 T2 T3
823 1/1 mem_b_rdata_q <= {SramDw{1'b0}};
Tests: T1 T2 T3
824 end else begin
825 1/1 mem_rsteering <= usb_mem_b_req;
Tests: T1 T2 T3
826 1/1 mem_b_read_q <= usb_mem_b_req & !usb_mem_b_write;
Tests: T1 T2 T3
827 // Capture the `usb` read data.
828 1/1 if (mem_b_read_q)
Tests: T1 T2 T3
829 1/1 mem_b_rdata_q <= mem_rdata;
Tests: T29 T31 T32
MISSING_ELSE
830 end
831 end
832
833 // Read responses.
834 1/1 assign sw_mem_a_rvalid = mem_rvalid & !mem_rsteering;
Tests: T1 T2 T3
835 unreachable assign sw_mem_a_rerror = {2{sw_mem_a_rvalid}} & mem_rerror;
836 // We may safely return the read data to both (no security implications), but `usb` rdata
837 // must be held static after the read, and be unaffected by `sw` reads.
838 1/1 assign sw_mem_a_rdata = mem_rdata;
Tests: T3 T29 T32
839 1/1 assign usb_mem_b_rdata = mem_b_read_q ? mem_rdata : mem_b_rdata_q;
Tests: T1 T2 T3
840
841 // SRAM Wrapper
842 prim_ram_1p_adv #(
843 .Depth (SramDepth),
844 .Width (SramDw), // 32 x 512 --> 2kB
845 .DataBitsPerMask(8),
846
847 .EnableECC (0), // No Protection
848 .EnableParity (0),
849 .EnableInputPipeline (0),
850 .EnableOutputPipeline(0)
851 ) u_memory_1p (
852 .clk_i,
853 .rst_ni,
854
855 .req_i (mem_req),
856 .write_i (mem_write),
857 .addr_i (mem_addr),
858 .wdata_i (mem_wdata),
859 .wmask_i ({SramDw{1'b1}}),
860 .rdata_o (mem_rdata),
861 .rvalid_o (mem_rvalid),
862 .rerror_o (mem_rerror),
863 .cfg_i (ram_cfg_i),
864 .alert_o ()
865 );
866 end : gen_no_stubbed_memory
867
868 logic [NumAlerts-1:0] alert_test, alerts;
869
870 // Register module
871 usbdev_reg_top u_reg (
872 .clk_i,
873 .rst_ni, // this reset is not stubbed off so that the registers are still accessible.
874 .clk_aon_i,
875 .rst_aon_ni, // this reset is not stubbed off so that the registers are still accessible.
876
877 .tl_i (tl_i),
878 .tl_o (tl_o),
879
880 .tl_win_o (tl_sram_h2d),
881 .tl_win_i (tl_sram_d2h),
882
883 .reg2hw(reg2hw_regtop),
884 .hw2reg(hw2reg_regtop),
885
886 // SEC_CM: BUS.INTEGRITY
887 .intg_err_o (alerts[0])
888 );
889
890 // Stub off all register connections to reg_top.
891 if (Stub) begin : gen_stubbed
892 logic unused_sigs;
893 assign reg2hw = '0;
894 assign hw2reg_regtop = '0;
895 assign unused_sigs = ^{reg2hw_regtop, hw2reg};
896 end else begin : gen_not_stubbed
897 1/1 assign reg2hw = reg2hw_regtop;
Tests: T1 T2 T3
898 1/1 assign hw2reg_regtop = hw2reg;
Tests: T1 T2 T3
899 end
900
901 // Alerts
902 1/1 assign alert_test = {
Tests: T1 T2 T3
903 reg2hw.alert_test.q &
904 reg2hw.alert_test.qe
905 };
906
907 // Alerts not stubbed off because registers and T-L access still present.
908 localparam logic [NumAlerts-1:0] AlertIsFatal = {NumAlerts{1'b1}};
909 for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx
910 prim_alert_sender #(
911 .AsyncOn(AlertAsyncOn[i]),
912 .IsFatal(AlertIsFatal[i])
913 ) u_prim_alert_sender (
914 .clk_i,
915 .rst_ni, // this reset is not stubbed off so that the pings still work.
916 .alert_test_i ( alert_test[i] ),
917 .alert_req_i ( alerts[0] ),
918 .alert_ack_o ( ),
919 .alert_state_o ( ),
920 .alert_rx_i ( alert_rx_i[i] ),
921 .alert_tx_o ( alert_tx_o[i] )
922 );
923 end
924
925 // Interrupts
926 prim_intr_hw #(.Width(1), .IntrT("Status")) intr_hw_pkt_received (
927 .clk_i,
928 .rst_ni, // not stubbed off so that the interrupt regs still work.
929 .event_intr_i (event_pkt_received),
930 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.pkt_received.q),
931 .reg2hw_intr_test_q_i (reg2hw.intr_test.pkt_received.q),
932 .reg2hw_intr_test_qe_i (reg2hw.intr_test.pkt_received.qe),
933 .reg2hw_intr_state_q_i (reg2hw.intr_state.pkt_received.q),
934 .hw2reg_intr_state_de_o (hw2reg.intr_state.pkt_received.de),
935 .hw2reg_intr_state_d_o (hw2reg.intr_state.pkt_received.d),
936 .intr_o (intr_pkt_received_o)
937 );
938
939 prim_intr_hw #(.Width(1), .IntrT("Status")) intr_hw_pkt_sent (
940 .clk_i,
941 .rst_ni, // not stubbed off so that the interrupt regs still work.
942 .event_intr_i (sent_event_pending),
943 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.pkt_sent.q),
944 .reg2hw_intr_test_q_i (reg2hw.intr_test.pkt_sent.q),
945 .reg2hw_intr_test_qe_i (reg2hw.intr_test.pkt_sent.qe),
946 .reg2hw_intr_state_q_i (reg2hw.intr_state.pkt_sent.q),
947 .hw2reg_intr_state_de_o (hw2reg.intr_state.pkt_sent.de),
948 .hw2reg_intr_state_d_o (hw2reg.intr_state.pkt_sent.d),
949 .intr_o (intr_pkt_sent_o)
950 );
951
952 prim_intr_hw #(.Width(1)) intr_disconnected (
953 .clk_i,
954 .rst_ni, // not stubbed off so that the interrupt regs still work.
955 .event_intr_i (event_disconnect),
956 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.disconnected.q),
957 .reg2hw_intr_test_q_i (reg2hw.intr_test.disconnected.q),
958 .reg2hw_intr_test_qe_i (reg2hw.intr_test.disconnected.qe),
959 .reg2hw_intr_state_q_i (reg2hw.intr_state.disconnected.q),
960 .hw2reg_intr_state_de_o (hw2reg.intr_state.disconnected.de),
961 .hw2reg_intr_state_d_o (hw2reg.intr_state.disconnected.d),
962 .intr_o (intr_disconnected_o)
963 );
964
965 prim_intr_hw #(.Width(1)) intr_powered (
966 .clk_i,
967 .rst_ni, // not stubbed off so that the interrupt regs still work.
968 .event_intr_i (event_powered),
969 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.powered.q),
970 .reg2hw_intr_test_q_i (reg2hw.intr_test.powered.q),
971 .reg2hw_intr_test_qe_i (reg2hw.intr_test.powered.qe),
972 .reg2hw_intr_state_q_i (reg2hw.intr_state.powered.q),
973 .hw2reg_intr_state_de_o (hw2reg.intr_state.powered.de),
974 .hw2reg_intr_state_d_o (hw2reg.intr_state.powered.d),
975 .intr_o (intr_powered_o)
976 );
977
978 prim_intr_hw #(.Width(1)) intr_host_lost (
979 .clk_i,
980 .rst_ni, // not stubbed off so that the interrupt regs still work.
981 .event_intr_i (event_host_lost),
982 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.host_lost.q),
983 .reg2hw_intr_test_q_i (reg2hw.intr_test.host_lost.q),
984 .reg2hw_intr_test_qe_i (reg2hw.intr_test.host_lost.qe),
985 .reg2hw_intr_state_q_i (reg2hw.intr_state.host_lost.q),
986 .hw2reg_intr_state_de_o (hw2reg.intr_state.host_lost.de),
987 .hw2reg_intr_state_d_o (hw2reg.intr_state.host_lost.d),
988 .intr_o (intr_host_lost_o)
989 );
990
991 prim_intr_hw #(.Width(1)) intr_link_reset (
992 .clk_i,
993 .rst_ni, // not stubbed off so that the interrupt regs still work.
994 .event_intr_i (event_link_reset),
995 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.link_reset.q),
996 .reg2hw_intr_test_q_i (reg2hw.intr_test.link_reset.q),
997 .reg2hw_intr_test_qe_i (reg2hw.intr_test.link_reset.qe),
998 .reg2hw_intr_state_q_i (reg2hw.intr_state.link_reset.q),
999 .hw2reg_intr_state_de_o (hw2reg.intr_state.link_reset.de),
1000 .hw2reg_intr_state_d_o (hw2reg.intr_state.link_reset.d),
1001 .intr_o (intr_link_reset_o)
1002 );
1003
1004 prim_intr_hw #(.Width(1)) intr_link_suspend (
1005 .clk_i,
1006 .rst_ni, // not stubbed off so that the interrupt regs still work.
1007 .event_intr_i (event_link_suspend),
1008 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.link_suspend.q),
1009 .reg2hw_intr_test_q_i (reg2hw.intr_test.link_suspend.q),
1010 .reg2hw_intr_test_qe_i (reg2hw.intr_test.link_suspend.qe),
1011 .reg2hw_intr_state_q_i (reg2hw.intr_state.link_suspend.q),
1012 .hw2reg_intr_state_de_o (hw2reg.intr_state.link_suspend.de),
1013 .hw2reg_intr_state_d_o (hw2reg.intr_state.link_suspend.d),
1014 .intr_o (intr_link_suspend_o)
1015 );
1016
1017 prim_intr_hw #(.Width(1)) intr_link_resume (
1018 .clk_i,
1019 .rst_ni, // not stubbed off so that the interrupt regs still work.
1020 .event_intr_i (event_link_resume),
1021 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.link_resume.q),
1022 .reg2hw_intr_test_q_i (reg2hw.intr_test.link_resume.q),
1023 .reg2hw_intr_test_qe_i (reg2hw.intr_test.link_resume.qe),
1024 .reg2hw_intr_state_q_i (reg2hw.intr_state.link_resume.q),
1025 .hw2reg_intr_state_de_o (hw2reg.intr_state.link_resume.de),
1026 .hw2reg_intr_state_d_o (hw2reg.intr_state.link_resume.d),
1027 .intr_o (intr_link_resume_o)
1028 );
1029
1030 prim_intr_hw #(.Width(1), .IntrT("Status")) intr_av_out_empty (
1031 .clk_i,
1032 .rst_ni, // not stubbed off so that the interrupt regs still work.
1033 .event_intr_i (event_av_out_empty),
1034 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.av_out_empty.q),
1035 .reg2hw_intr_test_q_i (reg2hw.intr_test.av_out_empty.q),
1036 .reg2hw_intr_test_qe_i (reg2hw.intr_test.av_out_empty.qe),
1037 .reg2hw_intr_state_q_i (reg2hw.intr_state.av_out_empty.q),
1038 .hw2reg_intr_state_de_o (hw2reg.intr_state.av_out_empty.de),
1039 .hw2reg_intr_state_d_o (hw2reg.intr_state.av_out_empty.d),
1040 .intr_o (intr_av_out_empty_o)
1041 );
1042
1043 prim_intr_hw #(.Width(1), .IntrT("Status")) intr_rx_full (
1044 .clk_i,
1045 .rst_ni, // not stubbed off so that the interrupt regs still work.
1046 .event_intr_i (event_rx_full),
1047 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rx_full.q),
1048 .reg2hw_intr_test_q_i (reg2hw.intr_test.rx_full.q),
1049 .reg2hw_intr_test_qe_i (reg2hw.intr_test.rx_full.qe),
1050 .reg2hw_intr_state_q_i (reg2hw.intr_state.rx_full.q),
1051 .hw2reg_intr_state_de_o (hw2reg.intr_state.rx_full.de),
1052 .hw2reg_intr_state_d_o (hw2reg.intr_state.rx_full.d),
1053 .intr_o (intr_rx_full_o)
1054 );
1055
1056 prim_intr_hw #(.Width(1)) intr_av_overflow (
1057 .clk_i,
1058 .rst_ni, // not stubbed off so that the interrupt regs still work.
1059 .event_intr_i (event_av_overflow),
1060 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.av_overflow.q),
1061 .reg2hw_intr_test_q_i (reg2hw.intr_test.av_overflow.q),
1062 .reg2hw_intr_test_qe_i (reg2hw.intr_test.av_overflow.qe),
1063 .reg2hw_intr_state_q_i (reg2hw.intr_state.av_overflow.q),
1064 .hw2reg_intr_state_de_o (hw2reg.intr_state.av_overflow.de),
1065 .hw2reg_intr_state_d_o (hw2reg.intr_state.av_overflow.d),
1066 .intr_o (intr_av_overflow_o)
1067 );
1068
1069 prim_intr_hw #(.Width(1)) intr_link_in_err (
1070 .clk_i,
1071 .rst_ni, // not stubbed off so that the interrupt regs still work.
1072 .event_intr_i (event_in_err),
1073 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.link_in_err.q),
1074 .reg2hw_intr_test_q_i (reg2hw.intr_test.link_in_err.q),
1075 .reg2hw_intr_test_qe_i (reg2hw.intr_test.link_in_err.qe),
1076 .reg2hw_intr_state_q_i (reg2hw.intr_state.link_in_err.q),
1077 .hw2reg_intr_state_de_o (hw2reg.intr_state.link_in_err.de),
1078 .hw2reg_intr_state_d_o (hw2reg.intr_state.link_in_err.d),
1079 .intr_o (intr_link_in_err_o)
1080 );
1081
1082 prim_intr_hw #(.Width(1)) intr_link_out_err (
1083 .clk_i,
1084 .rst_ni, // not stubbed off so that the interrupt regs still work.
1085 .event_intr_i (event_out_err),
1086 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.link_out_err.q),
1087 .reg2hw_intr_test_q_i (reg2hw.intr_test.link_out_err.q),
1088 .reg2hw_intr_test_qe_i (reg2hw.intr_test.link_out_err.qe),
1089 .reg2hw_intr_state_q_i (reg2hw.intr_state.link_out_err.q),
1090 .hw2reg_intr_state_de_o (hw2reg.intr_state.link_out_err.de),
1091 .hw2reg_intr_state_d_o (hw2reg.intr_state.link_out_err.d),
1092 .intr_o (intr_link_out_err_o)
1093 );
1094
1095 prim_intr_hw #(.Width(1)) intr_rx_crc_err (
1096 .clk_i,
1097 .rst_ni, // not stubbed off so that the interrupt regs still work.
1098 .event_intr_i (event_rx_crc_err),
1099 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rx_crc_err.q),
1100 .reg2hw_intr_test_q_i (reg2hw.intr_test.rx_crc_err.q),
1101 .reg2hw_intr_test_qe_i (reg2hw.intr_test.rx_crc_err.qe),
1102 .reg2hw_intr_state_q_i (reg2hw.intr_state.rx_crc_err.q),
1103 .hw2reg_intr_state_de_o (hw2reg.intr_state.rx_crc_err.de),
1104 .hw2reg_intr_state_d_o (hw2reg.intr_state.rx_crc_err.d),
1105 .intr_o (intr_rx_crc_err_o)
1106 );
1107
1108 prim_intr_hw #(.Width(1)) intr_rx_pid_err (
1109 .clk_i,
1110 .rst_ni, // not stubbed off so that the interrupt regs still work.
1111 .event_intr_i (event_rx_pid_err),
1112 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rx_pid_err.q),
1113 .reg2hw_intr_test_q_i (reg2hw.intr_test.rx_pid_err.q),
1114 .reg2hw_intr_test_qe_i (reg2hw.intr_test.rx_pid_err.qe),
1115 .reg2hw_intr_state_q_i (reg2hw.intr_state.rx_pid_err.q),
1116 .hw2reg_intr_state_de_o (hw2reg.intr_state.rx_pid_err.de),
1117 .hw2reg_intr_state_d_o (hw2reg.intr_state.rx_pid_err.d),
1118 .intr_o (intr_rx_pid_err_o)
1119 );
1120
1121 prim_intr_hw #(.Width(1)) intr_rx_bitstuff_err (
1122 .clk_i,
1123 .rst_ni, // not stubbed off so that the interrupt regs still work.
1124 .event_intr_i (event_rx_bitstuff_err),
1125 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rx_bitstuff_err.q),
1126 .reg2hw_intr_test_q_i (reg2hw.intr_test.rx_bitstuff_err.q),
1127 .reg2hw_intr_test_qe_i (reg2hw.intr_test.rx_bitstuff_err.qe),
1128 .reg2hw_intr_state_q_i (reg2hw.intr_state.rx_bitstuff_err.q),
1129 .hw2reg_intr_state_de_o (hw2reg.intr_state.rx_bitstuff_err.de),
1130 .hw2reg_intr_state_d_o (hw2reg.intr_state.rx_bitstuff_err.d),
1131 .intr_o (intr_rx_bitstuff_err_o)
1132 );
1133
1134 prim_intr_hw #(.Width(1)) intr_frame (
1135 .clk_i,
1136 .rst_ni, // not stubbed off so that the interrupt regs still work.
1137 .event_intr_i (event_frame),
1138 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.frame.q),
1139 .reg2hw_intr_test_q_i (reg2hw.intr_test.frame.q),
1140 .reg2hw_intr_test_qe_i (reg2hw.intr_test.frame.qe),
1141 .reg2hw_intr_state_q_i (reg2hw.intr_state.frame.q),
1142 .hw2reg_intr_state_de_o (hw2reg.intr_state.frame.de),
1143 .hw2reg_intr_state_d_o (hw2reg.intr_state.frame.d),
1144 .intr_o (intr_frame_o)
1145 );
1146
1147 prim_intr_hw #(.Width(1), .IntrT("Status")) intr_av_setup_empty (
1148 .clk_i,
1149 .rst_ni, // not stubbed off so that the interrupt regs still work.
1150 .event_intr_i (event_av_setup_empty),
1151 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.av_setup_empty.q),
1152 .reg2hw_intr_test_q_i (reg2hw.intr_test.av_setup_empty.q),
1153 .reg2hw_intr_test_qe_i (reg2hw.intr_test.av_setup_empty.qe),
1154 .reg2hw_intr_state_q_i (reg2hw.intr_state.av_setup_empty.q),
1155 .hw2reg_intr_state_de_o (hw2reg.intr_state.av_setup_empty.de),
1156 .hw2reg_intr_state_d_o (hw2reg.intr_state.av_setup_empty.d),
1157 .intr_o (intr_av_setup_empty_o)
1158 );
1159
1160 /////////////////////////////////
1161 // USB IO Muxing //
1162 /////////////////////////////////
1163 logic cio_usb_oe;
1164 logic usb_rx_enable;
1165 1/1 assign cio_usb_dp_en_o = cio_usb_oe;
Tests: T1 T2 T3
1166 1/1 assign cio_usb_dn_en_o = cio_usb_oe;
Tests: T1 T2 T3
1167 1/1 assign usb_tx_use_d_se0_o = reg2hw.phy_config.tx_use_d_se0.q; // cdc ok: quasi-static
Tests: T1 T2 T3
1168 1/1 assign hw2reg.usbstat.sense.d = usb_pwr_sense;
Tests: T1 T2 T3
1169
1170 usbdev_iomux i_usbdev_iomux (
1171 .clk_i,
1172 .rst_ni (rst_n),
1173
1174 // Register interface
1175 .hw2reg_sense_o (hw2reg.phy_pins_sense),
1176 .reg2hw_drive_i (reg2hw.phy_pins_drive),
1177
1178 // Chip IO
1179 .usb_rx_d_i (usb_rx_d_i),
1180 .usb_rx_dp_i (cio_usb_dp_i),
1181 .usb_rx_dn_i (cio_usb_dn_i),
1182 .cio_usb_sense_i (cio_sense_i),
1183 .usb_tx_d_o (usb_tx_d_o),
1184 .usb_tx_se0_o (usb_tx_se0_o),
1185 .usb_tx_dp_o (cio_usb_dp_o),
1186 .usb_tx_dn_o (cio_usb_dn_o),
1187 .usb_tx_oe_o (cio_usb_oe),
1188 .usb_dp_pullup_en_o (usb_dp_pullup_o),
1189 .usb_dn_pullup_en_o (usb_dn_pullup_o),
1190 .usb_rx_enable_o (usb_rx_enable_o),
1191
1192 // Internal interface
1193 .usb_rx_d_o (usb_rx_d),
1194 .usb_rx_dp_o (usb_rx_dp),
1195 .usb_rx_dn_o (usb_rx_dn),
1196 .usb_tx_d_i (usb_tx_d),
1197 .usb_tx_se0_i (usb_tx_se0),
1198 .usb_tx_dp_i (usb_tx_dp),
1199 .usb_tx_dn_i (usb_tx_dn),
1200 .usb_tx_oe_i (usb_tx_oe),
1201 .usb_pwr_sense_o (usb_pwr_sense),
1202 .usb_dp_pullup_en_i (usb_dp_pullup_en),
1203 .usb_dn_pullup_en_i (usb_dn_pullup_en),
1204 .usb_rx_enable_i (usb_rx_enable)
1205 );
1206
1207 // Differential receiver enable
1208 1/1 assign use_diff_rcvr = reg2hw.phy_config.use_diff_rcvr.q;
Tests: T1 T2 T3
1209 // enable rx only when the single-ended input is enabled and the device is
1210 // not suspended (unless it is forced on in the I/O mux).
1211 1/1 assign usb_rx_enable = use_diff_rcvr & ~link_suspend;
Tests: T1 T2 T3
1212
1213 // Symbols from the differential receiver are invalid until it has finished
1214 // waking up / powering on
1215 // Add 1 to the specified time to account for uncertainty in the
1216 // free-running counter for us_tick.
1217 localparam int RcvrWakeTimeWidth = vbits(RcvrWakeTimeUs + 2);
1218 logic [RcvrWakeTimeWidth-1:0] usb_rcvr_ok_counter_d, usb_rcvr_ok_counter_q;
1219
1220 1/1 assign usb_diff_rx_ok = (usb_rcvr_ok_counter_q == '0);
Tests: T1 T2 T3
1221 always_comb begin
1222 // When don't need to use a differential receiver, RX is always ready
1223 1/1 usb_rcvr_ok_counter_d = '0;
Tests: T1 T2 T3
1224 1/1 if (use_diff_rcvr & !usb_rx_enable_o) begin
Tests: T1 T2 T3
1225 1/1 usb_rcvr_ok_counter_d = RcvrWakeTimeWidth'(RcvrWakeTimeUs + 1);
Tests: T7 T18 T8
1226 1/1 end else if (us_tick && (usb_rcvr_ok_counter_q > '0)) begin
Tests: T1 T2 T3
1227 1/1 usb_rcvr_ok_counter_d = usb_rcvr_ok_counter_q - 1;
Tests: T203 T204 T205
1228 end
MISSING_ELSE
1229 end
1230
1231 always_ff @(posedge clk_i or negedge rst_n) begin
1232 1/1 if (!rst_n) begin
Tests: T1 T2 T3
1233 1/1 usb_rcvr_ok_counter_q <= RcvrWakeTimeWidth'(RcvrWakeTimeUs + 1);
Tests: T1 T2 T3
1234 end else begin
1235 1/1 usb_rcvr_ok_counter_q <= usb_rcvr_ok_counter_d;
Tests: T1 T2 T3
1236 end
1237 end
1238
1239 /////////////////////////////////////////
1240 // SOF Reference for Clock Calibration //
1241 /////////////////////////////////////////
1242
1243 logic usb_ref_val_d, usb_ref_val_q;
1244 logic usb_ref_disable;
1245 1/1 assign usb_ref_disable = reg2hw.phy_config.usb_ref_disable.q;
Tests: T1 T2 T3
1246
1247 // Directly forward the pulse unless disabled.
1248 1/1 assign usb_ref_pulse_o = usb_ref_disable ? 1'b0 : event_sof;
Tests: T1 T2 T3
1249
1250 // The first pulse is always ignored, but causes the valid to be asserted.
1251 // The valid signal is deasserted when:
1252 // - The link is no longer active.
1253 // - The host is lost (no SOF for 4ms).
1254 // - The reference generation is disabled.
1255 1/1 assign usb_ref_val_d = usb_ref_pulse_o ? 1'b1 :
Tests: T1 T2 T3
1256 (!link_active || host_lost || usb_ref_disable) ? 1'b0 : usb_ref_val_q;
1257
1258 always_ff @(posedge clk_i or negedge rst_n) begin
1259 1/1 if (!rst_n) begin
Tests: T1 T2 T3
1260 1/1 usb_ref_val_q <= 1'b0;
Tests: T1 T2 T3
1261 end else begin
1262 1/1 usb_ref_val_q <= usb_ref_val_d;
Tests: T1 T2 T3
1263 end
1264 end
1265
1266 1/1 assign usb_ref_val_o = usb_ref_val_q;
Tests: T1 T2 T3
1267
1268 /////////////////////////////////////////
1269 // USB aon detector signaling //
1270 /////////////////////////////////////////
1271 1/1 assign usb_aon_suspend_req_o = reg2hw.wake_control.suspend_req.qe &
Tests: T1 T2 T3
1272 reg2hw.wake_control.suspend_req.q;
1273 1/1 assign usb_aon_wake_ack_o = reg2hw.wake_control.wake_ack.qe &
Tests: T1 T2 T3
1274 reg2hw.wake_control.wake_ack.q;
1275
1276 /////////////////////////////////////////
1277 // capture async event and debug info //
1278 /////////////////////////////////////////
1279
1280 assign hw2reg.wake_events.module_active.de = 1'b1;
1281 1/1 assign hw2reg.wake_events.module_active.d = usb_aon_wake_detect_active_i;
Tests: T7 T8 T9
1282 assign hw2reg.wake_events.bus_not_idle.de = 1'b1;
1283 1/1 assign hw2reg.wake_events.bus_not_idle.d = usb_aon_bus_not_idle_i;
Tests: T7 T9 T10
1284 assign hw2reg.wake_events.disconnected.de = 1'b1;
1285 1/1 assign hw2reg.wake_events.disconnected.d = usb_aon_sense_lost_i;
Tests: T8 T11 T13
1286 assign hw2reg.wake_events.bus_reset.de = 1'b1;
1287 1/1 assign hw2reg.wake_events.bus_reset.d = usb_aon_bus_reset_i;
Tests: T7 T10 T14
1288
1289 /////////////////////////////////////
1290 // Diagnostic/performance counters //
1291 /////////////////////////////////////
1292
1293 // SW write strobes for the event enables of the counters.
1294 logic ctr_out_ev_qe;
1295 logic ctr_in_ev_qe;
1296 logic ctr_errors_ev_qe;
1297 0/1 ==> assign ctr_out_ev_qe = &{reg2hw.count_out.ign_avsetup.qe,
1298 reg2hw.count_out.drop_avout.qe,
1299 reg2hw.count_out.drop_rx.qe,
1300 reg2hw.count_out.datatog_out.qe};
1301 0/1 ==> assign ctr_in_ev_qe = &{reg2hw.count_in.timeout.qe,
1302 reg2hw.count_in.nak.qe,
1303 reg2hw.count_in.nodata.qe};
1304 0/1 ==> assign ctr_errors_ev_qe = &{reg2hw.count_errors.crc5.qe,
Cond Coverage for Module :
usbdev
| Total | Covered | Percent |
|---|
| Conditions | 134 | 117 | 87.31 |
| Logical | 134 | 117 | 87.31 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 167
EXPRESSION (event_rx_crc5_err | event_rx_crc16_err)
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T37,T39 |
| 1 | 0 | Covered | T19,T110,T73 |
LINE 220
EXPRESSION (ns_cnt == 6'd47)
--------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 257
EXPRESSION (reg2hw.fifo_ctrl.avsetup_rst.qe & reg2hw.fifo_ctrl.avsetup_rst.q)
---------------1--------------- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T42,T43,T37 |
| 1 | 0 | Covered | T32,T38,T108 |
| 1 | 1 | Covered | T42,T43,T37 |
LINE 258
EXPRESSION (reg2hw.fifo_ctrl.avout_rst.qe & reg2hw.fifo_ctrl.avout_rst.q)
--------------1-------------- --------------2-------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T42,T43,T32 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T42,T43,T32 |
LINE 259
EXPRESSION (reg2hw.fifo_ctrl.rx_rst.qe & reg2hw.fifo_ctrl.rx_rst.q)
-------------1------------ ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T42,T43,T37 |
| 1 | 0 | Covered | T32,T38,T108 |
| 1 | 1 | Covered | T42,T43,T37 |
LINE 263
EXPRESSION (connect_en & ((~avsetup_rvalid)))
-----1---- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T3,T28 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 264
EXPRESSION (connect_en & ((~avout_rvalid)))
-----1---- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T29,T41 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 266
EXPRESSION ((reg2hw.avsetupbuffer.qe & ((~avsetup_fifo_wready))) | (reg2hw.avoutbuffer.qe & ((~avout_fifo_wready))))
--------------------------1------------------------- ------------------------2-----------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T62,T87 |
| 1 | 0 | Covered | T1,T63,T86 |
LINE 266
SUB-EXPRESSION (reg2hw.avsetupbuffer.qe & ((~avsetup_fifo_wready)))
-----------1----------- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T3,T28 |
| 1 | 1 | Covered | T1,T63,T86 |
LINE 266
SUB-EXPRESSION (reg2hw.avoutbuffer.qe & ((~avout_fifo_wready)))
----------1---------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T29,T41 |
| 1 | 1 | Covered | T62,T87 |
LINE 268
EXPRESSION (connect_en & ((~rx_fifo_rvalid)))
-----1---- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T28,T29 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 316
EXPRESSION (reg2hw.rxfifo.ep.re | reg2hw.rxfifo.setup.re | reg2hw.rxfifo.size.re | reg2hw.rxfifo.buffer.re)
---------1--------- -----------2---------- ----------3---------- -----------4-----------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 1 | Not Covered | |
| 0 | 0 | 1 | 0 | Not Covered | |
| 0 | 1 | 0 | 0 | Not Covered | |
| 1 | 0 | 0 | 0 | Not Covered | |
LINE 327
EXPRESSION (rx_wready & (rx_depth < 4'((RXFifoDepth - 1))))
----1---- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T30,T37,T38 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 442
EXPRESSION (in_xact_starting ? in_buf[in_xact_start_ep] : in_buf_q)
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T29,T31,T32 |
LINE 443
EXPRESSION (in_xact_starting ? in_size[in_xact_start_ep] : in_size_q)
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T29,T31,T32 |
LINE 447
EXPRESSION (reg2hw.out_data_toggle.status.qe & reg2hw.out_data_toggle.mask.qe)
----------------1--------------- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T29,T32,T37 |
LINE 456
EXPRESSION (reg2hw.in_data_toggle.status.qe & reg2hw.in_data_toggle.mask.qe)
---------------1--------------- --------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T29,T32,T109 |
LINE 465
EXPRESSION (in_ep_xact_end && in_endpoint_val)
-------1------ -------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
| 1 | 1 | Covered | T29,T32,T33 |
LINE 493
EXPRESSION (rx_wvalid && out_endpoint_val)
----1---- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
| 1 | 1 | Covered | T3,T28,T29 |
LINE 512
EXPRESSION (setup_received & out_endpoint_val)
-------1------ --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
| 1 | 1 | Covered | T3,T28,T30 |
LINE 516
EXPRESSION (in_ep_xact_end & in_endpoint_val)
-------1------ -------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
| 1 | 1 | Covered | T29,T32,T33 |
LINE 542
EXPRESSION (reg2hw.configin[i].rdy.q | reg2hw.configin[i].pend.q)
------------1----------- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T85,T171,T68 |
| 1 | 0 | Covered | T29,T43,T31 |
LINE 550
EXPRESSION (set_sending[i] | set_sentbit[i] | update_pend[i])
-------1------ -------2------ -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T1,T2,T3 |
| 0 | 1 | 0 | Covered | T29,T32,T33 |
| 1 | 0 | 0 | Covered | T29,T31,T32 |
LINE 551
EXPRESSION (((~set_sentbit[i])) & ((~update_pend[i])))
---------1--------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T29,T32,T33 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 560
EXPRESSION (cfg_pinflip ? 1'b0 : usb_pullup_en)
-----1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T49,T52,T206 |
LINE 561
EXPRESSION (((!cfg_pinflip)) ? 1'b0 : usb_pullup_en)
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T49,T52,T206 |
| 1 | Covered | T1,T2,T3 |
LINE 688
EXPRESSION (reg2hw.usbctrl.resume_link_active.qe & reg2hw.usbctrl.resume_link_active.q)
------------------1----------------- -----------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T93,T94,T95 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T93,T94,T95 |
LINE 800
EXPRESSION (usb_mem_b_req | sw_mem_a_req)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T3,T29,T43 |
| 1 | 0 | Covered | T3,T28,T29 |
LINE 801
EXPRESSION (usb_mem_b_req ? usb_mem_b_write : sw_mem_a_write)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T28,T29 |
LINE 802
EXPRESSION (usb_mem_b_req ? usb_mem_b_addr : sw_mem_a_addr)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T28,T29 |
LINE 803
EXPRESSION (usb_mem_b_req ? usb_mem_b_wdata : sw_mem_a_wdata)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T28,T29 |
LINE 826
EXPRESSION (usb_mem_b_req & ((!usb_mem_b_write)))
------1------ ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T28,T29 |
| 1 | 1 | Covered | T29,T31,T32 |
LINE 834
EXPRESSION (gen_no_stubbed_memory.mem_rvalid & ((!gen_no_stubbed_memory.mem_rsteering)))
----------------1--------------- --------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T29,T31,T32 |
| 1 | 1 | Covered | T3,T29,T32 |
LINE 839
EXPRESSION (gen_no_stubbed_memory.mem_b_read_q ? gen_no_stubbed_memory.mem_rdata : gen_no_stubbed_memory.mem_b_rdata_q)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T29,T31,T32 |
LINE 902
SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
---------1--------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T207,T208,T209 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T207,T208,T209 |
LINE 1211
EXPRESSION (use_diff_rcvr & ((~link_suspend)))
------1------ --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T7,T18,T8 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 1220
EXPRESSION (usb_rcvr_ok_counter_q == '0)
--------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1224
EXPRESSION (use_diff_rcvr & ((!usb_rx_enable_o)))
------1------ ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T7,T18,T8 |
LINE 1226
EXPRESSION (us_tick && (usb_rcvr_ok_counter_q > '0))
---1--- --------------2-------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T203,T204,T205 |
LINE 1248
EXPRESSION (usb_ref_disable ? 1'b0 : event_sof)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T61,T210,T211 |
LINE 1255
EXPRESSION (usb_ref_pulse_o ? 1'b1 : ((((!link_active)) || host_lost || usb_ref_disable) ? 1'b0 : usb_ref_val_q))
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T41,T61,T8 |
LINE 1255
SUB-EXPRESSION ((((!link_active)) || host_lost || usb_ref_disable) ? 1'b0 : usb_ref_val_q)
-------------------------1------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1255
SUB-EXPRESSION (((!link_active)) || host_lost || usb_ref_disable)
--------1------- ----2---- -------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T61,T210,T211 |
| 0 | 1 | 0 | Covered | T66,T67,T68 |
| 1 | 0 | 0 | Covered | T1,T2,T3 |
LINE 1271
EXPRESSION (reg2hw.wake_control.suspend_req.qe & reg2hw.wake_control.suspend_req.q)
-----------------1---------------- ----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T7,T8,T9 |
| 1 | 0 | Covered | T7,T8,T9 |
| 1 | 1 | Covered | T7,T8,T9 |
LINE 1273
EXPRESSION (reg2hw.wake_control.wake_ack.qe & reg2hw.wake_control.wake_ack.q)
---------------1--------------- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T7,T8,T9 |
| 1 | 0 | Covered | T7,T8,T9 |
| 1 | 1 | Covered | T7,T8,T9 |
LINE 1310
EXPRESSION (reg2hw.count_out.rst.qe & reg2hw.count_out.rst.q)
-----------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 1336
EXPRESSION (reg2hw.count_in.rst.qe & reg2hw.count_in.rst.q)
-----------1---------- ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 1359
EXPRESSION (reg2hw.count_nodata_in.rst.qe & reg2hw.count_nodata_in.rst.q)
--------------1-------------- --------------2-------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 1376
EXPRESSION (reg2hw.count_errors.rst.qe & reg2hw.count_errors.rst.q)
-------------1------------ ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
Toggle Coverage for Module :
usbdev
| Total | Covered | Percent |
| Totals |
74 |
68 |
91.89 |
| Total Bits |
440 |
416 |
94.55 |
| Total Bits 0->1 |
220 |
208 |
94.55 |
| Total Bits 1->0 |
220 |
208 |
94.55 |
| | | |
| Ports |
74 |
68 |
91.89 |
| Port Bits |
440 |
416 |
94.55 |
| Port Bits 0->1 |
220 |
208 |
94.55 |
| Port Bits 1->0 |
220 |
208 |
94.55 |
Port Details
| Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
| clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| rst_ni |
Yes |
Yes |
T212,T167,T213 |
Yes |
T1,T2,T3 |
INPUT |
| clk_aon_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| rst_aon_ni |
Yes |
Yes |
T212,T167,T213 |
Yes |
T1,T2,T3 |
INPUT |
| tl_i.d_ready |
Yes |
Yes |
T2,T30,T43 |
Yes |
T1,T2,T3 |
INPUT |
| tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T2,T3,T42 |
Yes |
T2,T3,T42 |
INPUT |
| tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
| tl_i.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| tl_i.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| tl_i.a_address[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| tl_i.a_source[7:0] |
Yes |
Yes |
T2,T3,T28 |
Yes |
T2,T3,T28 |
INPUT |
| tl_i.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
| tl_i.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| tl_i.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| tl_o.a_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| tl_o.d_error |
Yes |
Yes |
T214,T215,T216 |
Yes |
T214,T215,T216 |
OUTPUT |
| tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| tl_o.d_user.rsp_intg[5:0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| tl_o.d_user.rsp_intg[6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
| tl_o.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T3,T28,T40 |
OUTPUT |
| tl_o.d_sink |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
| tl_o.d_source[7:0] |
Yes |
Yes |
T3,T28,T40 |
Yes |
T1,T3,T28 |
OUTPUT |
| tl_o.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
| tl_o.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
| tl_o.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| alert_rx_i[0].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| alert_rx_i[0].ack_p |
Yes |
Yes |
T207,T212,T208 |
Yes |
T207,T212,T208 |
INPUT |
| alert_rx_i[0].ping_n |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
| alert_rx_i[0].ping_p |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
| alert_tx_o[0].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| alert_tx_o[0].alert_p |
Yes |
Yes |
T207,T212,T208 |
Yes |
T207,T212,T208 |
OUTPUT |
| cio_usb_dp_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| cio_usb_dn_i |
Yes |
Yes |
T2,T3,T28 |
Yes |
T2,T3,T28 |
INPUT |
| usb_rx_d_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| cio_usb_dp_o |
Yes |
Yes |
T3,T28,T29 |
Yes |
T3,T28,T29 |
OUTPUT |
| cio_usb_dp_en_o |
Yes |
Yes |
T3,T28,T29 |
Yes |
T3,T28,T29 |
OUTPUT |
| cio_usb_dn_o |
Yes |
Yes |
T3,T28,T29 |
Yes |
T3,T28,T29 |
OUTPUT |
| cio_usb_dn_en_o |
Yes |
Yes |
T3,T28,T29 |
Yes |
T3,T28,T29 |
OUTPUT |
| usb_tx_se0_o |
Yes |
Yes |
T3,T28,T29 |
Yes |
T3,T28,T29 |
OUTPUT |
| usb_tx_d_o |
Yes |
Yes |
T3,T28,T29 |
Yes |
T3,T28,T29 |
OUTPUT |
| cio_sense_i |
Yes |
Yes |
T41,T18,T8 |
Yes |
T1,T2,T3 |
INPUT |
| usb_dp_pullup_o |
Yes |
Yes |
T41,T7,T18 |
Yes |
T1,T2,T3 |
OUTPUT |
| usb_dn_pullup_o |
Yes |
Yes |
T14,T97,T217 |
Yes |
T49,T52,T206 |
OUTPUT |
| usb_rx_enable_o |
Yes |
Yes |
T7,T18,T8 |
Yes |
T1,T2,T3 |
OUTPUT |
| usb_tx_use_d_se0_o |
Yes |
Yes |
T167,T218,T219 |
Yes |
T162,T110,T220 |
OUTPUT |
| usb_aon_suspend_req_o |
Yes |
Yes |
T7,T8,T9 |
Yes |
T7,T8,T9 |
OUTPUT |
| usb_aon_wake_ack_o |
Yes |
Yes |
T7,T8,T9 |
Yes |
T7,T8,T9 |
OUTPUT |
| usb_aon_bus_reset_i |
Yes |
Yes |
T7,T10,T14 |
Yes |
T7,T10,T14 |
INPUT |
| usb_aon_sense_lost_i |
Yes |
Yes |
T8,T11,T13 |
Yes |
T8,T11,T13 |
INPUT |
| usb_aon_bus_not_idle_i |
Yes |
Yes |
T7,T9,T10 |
Yes |
T7,T9,T10 |
INPUT |
| usb_aon_wake_detect_active_i |
Yes |
Yes |
T7,T8,T9 |
Yes |
T7,T8,T9 |
INPUT |
| usb_ref_val_o |
Yes |
Yes |
T41,T61,T8 |
Yes |
T41,T61,T8 |
OUTPUT |
| usb_ref_pulse_o |
Yes |
Yes |
T41,T61,T8 |
Yes |
T41,T61,T8 |
OUTPUT |
| ram_cfg_i.rf_cfg.cfg[3:0] |
No |
No |
|
No |
|
INPUT |
| ram_cfg_i.rf_cfg.cfg_en |
No |
No |
|
No |
|
INPUT |
| ram_cfg_i.rf_cfg.test |
No |
No |
|
No |
|
INPUT |
| ram_cfg_i.ram_cfg.cfg[3:0] |
No |
No |
|
No |
|
INPUT |
| ram_cfg_i.ram_cfg.cfg_en |
No |
No |
|
No |
|
INPUT |
| ram_cfg_i.ram_cfg.test |
No |
No |
|
No |
|
INPUT |
| intr_pkt_received_o |
Yes |
Yes |
T49,T51,T52 |
Yes |
T49,T51,T52 |
OUTPUT |
| intr_pkt_sent_o |
Yes |
Yes |
T33,T35,T17 |
Yes |
T33,T35,T17 |
OUTPUT |
| intr_powered_o |
Yes |
Yes |
T221,T222,T223 |
Yes |
T221,T222,T223 |
OUTPUT |
| intr_disconnected_o |
Yes |
Yes |
T41,T64,T65 |
Yes |
T41,T64,T65 |
OUTPUT |
| intr_host_lost_o |
Yes |
Yes |
T66,T221,T222 |
Yes |
T66,T221,T222 |
OUTPUT |
| intr_link_reset_o |
Yes |
Yes |
T50,T221,T223 |
Yes |
T50,T221,T223 |
OUTPUT |
| intr_link_suspend_o |
Yes |
Yes |
T221,T223,T224 |
Yes |
T221,T223,T224 |
OUTPUT |
| intr_link_resume_o |
Yes |
Yes |
T20,T69,T70 |
Yes |
T20,T69,T70 |
OUTPUT |
| intr_av_out_empty_o |
Yes |
Yes |
T53,T221,T223 |
Yes |
T53,T221,T223 |
OUTPUT |
| intr_rx_full_o |
Yes |
Yes |
T21,T56,T57 |
Yes |
T21,T56,T57 |
OUTPUT |
| intr_av_overflow_o |
Yes |
Yes |
T1,T62,T63 |
Yes |
T1,T62,T63 |
OUTPUT |
| intr_link_in_err_o |
Yes |
Yes |
T221,T223,T224 |
Yes |
T221,T223,T224 |
OUTPUT |
| intr_link_out_err_o |
Yes |
Yes |
T37,T39,T71 |
Yes |
T37,T39,T71 |
OUTPUT |
| intr_rx_crc_err_o |
Yes |
Yes |
T19,T73,T74 |
Yes |
T19,T73,T74 |
OUTPUT |
| intr_rx_pid_err_o |
Yes |
Yes |
T23,T75,T77 |
Yes |
T23,T75,T77 |
OUTPUT |
| intr_rx_bitstuff_err_o |
Yes |
Yes |
T2,T80,T81 |
Yes |
T2,T80,T81 |
OUTPUT |
| intr_frame_o |
Yes |
Yes |
T221,T223,T224 |
Yes |
T221,T223,T224 |
OUTPUT |
| intr_av_setup_empty_o |
Yes |
Yes |
T28,T24,T59 |
Yes |
T28,T24,T59 |
OUTPUT |
*Tests covering at least one bit in the range
Branch Coverage for Module :
usbdev
| Line No. | Total | Covered | Percent |
| Branches |
|
48 |
48 |
100.00 |
| TERNARY |
442 |
2 |
2 |
100.00 |
| TERNARY |
443 |
2 |
2 |
100.00 |
| TERNARY |
560 |
2 |
2 |
100.00 |
| TERNARY |
561 |
2 |
2 |
100.00 |
| TERNARY |
1248 |
2 |
2 |
100.00 |
| TERNARY |
1255 |
3 |
3 |
100.00 |
| TERNARY |
801 |
2 |
2 |
100.00 |
| TERNARY |
802 |
2 |
2 |
100.00 |
| TERNARY |
803 |
2 |
2 |
100.00 |
| TERNARY |
839 |
2 |
2 |
100.00 |
| IF |
222 |
3 |
3 |
100.00 |
| IF |
434 |
2 |
2 |
100.00 |
| IF |
465 |
2 |
2 |
100.00 |
| IF |
493 |
2 |
2 |
100.00 |
| IF |
508 |
4 |
4 |
100.00 |
| IF |
526 |
2 |
2 |
100.00 |
| IF |
718 |
2 |
2 |
100.00 |
| IF |
1224 |
3 |
3 |
100.00 |
| IF |
1232 |
2 |
2 |
100.00 |
| IF |
1259 |
2 |
2 |
100.00 |
| IF |
820 |
3 |
3 |
100.00 |
442 assign in_buf_d = in_xact_starting ? in_buf[in_xact_start_ep] : in_buf_q;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T29,T31,T32 |
| 0 |
Covered |
T1,T2,T3 |
443 assign in_size_d = in_xact_starting ? in_size[in_xact_start_ep] : in_size_q;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T29,T31,T32 |
| 0 |
Covered |
T1,T2,T3 |
560 assign usb_dp_pullup_en = cfg_pinflip ? 1'b0 : usb_pullup_en;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T49,T52,T206 |
| 0 |
Covered |
T1,T2,T3 |
561 assign usb_dn_pullup_en = !cfg_pinflip ? 1'b0 : usb_pullup_en;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T49,T52,T206 |
1248 assign usb_ref_pulse_o = usb_ref_disable ? 1'b0 : event_sof;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T61,T210,T211 |
| 0 |
Covered |
T1,T2,T3 |
1255 assign usb_ref_val_d = usb_ref_pulse_o ? 1'b1 :
-1-
==>
1256 (!link_active || host_lost || usb_ref_disable) ? 1'b0 : usb_ref_val_q;
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T41,T61,T8 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
801 assign mem_write = usb_mem_b_req ? usb_mem_b_write : sw_mem_a_write;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T3,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
802 assign mem_addr = usb_mem_b_req ? usb_mem_b_addr : sw_mem_a_addr;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T3,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
803 assign mem_wdata = usb_mem_b_req ? usb_mem_b_wdata : sw_mem_a_wdata;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T3,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
839 assign usb_mem_b_rdata = mem_b_read_q ? mem_rdata : mem_b_rdata_q;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T29,T31,T32 |
| 0 |
Covered |
T1,T2,T3 |
222 if (!rst_n) begin
-1-
223 ns_cnt <= '0;
==>
224 end else begin
225 if (us_tick) begin
-2-
226 ns_cnt <= '0;
==>
227 end else begin
228 ns_cnt <= ns_cnt + 1'b1;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
434 if (!rst_n) begin
-1-
435 in_buf_q <= '0;
==>
436 in_size_q <= '0;
437 end else begin
438 in_buf_q <= in_buf_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
465 if (in_ep_xact_end && in_endpoint_val) begin
-1-
466 set_sentbit[in_endpoint] = 1'b1;
==>
467 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T29,T32,T33 |
| 0 |
Covered |
T1,T2,T3 |
493 if (rx_wvalid && out_endpoint_val) begin
-1-
494 clear_rxenable_out[out_endpoint] = ep_set_nak_on_out[out_endpoint];
==>
495 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T3,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
508 if (event_link_reset) begin
-1-
509 clear_rdybit = {NEndpoints{1'b1}};
==>
510 update_pend = {NEndpoints{1'b1}};
511 end else begin
512 if (setup_received & out_endpoint_val) begin
-2-
513 // Clear pending when a SETUP is received
514 clear_rdybit[out_endpoint] = 1'b1;
==>
515 update_pend[out_endpoint] = 1'b1;
516 end else if (in_ep_xact_end & in_endpoint_val) begin
-3-
517 // Clear rdy and sending when an IN transmission was successful
518 clear_rdybit[in_endpoint] = 1'b1;
==>
519 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T3,T28,T30 |
| 0 |
0 |
1 |
Covered |
T29,T32,T33 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
526 if (in_xact_starting) set_sending[in_xact_start_ep] = 1'b1;
-1-
==>
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T29,T31,T32 |
| 0 |
Covered |
T1,T2,T3 |
718 if (setup_received && out_endpoint_val && out_endpoint == 4'(unsigned'(i))) begin
-1-
719 hw2reg.out_stall[i].de = 1'b1;
==>
720 hw2reg.in_stall[i].de = 1'b1;
721 end else begin
722 hw2reg.out_stall[i].de = 1'b0;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T3,T28,T30 |
| 0 |
Covered |
T1,T2,T3 |
1224 if (use_diff_rcvr & !usb_rx_enable_o) begin
-1-
1225 usb_rcvr_ok_counter_d = RcvrWakeTimeWidth'(RcvrWakeTimeUs + 1);
==>
1226 end else if (us_tick && (usb_rcvr_ok_counter_q > '0)) begin
-2-
1227 usb_rcvr_ok_counter_d = usb_rcvr_ok_counter_q - 1;
==>
1228 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T7,T18,T8 |
| 0 |
1 |
Covered |
T203,T204,T205 |
| 0 |
0 |
Covered |
T1,T2,T3 |
1232 if (!rst_n) begin
-1-
1233 usb_rcvr_ok_counter_q <= RcvrWakeTimeWidth'(RcvrWakeTimeUs + 1);
==>
1234 end else begin
1235 usb_rcvr_ok_counter_q <= usb_rcvr_ok_counter_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
1259 if (!rst_n) begin
-1-
1260 usb_ref_val_q <= 1'b0;
==>
1261 end else begin
1262 usb_ref_val_q <= usb_ref_val_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
820 if (!rst_ni) begin
-1-
821 mem_rsteering <= 1'b0;
==>
822 mem_b_read_q <= 1'b0;
823 mem_b_rdata_q <= {SramDw{1'b0}};
824 end else begin
825 mem_rsteering <= usb_mem_b_req;
826 mem_b_read_q <= usb_mem_b_req & !usb_mem_b_write;
827 // Capture the `usb` read data.
828 if (mem_b_read_q)
-2-
829 mem_b_rdata_q <= mem_rdata;
==>
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T29,T31,T32 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
usbdev
Assertion Details
AlertsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
CIODnEnKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
CIODnKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
CIODpEnKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
CIODpKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
FpvSecCmRegWeOnehotCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
70 |
0 |
0 |
| T5 |
78155 |
0 |
0 |
0 |
| T6 |
93188 |
0 |
0 |
0 |
| T62 |
6774 |
0 |
0 |
0 |
| T64 |
6563 |
0 |
0 |
0 |
| T80 |
10645 |
0 |
0 |
0 |
| T109 |
29672 |
0 |
0 |
0 |
| T110 |
23113 |
0 |
0 |
0 |
| T212 |
23969 |
20 |
0 |
0 |
| T213 |
0 |
10 |
0 |
0 |
| T225 |
0 |
10 |
0 |
0 |
| T226 |
0 |
20 |
0 |
0 |
| T227 |
0 |
10 |
0 |
0 |
| T228 |
7672 |
0 |
0 |
0 |
| T229 |
1531 |
0 |
0 |
0 |
TlOAReadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
TlODValidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBAonSuspendReqKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBAonWakeAckKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBDnPUKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBDpPUKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBIntrAvOutEmptyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBIntrAvOverKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBIntrAvSetupEmptyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBIntrDisConKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBIntrFrameKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBIntrHostLostKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBIntrLinkInErrKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBIntrLinkOutErrKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBIntrLinkResKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBIntrLinkRstKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBIntrLinkSusKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBIntrPktRcvdKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBIntrPktSentKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBIntrPwrdKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBIntrRxBitstuffErrKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBIntrRxCrCErrKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBIntrRxFullKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBIntrRxPidErrKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBRefPulseKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBRefValKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBRxEnableKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBTxDKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBTxSe0Known_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
Line Coverage for Instance : tb.dut
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 162 | 158 | 97.53 |
| CONT_ASSIGN | 123 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 220 | 1 | 1 | 100.00 |
| ALWAYS | 222 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 257 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 258 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 259 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 263 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 264 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 266 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 268 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 316 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 321 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 324 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 327 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 352 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 353 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 354 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 355 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 356 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 360 | 1 | 0 | 0.00 |
| ALWAYS | 383 | 0 | 0 | |
| ALWAYS | 383 | 3 | 3 | 100.00 |
| ALWAYS | 391 | 0 | 0 | |
| ALWAYS | 391 | 4 | 4 | 100.00 |
| ALWAYS | 400 | 0 | 0 | |
| ALWAYS | 400 | 3 | 3 | 100.00 |
| ALWAYS | 407 | 0 | 0 | |
| ALWAYS | 407 | 3 | 3 | 100.00 |
| ALWAYS | 414 | 0 | 0 | |
| ALWAYS | 414 | 3 | 3 | 100.00 |
| ALWAYS | 421 | 0 | 0 | |
| ALWAYS | 421 | 2 | 2 | 100.00 |
| ALWAYS | 434 | 5 | 5 | 100.00 |
| CONT_ASSIGN | 442 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 443 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 447 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 448 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 449 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 451 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 456 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 457 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 458 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 460 | 1 | 1 | 100.00 |
| ALWAYS | 464 | 3 | 3 | 100.00 |
| ALWAYS | 471 | 0 | 0 | |
| ALWAYS | 471 | 3 | 3 | 100.00 |
| ALWAYS | 480 | 3 | 3 | 100.00 |
| ALWAYS | 492 | 3 | 3 | 100.00 |
| ALWAYS | 499 | 0 | 0 | |
| ALWAYS | 499 | 3 | 3 | 100.00 |
| ALWAYS | 506 | 10 | 10 | 100.00 |
| ALWAYS | 525 | 3 | 3 | 100.00 |
| ALWAYS | 532 | 0 | 0 | |
| ALWAYS | 532 | 3 | 3 | 100.00 |
| ALWAYS | 540 | 0 | 0 | |
| ALWAYS | 540 | 3 | 3 | 100.00 |
| ALWAYS | 549 | 0 | 0 | |
| ALWAYS | 549 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 559 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 560 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 561 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 684 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 685 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 687 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 688 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 706 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 709 | 1 | 1 | 100.00 |
| ALWAYS | 715 | 0 | 0 | |
| ALWAYS | 715 | 8 | 8 | 100.00 |
| CONT_ASSIGN | 800 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 801 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 802 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 803 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 811 | 1 | 1 | 100.00 |
| ALWAYS | 820 | 8 | 8 | 100.00 |
| CONT_ASSIGN | 834 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 835 | 0 | 0 | |
| CONT_ASSIGN | 838 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 839 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 897 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 898 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 902 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1165 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1166 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1168 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1208 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1211 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1220 | 1 | 1 | 100.00 |
| ALWAYS | 1223 | 5 | 5 | 100.00 |
| ALWAYS | 1232 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 1245 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1248 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1255 | 1 | 1 | 100.00 |
| ALWAYS | 1259 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 1266 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1271 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1273 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1281 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1283 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1285 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1287 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1297 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 1301 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 1304 | 1 | 0 | 0.00 |
122 end else begin : gen_no_stubbed_reset
123 1/1 assign rst_n = rst_ni;
Tests: T1 T2 T3
124 end
125
126 tlul_pkg::tl_h2d_t tl_sram_h2d;
127 tlul_pkg::tl_d2h_t tl_sram_d2h;
128
129 // Software access to the Packet Buffer RAM
130 logic sw_mem_a_req;
131 logic sw_mem_a_gnt;
132 logic sw_mem_a_write;
133 logic [SramAw-1:0] sw_mem_a_addr;
134 logic [SramDw-1:0] sw_mem_a_wdata;
135 logic sw_mem_a_rvalid;
136 logic [SramDw-1:0] sw_mem_a_rdata;
137 logic [1:0] sw_mem_a_rerror;
138
139 // usbdev hardware access to the Packet Buffer RAM
140 logic usb_mem_b_req;
141 logic usb_mem_b_write;
142 logic [SramAw-1:0] usb_mem_b_addr;
143 logic [SramDw-1:0] usb_mem_b_wdata;
144 logic [SramDw-1:0] usb_mem_b_rdata;
145
146 logic clr_devaddr;
147 logic event_av_setup_empty, event_av_out_empty, event_av_overflow, event_rx_full;
148 logic link_reset, link_suspend;
149 logic host_lost, link_disconnect, link_powered;
150 logic event_link_reset, event_link_suspend, event_link_resume;
151 logic event_host_lost, event_disconnect, event_powered;
152 logic event_rx_crc5_err, event_rx_crc16_err;
153 logic event_rx_crc_err, event_rx_pid_err;
154 logic event_rx_bitstuff_err;
155 logic event_in_err;
156 logic event_out_err;
157 logic event_frame, event_sof;
158 logic link_active;
159
160 // Diagnostic visibility of OUT-side exceptional events
161 logic event_ign_avsetup, event_drop_avout, event_drop_rx, event_datatog_out;
162 // Diagnostic visibility of IN-side exceptional events
163 logic event_timeout_in, event_nak_in, event_nodata_in;
164
165 // Interrupt to software reports both types of CRC error; they are separated only for the
166 // purpose of diagnostic event counting.
167 1/1 assign event_rx_crc_err = event_rx_crc5_err | event_rx_crc16_err;
Tests: T1 T2 T3
168
169 logic [10:0] frame;
170 logic [2:0] link_state;
171 logic connect_en;
172 logic resume_link_active;
173
174 // Current state of OUT data toggles
175 logic [NEndpoints-1:0] out_data_toggle;
176 // Write strobe from register interface
177 logic out_datatog_we;
178 // Write data from register interface
179 logic [NEndpoints-1:0] out_datatog_status;
180 logic [NEndpoints-1:0] out_datatog_mask;
181
182 // Current state of IN data toggles
183 logic [NEndpoints-1:0] in_data_toggle;
184 // Write strobe from register interface
185 logic in_datatog_we;
186 // Write data from register interface
187 logic [NEndpoints-1:0] in_datatog_status;
188 logic [NEndpoints-1:0] in_datatog_mask;
189
190 /////////////////////////////////
191 // USB RX after CDC & muxing //
192 /////////////////////////////////
193 logic usb_rx_d;
194 logic usb_rx_dp;
195 logic usb_rx_dn;
196 /////////////////////////////////
197 // USB TX after CDC & muxing //
198 /////////////////////////////////
199 logic usb_tx_d;
200 logic usb_tx_se0;
201 logic usb_tx_dp;
202 logic usb_tx_dn;
203 logic usb_tx_oe;
204 /////////////////////////////////
205 // USB contol pins after CDC //
206 /////////////////////////////////
207 logic usb_pwr_sense;
208 logic usb_pullup_en;
209 logic usb_dp_pullup_en;
210 logic usb_dn_pullup_en;
211
212 //////////////////////////////////
213 // Microsecond timing reference //
214 //////////////////////////////////
215 // us_tick ticks for one cycle every us, and it is based off a free-running
216 // counter.
217 logic [5:0] ns_cnt;
218 logic us_tick;
219
220 1/1 assign us_tick = (ns_cnt == 6'd47);
Tests: T1 T2 T3
221 always_ff @(posedge clk_i or negedge rst_n) begin
222 1/1 if (!rst_n) begin
Tests: T1 T2 T3
223 1/1 ns_cnt <= '0;
Tests: T1 T2 T3
224 end else begin
225 1/1 if (us_tick) begin
Tests: T1 T2 T3
226 1/1 ns_cnt <= '0;
Tests: T1 T2 T3
227 end else begin
228 1/1 ns_cnt <= ns_cnt + 1'b1;
Tests: T1 T2 T3
229 end
230 end
231 end
232
233 /////////////////////////////
234 // Receive interface fifos //
235 /////////////////////////////
236
237 logic avsetup_fifo_rst;
238 logic avsetup_fifo_wready;
239 logic avout_fifo_rst;
240 logic avout_fifo_wready;
241 logic event_pkt_received;
242 logic avsetup_rvalid, avsetup_rready;
243 logic avout_rvalid, avout_rready;
244 logic rx_fifo_rst;
245 logic rx_wvalid, rx_wready;
246 logic rx_wready_setup, rx_wready_out;
247 logic rx_fifo_rvalid;
248 logic rx_fifo_re;
249
250 logic [AVFifoWidth - 1:0] avsetup_rdata;
251 logic [AVFifoWidth - 1:0] avout_rdata;
252 logic [RXFifoWidth - 1:0] rx_wdata, rx_rdata;
253
254 logic [NEndpoints-1:0] clear_rxenable_out;
255
256 // Software reset signals
257 1/1 assign avsetup_fifo_rst = reg2hw.fifo_ctrl.avsetup_rst.qe & reg2hw.fifo_ctrl.avsetup_rst.q;
Tests: T1 T2 T3
258 1/1 assign avout_fifo_rst = reg2hw.fifo_ctrl.avout_rst.qe & reg2hw.fifo_ctrl.avout_rst.q;
Tests: T1 T2 T3
259 1/1 assign rx_fifo_rst = reg2hw.fifo_ctrl.rx_rst.qe & reg2hw.fifo_ctrl.rx_rst.q;
Tests: T1 T2 T3
260
261 // Separate 'FIFO empty' interrupts for the OUT and SETUP FIFOs because each interrupt cannot be
262 // cleared without writing a buffer into the FIFO
263 1/1 assign event_av_setup_empty = connect_en & ~avsetup_rvalid;
Tests: T1 T2 T3
264 1/1 assign event_av_out_empty = connect_en & ~avout_rvalid;
Tests: T1 T2 T3
265 // A single 'overflow' interrupt suffices since this indicates a programming error
266 1/1 assign event_av_overflow = (reg2hw.avsetupbuffer.qe & (~avsetup_fifo_wready))
Tests: T1 T2 T3
267 | (reg2hw.avoutbuffer.qe & (~avout_fifo_wready));
268 1/1 assign hw2reg.usbstat.rx_empty.d = connect_en & ~rx_fifo_rvalid;
Tests: T1 T2 T3
269
270 // Available SETUP Buffer FIFO
271 prim_fifo_sync #(
272 .Width(AVFifoWidth),
273 .Pass(1'b0),
274 .Depth(AVSetupFifoDepth),
275 .OutputZeroIfEmpty(1'b0)
276 ) usbdev_avsetupfifo (
277 .clk_i,
278 .rst_ni (rst_n),
279 .clr_i (avsetup_fifo_rst),
280
281 .wvalid_i (reg2hw.avsetupbuffer.qe),
282 .wready_o (avsetup_fifo_wready),
283 .wdata_i (reg2hw.avsetupbuffer.q),
284
285 .rvalid_o (avsetup_rvalid),
286 .rready_i (avsetup_rready),
287 .rdata_o (avsetup_rdata),
288 .full_o (hw2reg.usbstat.av_setup_full.d),
289 .depth_o (hw2reg.usbstat.av_setup_depth.d),
290 .err_o ()
291 );
292
293 // Available OUT Buffer FIFO
294 prim_fifo_sync #(
295 .Width(AVFifoWidth),
296 .Pass(1'b0),
297 .Depth(AVOutFifoDepth),
298 .OutputZeroIfEmpty(1'b0)
299 ) usbdev_avoutfifo (
300 .clk_i,
301 .rst_ni (rst_n),
302 .clr_i (avout_fifo_rst),
303
304 .wvalid_i (reg2hw.avoutbuffer.qe),
305 .wready_o (avout_fifo_wready),
306 .wdata_i (reg2hw.avoutbuffer.q),
307
308 .rvalid_o (avout_rvalid),
309 .rready_i (avout_rready),
310 .rdata_o (avout_rdata),
311 .full_o (hw2reg.usbstat.av_out_full.d),
312 .depth_o (hw2reg.usbstat.av_out_depth.d),
313 .err_o ()
314 );
315
316 1/1 assign rx_fifo_re = reg2hw.rxfifo.ep.re | reg2hw.rxfifo.setup.re |
Tests: T3 T29 T32
317 reg2hw.rxfifo.size.re | reg2hw.rxfifo.buffer.re;
318
319 // The number of used entries in the Received Buffer FIFO is presented to the software
320 logic [RXFifoDepthW-1:0] rx_depth;
321 1/1 assign hw2reg.usbstat.rx_depth.d = rx_depth;
Tests: T1 T2 T3
322
323 // We can always accept a SETUP packet if the Received Buffer FIFO is not full...
324 1/1 assign rx_wready_setup = rx_wready;
Tests: T1 T2 T3
325 // ... but regular OUT packets are not permitted to use the final entry; still qualified
326 // with 'rx_wready' for when reset is asserted.
327 1/1 assign rx_wready_out = rx_wready & (rx_depth < RXFifoDepthW'(RXFifoDepth - 1));
Tests: T1 T2 T3
328
329 // Received Buffer FIFO
330 prim_fifo_sync #(
331 .Width(RXFifoWidth),
332 .Pass(1'b0),
333 .Depth(RXFifoDepth),
334 .OutputZeroIfEmpty(1'b1)
335 ) usbdev_rxfifo (
336 .clk_i,
337 .rst_ni (rst_n),
338 .clr_i (rx_fifo_rst),
339
340 .wvalid_i (rx_wvalid),
341 .wready_o (rx_wready),
342 .wdata_i (rx_wdata),
343
344 .rvalid_o (rx_fifo_rvalid),
345 .rready_i (rx_fifo_re),
346 .rdata_o (rx_rdata),
347 .full_o (event_rx_full),
348 .depth_o (rx_depth),
349 .err_o ()
350 );
351
352 1/1 assign hw2reg.rxfifo.ep.d = rx_rdata[16:13];
Tests: T1 T2 T3
353 1/1 assign hw2reg.rxfifo.setup.d = rx_rdata[12];
Tests: T1 T2 T3
354 1/1 assign hw2reg.rxfifo.size.d = rx_rdata[11:5];
Tests: T1 T2 T3
355 1/1 assign hw2reg.rxfifo.buffer.d = rx_rdata[4:0];
Tests: T1 T2 T3
356 1/1 assign event_pkt_received = rx_fifo_rvalid;
Tests: T1 T2 T3
357
358 // The rxfifo register is hrw, but we just need the read enables.
359 logic [16:0] unused_rxfifo_q;
360 0/1 ==> assign unused_rxfifo_q = {reg2hw.rxfifo.ep.q, reg2hw.rxfifo.setup.q,
361 reg2hw.rxfifo.size.q, reg2hw.rxfifo.buffer.q};
362
363 ////////////////////////////////////
364 // IN (Transmit) interface config //
365 ////////////////////////////////////
366 logic [NBufWidth-1:0] in_buf [NEndpoints];
367 logic [SizeWidth:0] in_size [NEndpoints];
368 logic [3:0] in_endpoint;
369 logic in_endpoint_val;
370 logic [NEndpoints-1:0] in_rdy;
371 logic [NEndpoints-1:0] clear_rdybit, set_sentbit, update_pend, set_sending;
372 logic setup_received, in_ep_xact_end;
373 logic [NEndpoints-1:0] ep_out_iso, ep_in_iso;
374 logic [NEndpoints-1:0] enable_out, enable_setup, in_ep_stall, out_ep_stall;
375 logic [NEndpoints-1:0] ep_set_nak_on_out;
376 logic [NEndpoints-1:0] ep_in_enable, ep_out_enable;
377 logic [3:0] out_endpoint;
378 logic out_endpoint_val;
379 logic use_diff_rcvr, usb_diff_rx_ok;
380
381 // Endpoint enables
382 always_comb begin : proc_map_ep_enable
383 1/1 for (int i = 0; i < NEndpoints; i++) begin
Tests: T1 T2 T3
384 1/1 ep_in_enable[i] = reg2hw.ep_in_enable[i].q;
Tests: T1 T2 T3
385 1/1 ep_out_enable[i] = reg2hw.ep_out_enable[i].q;
Tests: T1 T2 T3
386 end
387 end
388
389 // RX enables
390 always_comb begin : proc_map_rxenable
391 1/1 for (int i = 0; i < NEndpoints; i++) begin
Tests: T1 T2 T3
392 1/1 enable_setup[i] = reg2hw.rxenable_setup[i].q;
Tests: T1 T2 T3
393 1/1 enable_out[i] = reg2hw.rxenable_out[i].q;
Tests: T1 T2 T3
394 1/1 ep_set_nak_on_out[i] = reg2hw.set_nak_out[i].q;
Tests: T1 T2 T3
395 end
396 end
397
398 // STALL for both directions
399 always_comb begin : proc_map_stall
400 1/1 for (int i = 0; i < NEndpoints; i++) begin
Tests: T1 T2 T3
401 1/1 in_ep_stall[i] = reg2hw.in_stall[i];
Tests: T1 T2 T3
402 1/1 out_ep_stall[i] = reg2hw.out_stall[i];
Tests: T1 T2 T3
403 end
404 end
405
406 always_comb begin : proc_map_iso
407 1/1 for (int i = 0; i < NEndpoints; i++) begin
Tests: T1 T2 T3
408 1/1 ep_out_iso[i] = reg2hw.out_iso[i].q;
Tests: T1 T2 T3
409 1/1 ep_in_iso[i] = reg2hw.in_iso[i].q;
Tests: T1 T2 T3
410 end
411 end
412
413 always_comb begin : proc_map_buf_size
414 1/1 for (int i = 0; i < NEndpoints; i++) begin
Tests: T1 T2 T3
415 1/1 in_buf[i] = reg2hw.configin[i].buffer.q;
Tests: T1 T2 T3
416 1/1 in_size[i] = reg2hw.configin[i].size.q;
Tests: T1 T2 T3
417 end
418 end
419
420 always_comb begin : proc_map_rdy_reg2hw
421 1/1 for (int i = 0; i < NEndpoints; i++) begin
Tests: T1 T2 T3
422 1/1 in_rdy[i] = reg2hw.configin[i].rdy.q;
Tests: T1 T2 T3
423 end
424 end
425
426 // Captured properties of current IN buffer, maintained throughout packet collection as
427 // protection against change during packet retraction by FW.
428 logic [NBufWidth-1:0] in_buf_q, in_buf_d;
429 logic [SizeWidth:0] in_size_q, in_size_d;
430 logic in_xact_starting;
431 logic [3:0] in_xact_start_ep;
432
433 always_ff @(posedge clk_i or negedge rst_n) begin
434 1/1 if (!rst_n) begin
Tests: T1 T2 T3
435 1/1 in_buf_q <= '0;
Tests: T1 T2 T3
436 1/1 in_size_q <= '0;
Tests: T1 T2 T3
437 end else begin
438 1/1 in_buf_q <= in_buf_d;
Tests: T1 T2 T3
439 1/1 in_size_q <= in_size_d;
Tests: T1 T2 T3
440 end
441 end
442 1/1 assign in_buf_d = in_xact_starting ? in_buf[in_xact_start_ep] : in_buf_q;
Tests: T1 T2 T3
443 1/1 assign in_size_d = in_xact_starting ? in_size[in_xact_start_ep] : in_size_q;
Tests: T1 T2 T3
444
445 // OUT data toggles are maintained with the packet engine but may be set or
446 // cleared by software
447 1/1 assign out_datatog_we = reg2hw.out_data_toggle.status.qe & reg2hw.out_data_toggle.mask.qe;
Tests: T29 T32 T37
448 1/1 assign out_datatog_status = reg2hw.out_data_toggle.status.q;
Tests: T1 T2 T3
449 1/1 assign out_datatog_mask = reg2hw.out_data_toggle.mask.q;
Tests: T1 T2 T3
450 // Software may read tham at any time
451 1/1 assign hw2reg.out_data_toggle.status.d = out_data_toggle;
Tests: T1 T2 T3
452 assign hw2reg.out_data_toggle.mask.d = {NEndpoints{1'b0}};
453
454 // IN data toggles are maintained with the packet engine but may be set or
455 // cleared by software
456 1/1 assign in_datatog_we = reg2hw.in_data_toggle.status.qe & reg2hw.in_data_toggle.mask.qe;
Tests: T29 T32 T109
457 1/1 assign in_datatog_status = reg2hw.in_data_toggle.status.q;
Tests: T1 T2 T3
458 1/1 assign in_datatog_mask = reg2hw.in_data_toggle.mask.q;
Tests: T1 T2 T3
459 // Software may read them at any time
460 1/1 assign hw2reg.in_data_toggle.status.d = in_data_toggle;
Tests: T1 T2 T3
461 assign hw2reg.in_data_toggle.mask.d = {NEndpoints{1'b0}};
462
463 always_comb begin
464 1/1 set_sentbit = '0;
Tests: T1 T2 T3
465 1/1 if (in_ep_xact_end && in_endpoint_val) begin
Tests: T1 T2 T3
466 1/1 set_sentbit[in_endpoint] = 1'b1;
Tests: T29 T32 T33
467 end
MISSING_ELSE
468 end
469
470 always_comb begin : proc_map_sent
471 1/1 for (int i = 0; i < NEndpoints; i++) begin
Tests: T29 T32 T33
472 1/1 hw2reg.in_sent[i].de = set_sentbit[i];
Tests: T29 T32 T33
473 1/1 hw2reg.in_sent[i].d = 1'b1;
Tests: T29 T32 T33
474 end
475 end
476
477 // This must be held level for the interrupt, so no sent packets are missed.
478 logic sent_event_pending;
479 always_comb begin
480 1/1 sent_event_pending = 1'b0;
Tests: T1 T2 T3
481 1/1 for (int i = 0; i < NEndpoints; i++) begin
Tests: T1 T2 T3
482 1/1 sent_event_pending |= reg2hw.in_sent[i].q;
Tests: T1 T2 T3
483 end
484 end
485
486 // Clear of rxenable_out bit
487 // If so configured, for every received transaction on a given endpoint, clear
488 // the rxenable_out bit. In this configuration, hardware defaults to NAKing
489 // any subsequent transaction, so software has time to decide the next
490 // response.
491 always_comb begin
492 1/1 clear_rxenable_out = '0;
Tests: T1 T2 T3
493 1/1 if (rx_wvalid && out_endpoint_val) begin
Tests: T1 T2 T3
494 1/1 clear_rxenable_out[out_endpoint] = ep_set_nak_on_out[out_endpoint];
Tests: T3 T28 T29
495 end
MISSING_ELSE
496 end
497
498 always_comb begin
499 1/1 for (int i = 0; i < NEndpoints; i++) begin
Tests: T72 T126 T141
500 1/1 hw2reg.rxenable_out[i].d = 1'b0;
Tests: T72 T126 T141
501 1/1 hw2reg.rxenable_out[i].de = clear_rxenable_out[i];
Tests: T72 T126 T141
502 end
503 end
504
505 always_comb begin
506 1/1 clear_rdybit = '0;
Tests: T1 T2 T3
507 1/1 update_pend = '0;
Tests: T1 T2 T3
508 1/1 if (event_link_reset) begin
Tests: T1 T2 T3
509 1/1 clear_rdybit = {NEndpoints{1'b1}};
Tests: T1 T2 T3
510 1/1 update_pend = {NEndpoints{1'b1}};
Tests: T1 T2 T3
511 end else begin
512 1/1 if (setup_received & out_endpoint_val) begin
Tests: T1 T2 T3
513 // Clear pending when a SETUP is received
514 1/1 clear_rdybit[out_endpoint] = 1'b1;
Tests: T3 T28 T30
515 1/1 update_pend[out_endpoint] = 1'b1;
Tests: T3 T28 T30
516 1/1 end else if (in_ep_xact_end & in_endpoint_val) begin
Tests: T1 T2 T3
517 // Clear rdy and sending when an IN transmission was successful
518 1/1 clear_rdybit[in_endpoint] = 1'b1;
Tests: T29 T32 T33
519 end
MISSING_ELSE
520 end
521 end
522
523 // IN transaction starting on any endpoint?
524 always_comb begin
525 1/1 set_sending = '0;
Tests: T1 T2 T3
526 2/2 if (in_xact_starting) set_sending[in_xact_start_ep] = 1'b1;
Tests: T1 T2 T3 | T29 T31 T32
MISSING_ELSE
527 end
528
529 // Clearing of rdy bit in response to successful IN packet transmission or packet cancellation
530 // through link reset or SETUP packet reception.
531 always_comb begin : proc_map_rdy_hw2reg
532 1/1 for (int i = 0; i < NEndpoints; i++) begin
Tests: T1 T2 T3
533 1/1 hw2reg.configin[i].rdy.de = clear_rdybit[i];
Tests: T1 T2 T3
534 1/1 hw2reg.configin[i].rdy.d = 1'b0;
Tests: T1 T2 T3
535 end
536 end
537
538 // Update the pending bit by copying the ready bit that is about to clear
539 always_comb begin : proc_map_pend
540 1/1 for (int i = 0; i < NEndpoints; i++) begin
Tests: T1 T2 T3
541 1/1 hw2reg.configin[i].pend.de = update_pend[i];
Tests: T1 T2 T3
542 1/1 hw2reg.configin[i].pend.d = reg2hw.configin[i].rdy.q | reg2hw.configin[i].pend.q;
Tests: T1 T2 T3
543 end
544 end
545
546 // Update the sending bit to mark that collection of the packet by the USB host has been
547 // attempted and FW shall not attempt retraction of the packet.
548 always_comb begin : proc_map_sending
549 1/1 for (int i = 0; i < NEndpoints; i++) begin
Tests: T1 T2 T3
550 1/1 hw2reg.configin[i].sending.de = set_sending[i] | set_sentbit[i] | update_pend[i];
Tests: T1 T2 T3
551 1/1 hw2reg.configin[i].sending.d = ~set_sentbit[i] & ~update_pend[i];
Tests: T1 T2 T3
552 end
553 end
554
555 ////////////////////////////////////////////////////////
556 // USB interface -- everything is in USB clock domain //
557 ////////////////////////////////////////////////////////
558 logic cfg_pinflip;
559 1/1 assign cfg_pinflip = reg2hw.phy_config.pinflip.q;
Tests: T1 T2 T3
560 1/1 assign usb_dp_pullup_en = cfg_pinflip ? 1'b0 : usb_pullup_en;
Tests: T1 T2 T3
561 1/1 assign usb_dn_pullup_en = !cfg_pinflip ? 1'b0 : usb_pullup_en;
Tests: T1 T2 T3
562
563
564 usbdev_usbif #(
565 .NEndpoints (NEndpoints),
566 .AVFifoWidth (AVFifoWidth),
567 .RXFifoWidth (RXFifoWidth),
568 .MaxPktSizeByte (MaxPktSizeByte),
569 .NBuf (NBuf),
570 .SramAw (SramAw)
571 ) usbdev_impl (
572 .clk_48mhz_i (clk_i),
573 .rst_ni (rst_n),
574
575 // Pins
576 .usb_d_i (usb_rx_d),
577 .usb_dp_i (usb_rx_dp),
578 .usb_dn_i (usb_rx_dn),
579 .usb_oe_o (usb_tx_oe),
580 .usb_d_o (usb_tx_d),
581 .usb_se0_o (usb_tx_se0),
582 .usb_dp_o (usb_tx_dp),
583 .usb_dn_o (usb_tx_dn),
584 .usb_sense_i (usb_pwr_sense),
585 .usb_pullup_en_o (usb_pullup_en),
586
587 // receive side
588 .rx_setup_i (enable_setup),
589 .rx_out_i (enable_out),
590 .rx_stall_i (out_ep_stall),
591 .avsetup_rvalid_i (avsetup_rvalid),
592 .avsetup_rready_o (avsetup_rready),
593 .avsetup_rdata_i (avsetup_rdata),
594 .avout_rvalid_i (avout_rvalid),
595 .avout_rready_o (avout_rready),
596 .avout_rdata_i (avout_rdata),
597
598 .rx_wvalid_o (rx_wvalid),
599 .rx_wready_setup_i (rx_wready_setup),
600 .rx_wready_out_i (rx_wready_out),
601 .rx_wdata_o (rx_wdata),
602 .setup_received_o (setup_received),
603 .out_endpoint_o (out_endpoint), // will be stable for several cycles
604 .out_endpoint_val_o (out_endpoint_val),
605
606 // transmit side
607 .in_xact_starting_o (in_xact_starting),
608 .in_xact_start_ep_o (in_xact_start_ep),
609 .in_buf_i (in_buf_q),
610 .in_size_i (in_size_q),
611 .in_stall_i (in_ep_stall),
612 .in_rdy_i (in_rdy),
613 .in_ep_xact_end_o (in_ep_xact_end),
614 .in_endpoint_o (in_endpoint),
615 .in_endpoint_val_o (in_endpoint_val),
616
617 // memory
618 .mem_req_o (usb_mem_b_req),
619 .mem_write_o (usb_mem_b_write),
620 .mem_addr_o (usb_mem_b_addr),
621 .mem_wdata_o (usb_mem_b_wdata),
622 .mem_rdata_i (usb_mem_b_rdata),
623
624 // time reference
625 .us_tick_i (us_tick),
626
627 // control
628 .connect_en_i (connect_en),
629 .devaddr_i (reg2hw.usbctrl.device_address.q),
630 .clr_devaddr_o (clr_devaddr),
631 .in_ep_enabled_i (ep_in_enable),
632 .out_ep_enabled_i (ep_out_enable),
633 .out_ep_iso_i (ep_out_iso),
634 .in_ep_iso_i (ep_in_iso),
635 .diff_rx_ok_i (usb_diff_rx_ok),
636 .cfg_eop_single_bit_i (reg2hw.phy_config.eop_single_bit.q), // cdc ok: quasi-static
637 .tx_osc_test_mode_i (reg2hw.phy_config.tx_osc_test_mode.q), // cdc ok: quasi-static
638 .cfg_use_diff_rcvr_i (usb_rx_enable_o),
639 .cfg_pinflip_i (cfg_pinflip),
640 .out_data_toggle_o (out_data_toggle),
641 .out_datatog_we_i (out_datatog_we),
642 .out_datatog_status_i (out_datatog_status),
643 .out_datatog_mask_i (out_datatog_mask),
644 .in_data_toggle_o (in_data_toggle),
645 .in_datatog_we_i (in_datatog_we),
646 .in_datatog_status_i (in_datatog_status),
647 .in_datatog_mask_i (in_datatog_mask),
648
649 .resume_link_active_i (resume_link_active),
650
651 // status
652 .frame_o (frame),
653 .frame_start_o (event_frame),
654 .sof_detected_o (event_sof),
655 .link_state_o (link_state),
656 .link_disconnect_o (link_disconnect),
657 .link_powered_o (link_powered),
658 .link_reset_o (link_reset),
659 .link_active_o (link_active),
660 .link_suspend_o (link_suspend),
661 .link_resume_o (event_link_resume),
662 .host_lost_o (host_lost),
663 .link_in_err_o (event_in_err),
664 .link_out_err_o (event_out_err),
665 .rx_crc5_err_o (event_rx_crc5_err),
666 .rx_crc16_err_o (event_rx_crc16_err),
667 .rx_pid_err_o (event_rx_pid_err),
668 .rx_bitstuff_err_o (event_rx_bitstuff_err),
669
670 // event counters
671 .event_ign_avsetup_o (event_ign_avsetup),
672 .event_drop_avout_o (event_drop_avout),
673 .event_drop_rx_o (event_drop_rx),
674 .event_datatog_out_o (event_datatog_out),
675 .event_timeout_in_o (event_timeout_in),
676 .event_nak_in_o (event_nak_in),
677 .event_nodata_in_o (event_nodata_in)
678 );
679
680 /////////////////////////////////
681 // Control signal / status CDC //
682 /////////////////////////////////
683
684 1/1 assign hw2reg.usbstat.link_state.d = link_state;
Tests: T1 T2 T3
685 1/1 assign hw2reg.usbstat.frame.d = frame;
Tests: T1 T2 T3
686
687 1/1 assign connect_en = reg2hw.usbctrl.enable.q;
Tests: T1 T2 T3
688 1/1 assign resume_link_active = reg2hw.usbctrl.resume_link_active.qe &
Tests: T1 T2 T3
689 reg2hw.usbctrl.resume_link_active.q;
690
691 // Just want a pulse to ensure only one interrupt for an event
692 prim_edge_detector #(
693 .Width(5),
694 .EnSync(1'b0)
695 ) gen_event (
696 .clk_i,
697 .rst_ni (rst_n),
698 .d_i ({link_disconnect, link_reset, link_suspend,
699 host_lost, link_powered}),
700 .q_sync_o (),
701 .q_posedge_pulse_o({event_disconnect, event_link_reset, event_link_suspend,
702 event_host_lost, event_powered}),
703 .q_negedge_pulse_o()
704 );
705
706 1/1 assign hw2reg.usbstat.host_lost.d = host_lost;
Tests: T1 T2 T3
707
708 // resets etc cause the device address to clear
709 1/1 assign hw2reg.usbctrl.device_address.de = clr_devaddr;
Tests: T1 T2 T3
710 assign hw2reg.usbctrl.device_address.d = '0;
711
712 // Clear the stall flag when a SETUP is received
713
714 always_comb begin : proc_stall_tieoff
715 1/1 for (int i = 0; i < NEndpoints; i++) begin
Tests: T1 T2 T3
716 1/1 hw2reg.in_stall[i].d = 1'b0;
Tests: T1 T2 T3
717 1/1 hw2reg.out_stall[i].d = 1'b0;
Tests: T1 T2 T3
718 1/1 if (setup_received && out_endpoint_val && out_endpoint == 4'(unsigned'(i))) begin
Tests: T1 T2 T3
719 1/1 hw2reg.out_stall[i].de = 1'b1;
Tests: T3 T28 T30
720 1/1 hw2reg.in_stall[i].de = 1'b1;
Tests: T3 T28 T30
721 end else begin
722 1/1 hw2reg.out_stall[i].de = 1'b0;
Tests: T1 T2 T3
723 1/1 hw2reg.in_stall[i].de = 1'b0;
Tests: T1 T2 T3
724 end
725 end
726 end
727
728 if (Stub) begin : gen_stubbed_memory
729 // Stub this window off with an error responder if stubbed.
730 tlul_err_resp u_tlul_err_resp (
731 .clk_i,
732 .rst_ni,
733 .tl_h_i(tl_sram_h2d),
734 .tl_h_o(tl_sram_d2h)
735 );
736
737 // Tie off unused signals
738 assign sw_mem_a_req = '0;
739 assign sw_mem_a_gnt = '0;
740 assign sw_mem_a_write = '0;
741 assign sw_mem_a_addr = '0;
742 assign sw_mem_a_wdata = '0;
743 assign sw_mem_a_rvalid = '0;
744 assign sw_mem_a_rdata = '0;
745 assign sw_mem_a_rerror = '0;
746
747 assign usb_mem_b_rdata = '0;
748
749 logic unused_usb_mem_b_sigs;
750 assign unused_usb_mem_b_sigs = ^{
751 ram_cfg_i,
752 usb_mem_b_req,
753 usb_mem_b_write,
754 usb_mem_b_addr,
755 usb_mem_b_wdata,
756 usb_mem_b_rdata
757 };
758 end else begin : gen_no_stubbed_memory
759 // TL-UL to SRAM adapter
760 tlul_adapter_sram #(
761 .SramAw(SramAw),
762 .ByteAccess(0)
763 ) u_tlul2sram (
764 .clk_i,
765 .rst_ni,
766
767 .tl_i (tl_sram_h2d),
768 .tl_o (tl_sram_d2h),
769 .en_ifetch_i (prim_mubi_pkg::MuBi4False),
770 .req_o (sw_mem_a_req),
771 .req_type_o (),
772 .gnt_i (sw_mem_a_gnt),
773 .we_o (sw_mem_a_write),
774 .addr_o (sw_mem_a_addr),
775 .wdata_o (sw_mem_a_wdata),
776 .wmask_o (), // Not used
777 .intg_error_o (),
778 .rdata_i (sw_mem_a_rdata),
779 .rvalid_i (sw_mem_a_rvalid),
780 .rerror_i (sw_mem_a_rerror),
781 .compound_txn_in_progress_o (),
782 .readback_en_i (prim_mubi_pkg::MuBi4False),
783 .readback_error_o (),
784 .wr_collision_i (1'b0),
785 .write_pending_i (1'b0)
786 );
787
788 // Single Port RAM implementation, which will award the `usb` port absolute priority and
789 // delay `sw` access by in the event of a collision.
790 //
791 // In practice the `usb` access to memory is sporadic (4x oversampling of bits, and read/write
792 // operations transfer 32 bits so on average the probability of collision is just 1/128 even
793 // during active USB traffic, if the TL-UL interface were active on every cycle).
794
795 // usb access has absolute priority, followed by any deferred write, and then any sw access.
796 logic mem_req;
797 logic mem_write;
798 logic [SramAw-1:0] mem_addr;
799 logic [SramDw-1:0] mem_wdata;
800 1/1 assign mem_req = usb_mem_b_req | sw_mem_a_req;
Tests: T1 T2 T3
801 1/1 assign mem_write = usb_mem_b_req ? usb_mem_b_write : sw_mem_a_write;
Tests: T1 T2 T3
802 1/1 assign mem_addr = usb_mem_b_req ? usb_mem_b_addr : sw_mem_a_addr;
Tests: T1 T2 T3
803 1/1 assign mem_wdata = usb_mem_b_req ? usb_mem_b_wdata : sw_mem_a_wdata;
Tests: T1 T2 T3
804
805 logic mem_rvalid;
806 logic [SramDw-1:0] mem_rdata;
807 logic [1:0] mem_rerror;
808 logic mem_rsteering;
809
810 // Always grant when no `usb` request.
811 1/1 assign sw_mem_a_gnt = !usb_mem_b_req;
Tests: T1 T2 T3
812
813 // `usb` relies upon its read data remaining static after read.
814 logic mem_b_read_q;
815 logic [SramDw-1:0] mem_b_rdata_q;
816
817 // Remember granted read accesses.
818 // NOTE: No pipelining within the RAM model.
819 always_ff @(posedge clk_i or negedge rst_ni) begin
820 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
821 1/1 mem_rsteering <= 1'b0;
Tests: T1 T2 T3
822 1/1 mem_b_read_q <= 1'b0;
Tests: T1 T2 T3
823 1/1 mem_b_rdata_q <= {SramDw{1'b0}};
Tests: T1 T2 T3
824 end else begin
825 1/1 mem_rsteering <= usb_mem_b_req;
Tests: T1 T2 T3
826 1/1 mem_b_read_q <= usb_mem_b_req & !usb_mem_b_write;
Tests: T1 T2 T3
827 // Capture the `usb` read data.
828 1/1 if (mem_b_read_q)
Tests: T1 T2 T3
829 1/1 mem_b_rdata_q <= mem_rdata;
Tests: T29 T31 T32
MISSING_ELSE
830 end
831 end
832
833 // Read responses.
834 1/1 assign sw_mem_a_rvalid = mem_rvalid & !mem_rsteering;
Tests: T1 T2 T3
835 unreachable assign sw_mem_a_rerror = {2{sw_mem_a_rvalid}} & mem_rerror;
836 // We may safely return the read data to both (no security implications), but `usb` rdata
837 // must be held static after the read, and be unaffected by `sw` reads.
838 1/1 assign sw_mem_a_rdata = mem_rdata;
Tests: T3 T29 T32
839 1/1 assign usb_mem_b_rdata = mem_b_read_q ? mem_rdata : mem_b_rdata_q;
Tests: T1 T2 T3
840
841 // SRAM Wrapper
842 prim_ram_1p_adv #(
843 .Depth (SramDepth),
844 .Width (SramDw), // 32 x 512 --> 2kB
845 .DataBitsPerMask(8),
846
847 .EnableECC (0), // No Protection
848 .EnableParity (0),
849 .EnableInputPipeline (0),
850 .EnableOutputPipeline(0)
851 ) u_memory_1p (
852 .clk_i,
853 .rst_ni,
854
855 .req_i (mem_req),
856 .write_i (mem_write),
857 .addr_i (mem_addr),
858 .wdata_i (mem_wdata),
859 .wmask_i ({SramDw{1'b1}}),
860 .rdata_o (mem_rdata),
861 .rvalid_o (mem_rvalid),
862 .rerror_o (mem_rerror),
863 .cfg_i (ram_cfg_i),
864 .alert_o ()
865 );
866 end : gen_no_stubbed_memory
867
868 logic [NumAlerts-1:0] alert_test, alerts;
869
870 // Register module
871 usbdev_reg_top u_reg (
872 .clk_i,
873 .rst_ni, // this reset is not stubbed off so that the registers are still accessible.
874 .clk_aon_i,
875 .rst_aon_ni, // this reset is not stubbed off so that the registers are still accessible.
876
877 .tl_i (tl_i),
878 .tl_o (tl_o),
879
880 .tl_win_o (tl_sram_h2d),
881 .tl_win_i (tl_sram_d2h),
882
883 .reg2hw(reg2hw_regtop),
884 .hw2reg(hw2reg_regtop),
885
886 // SEC_CM: BUS.INTEGRITY
887 .intg_err_o (alerts[0])
888 );
889
890 // Stub off all register connections to reg_top.
891 if (Stub) begin : gen_stubbed
892 logic unused_sigs;
893 assign reg2hw = '0;
894 assign hw2reg_regtop = '0;
895 assign unused_sigs = ^{reg2hw_regtop, hw2reg};
896 end else begin : gen_not_stubbed
897 1/1 assign reg2hw = reg2hw_regtop;
Tests: T1 T2 T3
898 1/1 assign hw2reg_regtop = hw2reg;
Tests: T1 T2 T3
899 end
900
901 // Alerts
902 1/1 assign alert_test = {
Tests: T1 T2 T3
903 reg2hw.alert_test.q &
904 reg2hw.alert_test.qe
905 };
906
907 // Alerts not stubbed off because registers and T-L access still present.
908 localparam logic [NumAlerts-1:0] AlertIsFatal = {NumAlerts{1'b1}};
909 for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_tx
910 prim_alert_sender #(
911 .AsyncOn(AlertAsyncOn[i]),
912 .IsFatal(AlertIsFatal[i])
913 ) u_prim_alert_sender (
914 .clk_i,
915 .rst_ni, // this reset is not stubbed off so that the pings still work.
916 .alert_test_i ( alert_test[i] ),
917 .alert_req_i ( alerts[0] ),
918 .alert_ack_o ( ),
919 .alert_state_o ( ),
920 .alert_rx_i ( alert_rx_i[i] ),
921 .alert_tx_o ( alert_tx_o[i] )
922 );
923 end
924
925 // Interrupts
926 prim_intr_hw #(.Width(1), .IntrT("Status")) intr_hw_pkt_received (
927 .clk_i,
928 .rst_ni, // not stubbed off so that the interrupt regs still work.
929 .event_intr_i (event_pkt_received),
930 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.pkt_received.q),
931 .reg2hw_intr_test_q_i (reg2hw.intr_test.pkt_received.q),
932 .reg2hw_intr_test_qe_i (reg2hw.intr_test.pkt_received.qe),
933 .reg2hw_intr_state_q_i (reg2hw.intr_state.pkt_received.q),
934 .hw2reg_intr_state_de_o (hw2reg.intr_state.pkt_received.de),
935 .hw2reg_intr_state_d_o (hw2reg.intr_state.pkt_received.d),
936 .intr_o (intr_pkt_received_o)
937 );
938
939 prim_intr_hw #(.Width(1), .IntrT("Status")) intr_hw_pkt_sent (
940 .clk_i,
941 .rst_ni, // not stubbed off so that the interrupt regs still work.
942 .event_intr_i (sent_event_pending),
943 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.pkt_sent.q),
944 .reg2hw_intr_test_q_i (reg2hw.intr_test.pkt_sent.q),
945 .reg2hw_intr_test_qe_i (reg2hw.intr_test.pkt_sent.qe),
946 .reg2hw_intr_state_q_i (reg2hw.intr_state.pkt_sent.q),
947 .hw2reg_intr_state_de_o (hw2reg.intr_state.pkt_sent.de),
948 .hw2reg_intr_state_d_o (hw2reg.intr_state.pkt_sent.d),
949 .intr_o (intr_pkt_sent_o)
950 );
951
952 prim_intr_hw #(.Width(1)) intr_disconnected (
953 .clk_i,
954 .rst_ni, // not stubbed off so that the interrupt regs still work.
955 .event_intr_i (event_disconnect),
956 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.disconnected.q),
957 .reg2hw_intr_test_q_i (reg2hw.intr_test.disconnected.q),
958 .reg2hw_intr_test_qe_i (reg2hw.intr_test.disconnected.qe),
959 .reg2hw_intr_state_q_i (reg2hw.intr_state.disconnected.q),
960 .hw2reg_intr_state_de_o (hw2reg.intr_state.disconnected.de),
961 .hw2reg_intr_state_d_o (hw2reg.intr_state.disconnected.d),
962 .intr_o (intr_disconnected_o)
963 );
964
965 prim_intr_hw #(.Width(1)) intr_powered (
966 .clk_i,
967 .rst_ni, // not stubbed off so that the interrupt regs still work.
968 .event_intr_i (event_powered),
969 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.powered.q),
970 .reg2hw_intr_test_q_i (reg2hw.intr_test.powered.q),
971 .reg2hw_intr_test_qe_i (reg2hw.intr_test.powered.qe),
972 .reg2hw_intr_state_q_i (reg2hw.intr_state.powered.q),
973 .hw2reg_intr_state_de_o (hw2reg.intr_state.powered.de),
974 .hw2reg_intr_state_d_o (hw2reg.intr_state.powered.d),
975 .intr_o (intr_powered_o)
976 );
977
978 prim_intr_hw #(.Width(1)) intr_host_lost (
979 .clk_i,
980 .rst_ni, // not stubbed off so that the interrupt regs still work.
981 .event_intr_i (event_host_lost),
982 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.host_lost.q),
983 .reg2hw_intr_test_q_i (reg2hw.intr_test.host_lost.q),
984 .reg2hw_intr_test_qe_i (reg2hw.intr_test.host_lost.qe),
985 .reg2hw_intr_state_q_i (reg2hw.intr_state.host_lost.q),
986 .hw2reg_intr_state_de_o (hw2reg.intr_state.host_lost.de),
987 .hw2reg_intr_state_d_o (hw2reg.intr_state.host_lost.d),
988 .intr_o (intr_host_lost_o)
989 );
990
991 prim_intr_hw #(.Width(1)) intr_link_reset (
992 .clk_i,
993 .rst_ni, // not stubbed off so that the interrupt regs still work.
994 .event_intr_i (event_link_reset),
995 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.link_reset.q),
996 .reg2hw_intr_test_q_i (reg2hw.intr_test.link_reset.q),
997 .reg2hw_intr_test_qe_i (reg2hw.intr_test.link_reset.qe),
998 .reg2hw_intr_state_q_i (reg2hw.intr_state.link_reset.q),
999 .hw2reg_intr_state_de_o (hw2reg.intr_state.link_reset.de),
1000 .hw2reg_intr_state_d_o (hw2reg.intr_state.link_reset.d),
1001 .intr_o (intr_link_reset_o)
1002 );
1003
1004 prim_intr_hw #(.Width(1)) intr_link_suspend (
1005 .clk_i,
1006 .rst_ni, // not stubbed off so that the interrupt regs still work.
1007 .event_intr_i (event_link_suspend),
1008 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.link_suspend.q),
1009 .reg2hw_intr_test_q_i (reg2hw.intr_test.link_suspend.q),
1010 .reg2hw_intr_test_qe_i (reg2hw.intr_test.link_suspend.qe),
1011 .reg2hw_intr_state_q_i (reg2hw.intr_state.link_suspend.q),
1012 .hw2reg_intr_state_de_o (hw2reg.intr_state.link_suspend.de),
1013 .hw2reg_intr_state_d_o (hw2reg.intr_state.link_suspend.d),
1014 .intr_o (intr_link_suspend_o)
1015 );
1016
1017 prim_intr_hw #(.Width(1)) intr_link_resume (
1018 .clk_i,
1019 .rst_ni, // not stubbed off so that the interrupt regs still work.
1020 .event_intr_i (event_link_resume),
1021 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.link_resume.q),
1022 .reg2hw_intr_test_q_i (reg2hw.intr_test.link_resume.q),
1023 .reg2hw_intr_test_qe_i (reg2hw.intr_test.link_resume.qe),
1024 .reg2hw_intr_state_q_i (reg2hw.intr_state.link_resume.q),
1025 .hw2reg_intr_state_de_o (hw2reg.intr_state.link_resume.de),
1026 .hw2reg_intr_state_d_o (hw2reg.intr_state.link_resume.d),
1027 .intr_o (intr_link_resume_o)
1028 );
1029
1030 prim_intr_hw #(.Width(1), .IntrT("Status")) intr_av_out_empty (
1031 .clk_i,
1032 .rst_ni, // not stubbed off so that the interrupt regs still work.
1033 .event_intr_i (event_av_out_empty),
1034 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.av_out_empty.q),
1035 .reg2hw_intr_test_q_i (reg2hw.intr_test.av_out_empty.q),
1036 .reg2hw_intr_test_qe_i (reg2hw.intr_test.av_out_empty.qe),
1037 .reg2hw_intr_state_q_i (reg2hw.intr_state.av_out_empty.q),
1038 .hw2reg_intr_state_de_o (hw2reg.intr_state.av_out_empty.de),
1039 .hw2reg_intr_state_d_o (hw2reg.intr_state.av_out_empty.d),
1040 .intr_o (intr_av_out_empty_o)
1041 );
1042
1043 prim_intr_hw #(.Width(1), .IntrT("Status")) intr_rx_full (
1044 .clk_i,
1045 .rst_ni, // not stubbed off so that the interrupt regs still work.
1046 .event_intr_i (event_rx_full),
1047 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rx_full.q),
1048 .reg2hw_intr_test_q_i (reg2hw.intr_test.rx_full.q),
1049 .reg2hw_intr_test_qe_i (reg2hw.intr_test.rx_full.qe),
1050 .reg2hw_intr_state_q_i (reg2hw.intr_state.rx_full.q),
1051 .hw2reg_intr_state_de_o (hw2reg.intr_state.rx_full.de),
1052 .hw2reg_intr_state_d_o (hw2reg.intr_state.rx_full.d),
1053 .intr_o (intr_rx_full_o)
1054 );
1055
1056 prim_intr_hw #(.Width(1)) intr_av_overflow (
1057 .clk_i,
1058 .rst_ni, // not stubbed off so that the interrupt regs still work.
1059 .event_intr_i (event_av_overflow),
1060 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.av_overflow.q),
1061 .reg2hw_intr_test_q_i (reg2hw.intr_test.av_overflow.q),
1062 .reg2hw_intr_test_qe_i (reg2hw.intr_test.av_overflow.qe),
1063 .reg2hw_intr_state_q_i (reg2hw.intr_state.av_overflow.q),
1064 .hw2reg_intr_state_de_o (hw2reg.intr_state.av_overflow.de),
1065 .hw2reg_intr_state_d_o (hw2reg.intr_state.av_overflow.d),
1066 .intr_o (intr_av_overflow_o)
1067 );
1068
1069 prim_intr_hw #(.Width(1)) intr_link_in_err (
1070 .clk_i,
1071 .rst_ni, // not stubbed off so that the interrupt regs still work.
1072 .event_intr_i (event_in_err),
1073 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.link_in_err.q),
1074 .reg2hw_intr_test_q_i (reg2hw.intr_test.link_in_err.q),
1075 .reg2hw_intr_test_qe_i (reg2hw.intr_test.link_in_err.qe),
1076 .reg2hw_intr_state_q_i (reg2hw.intr_state.link_in_err.q),
1077 .hw2reg_intr_state_de_o (hw2reg.intr_state.link_in_err.de),
1078 .hw2reg_intr_state_d_o (hw2reg.intr_state.link_in_err.d),
1079 .intr_o (intr_link_in_err_o)
1080 );
1081
1082 prim_intr_hw #(.Width(1)) intr_link_out_err (
1083 .clk_i,
1084 .rst_ni, // not stubbed off so that the interrupt regs still work.
1085 .event_intr_i (event_out_err),
1086 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.link_out_err.q),
1087 .reg2hw_intr_test_q_i (reg2hw.intr_test.link_out_err.q),
1088 .reg2hw_intr_test_qe_i (reg2hw.intr_test.link_out_err.qe),
1089 .reg2hw_intr_state_q_i (reg2hw.intr_state.link_out_err.q),
1090 .hw2reg_intr_state_de_o (hw2reg.intr_state.link_out_err.de),
1091 .hw2reg_intr_state_d_o (hw2reg.intr_state.link_out_err.d),
1092 .intr_o (intr_link_out_err_o)
1093 );
1094
1095 prim_intr_hw #(.Width(1)) intr_rx_crc_err (
1096 .clk_i,
1097 .rst_ni, // not stubbed off so that the interrupt regs still work.
1098 .event_intr_i (event_rx_crc_err),
1099 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rx_crc_err.q),
1100 .reg2hw_intr_test_q_i (reg2hw.intr_test.rx_crc_err.q),
1101 .reg2hw_intr_test_qe_i (reg2hw.intr_test.rx_crc_err.qe),
1102 .reg2hw_intr_state_q_i (reg2hw.intr_state.rx_crc_err.q),
1103 .hw2reg_intr_state_de_o (hw2reg.intr_state.rx_crc_err.de),
1104 .hw2reg_intr_state_d_o (hw2reg.intr_state.rx_crc_err.d),
1105 .intr_o (intr_rx_crc_err_o)
1106 );
1107
1108 prim_intr_hw #(.Width(1)) intr_rx_pid_err (
1109 .clk_i,
1110 .rst_ni, // not stubbed off so that the interrupt regs still work.
1111 .event_intr_i (event_rx_pid_err),
1112 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rx_pid_err.q),
1113 .reg2hw_intr_test_q_i (reg2hw.intr_test.rx_pid_err.q),
1114 .reg2hw_intr_test_qe_i (reg2hw.intr_test.rx_pid_err.qe),
1115 .reg2hw_intr_state_q_i (reg2hw.intr_state.rx_pid_err.q),
1116 .hw2reg_intr_state_de_o (hw2reg.intr_state.rx_pid_err.de),
1117 .hw2reg_intr_state_d_o (hw2reg.intr_state.rx_pid_err.d),
1118 .intr_o (intr_rx_pid_err_o)
1119 );
1120
1121 prim_intr_hw #(.Width(1)) intr_rx_bitstuff_err (
1122 .clk_i,
1123 .rst_ni, // not stubbed off so that the interrupt regs still work.
1124 .event_intr_i (event_rx_bitstuff_err),
1125 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rx_bitstuff_err.q),
1126 .reg2hw_intr_test_q_i (reg2hw.intr_test.rx_bitstuff_err.q),
1127 .reg2hw_intr_test_qe_i (reg2hw.intr_test.rx_bitstuff_err.qe),
1128 .reg2hw_intr_state_q_i (reg2hw.intr_state.rx_bitstuff_err.q),
1129 .hw2reg_intr_state_de_o (hw2reg.intr_state.rx_bitstuff_err.de),
1130 .hw2reg_intr_state_d_o (hw2reg.intr_state.rx_bitstuff_err.d),
1131 .intr_o (intr_rx_bitstuff_err_o)
1132 );
1133
1134 prim_intr_hw #(.Width(1)) intr_frame (
1135 .clk_i,
1136 .rst_ni, // not stubbed off so that the interrupt regs still work.
1137 .event_intr_i (event_frame),
1138 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.frame.q),
1139 .reg2hw_intr_test_q_i (reg2hw.intr_test.frame.q),
1140 .reg2hw_intr_test_qe_i (reg2hw.intr_test.frame.qe),
1141 .reg2hw_intr_state_q_i (reg2hw.intr_state.frame.q),
1142 .hw2reg_intr_state_de_o (hw2reg.intr_state.frame.de),
1143 .hw2reg_intr_state_d_o (hw2reg.intr_state.frame.d),
1144 .intr_o (intr_frame_o)
1145 );
1146
1147 prim_intr_hw #(.Width(1), .IntrT("Status")) intr_av_setup_empty (
1148 .clk_i,
1149 .rst_ni, // not stubbed off so that the interrupt regs still work.
1150 .event_intr_i (event_av_setup_empty),
1151 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.av_setup_empty.q),
1152 .reg2hw_intr_test_q_i (reg2hw.intr_test.av_setup_empty.q),
1153 .reg2hw_intr_test_qe_i (reg2hw.intr_test.av_setup_empty.qe),
1154 .reg2hw_intr_state_q_i (reg2hw.intr_state.av_setup_empty.q),
1155 .hw2reg_intr_state_de_o (hw2reg.intr_state.av_setup_empty.de),
1156 .hw2reg_intr_state_d_o (hw2reg.intr_state.av_setup_empty.d),
1157 .intr_o (intr_av_setup_empty_o)
1158 );
1159
1160 /////////////////////////////////
1161 // USB IO Muxing //
1162 /////////////////////////////////
1163 logic cio_usb_oe;
1164 logic usb_rx_enable;
1165 1/1 assign cio_usb_dp_en_o = cio_usb_oe;
Tests: T1 T2 T3
1166 1/1 assign cio_usb_dn_en_o = cio_usb_oe;
Tests: T1 T2 T3
1167 1/1 assign usb_tx_use_d_se0_o = reg2hw.phy_config.tx_use_d_se0.q; // cdc ok: quasi-static
Tests: T1 T2 T3
1168 1/1 assign hw2reg.usbstat.sense.d = usb_pwr_sense;
Tests: T1 T2 T3
1169
1170 usbdev_iomux i_usbdev_iomux (
1171 .clk_i,
1172 .rst_ni (rst_n),
1173
1174 // Register interface
1175 .hw2reg_sense_o (hw2reg.phy_pins_sense),
1176 .reg2hw_drive_i (reg2hw.phy_pins_drive),
1177
1178 // Chip IO
1179 .usb_rx_d_i (usb_rx_d_i),
1180 .usb_rx_dp_i (cio_usb_dp_i),
1181 .usb_rx_dn_i (cio_usb_dn_i),
1182 .cio_usb_sense_i (cio_sense_i),
1183 .usb_tx_d_o (usb_tx_d_o),
1184 .usb_tx_se0_o (usb_tx_se0_o),
1185 .usb_tx_dp_o (cio_usb_dp_o),
1186 .usb_tx_dn_o (cio_usb_dn_o),
1187 .usb_tx_oe_o (cio_usb_oe),
1188 .usb_dp_pullup_en_o (usb_dp_pullup_o),
1189 .usb_dn_pullup_en_o (usb_dn_pullup_o),
1190 .usb_rx_enable_o (usb_rx_enable_o),
1191
1192 // Internal interface
1193 .usb_rx_d_o (usb_rx_d),
1194 .usb_rx_dp_o (usb_rx_dp),
1195 .usb_rx_dn_o (usb_rx_dn),
1196 .usb_tx_d_i (usb_tx_d),
1197 .usb_tx_se0_i (usb_tx_se0),
1198 .usb_tx_dp_i (usb_tx_dp),
1199 .usb_tx_dn_i (usb_tx_dn),
1200 .usb_tx_oe_i (usb_tx_oe),
1201 .usb_pwr_sense_o (usb_pwr_sense),
1202 .usb_dp_pullup_en_i (usb_dp_pullup_en),
1203 .usb_dn_pullup_en_i (usb_dn_pullup_en),
1204 .usb_rx_enable_i (usb_rx_enable)
1205 );
1206
1207 // Differential receiver enable
1208 1/1 assign use_diff_rcvr = reg2hw.phy_config.use_diff_rcvr.q;
Tests: T1 T2 T3
1209 // enable rx only when the single-ended input is enabled and the device is
1210 // not suspended (unless it is forced on in the I/O mux).
1211 1/1 assign usb_rx_enable = use_diff_rcvr & ~link_suspend;
Tests: T1 T2 T3
1212
1213 // Symbols from the differential receiver are invalid until it has finished
1214 // waking up / powering on
1215 // Add 1 to the specified time to account for uncertainty in the
1216 // free-running counter for us_tick.
1217 localparam int RcvrWakeTimeWidth = vbits(RcvrWakeTimeUs + 2);
1218 logic [RcvrWakeTimeWidth-1:0] usb_rcvr_ok_counter_d, usb_rcvr_ok_counter_q;
1219
1220 1/1 assign usb_diff_rx_ok = (usb_rcvr_ok_counter_q == '0);
Tests: T1 T2 T3
1221 always_comb begin
1222 // When don't need to use a differential receiver, RX is always ready
1223 1/1 usb_rcvr_ok_counter_d = '0;
Tests: T1 T2 T3
1224 1/1 if (use_diff_rcvr & !usb_rx_enable_o) begin
Tests: T1 T2 T3
1225 1/1 usb_rcvr_ok_counter_d = RcvrWakeTimeWidth'(RcvrWakeTimeUs + 1);
Tests: T7 T18 T8
1226 1/1 end else if (us_tick && (usb_rcvr_ok_counter_q > '0)) begin
Tests: T1 T2 T3
1227 1/1 usb_rcvr_ok_counter_d = usb_rcvr_ok_counter_q - 1;
Tests: T203 T204 T205
1228 end
MISSING_ELSE
1229 end
1230
1231 always_ff @(posedge clk_i or negedge rst_n) begin
1232 1/1 if (!rst_n) begin
Tests: T1 T2 T3
1233 1/1 usb_rcvr_ok_counter_q <= RcvrWakeTimeWidth'(RcvrWakeTimeUs + 1);
Tests: T1 T2 T3
1234 end else begin
1235 1/1 usb_rcvr_ok_counter_q <= usb_rcvr_ok_counter_d;
Tests: T1 T2 T3
1236 end
1237 end
1238
1239 /////////////////////////////////////////
1240 // SOF Reference for Clock Calibration //
1241 /////////////////////////////////////////
1242
1243 logic usb_ref_val_d, usb_ref_val_q;
1244 logic usb_ref_disable;
1245 1/1 assign usb_ref_disable = reg2hw.phy_config.usb_ref_disable.q;
Tests: T1 T2 T3
1246
1247 // Directly forward the pulse unless disabled.
1248 1/1 assign usb_ref_pulse_o = usb_ref_disable ? 1'b0 : event_sof;
Tests: T1 T2 T3
1249
1250 // The first pulse is always ignored, but causes the valid to be asserted.
1251 // The valid signal is deasserted when:
1252 // - The link is no longer active.
1253 // - The host is lost (no SOF for 4ms).
1254 // - The reference generation is disabled.
1255 1/1 assign usb_ref_val_d = usb_ref_pulse_o ? 1'b1 :
Tests: T1 T2 T3
1256 (!link_active || host_lost || usb_ref_disable) ? 1'b0 : usb_ref_val_q;
1257
1258 always_ff @(posedge clk_i or negedge rst_n) begin
1259 1/1 if (!rst_n) begin
Tests: T1 T2 T3
1260 1/1 usb_ref_val_q <= 1'b0;
Tests: T1 T2 T3
1261 end else begin
1262 1/1 usb_ref_val_q <= usb_ref_val_d;
Tests: T1 T2 T3
1263 end
1264 end
1265
1266 1/1 assign usb_ref_val_o = usb_ref_val_q;
Tests: T1 T2 T3
1267
1268 /////////////////////////////////////////
1269 // USB aon detector signaling //
1270 /////////////////////////////////////////
1271 1/1 assign usb_aon_suspend_req_o = reg2hw.wake_control.suspend_req.qe &
Tests: T1 T2 T3
1272 reg2hw.wake_control.suspend_req.q;
1273 1/1 assign usb_aon_wake_ack_o = reg2hw.wake_control.wake_ack.qe &
Tests: T1 T2 T3
1274 reg2hw.wake_control.wake_ack.q;
1275
1276 /////////////////////////////////////////
1277 // capture async event and debug info //
1278 /////////////////////////////////////////
1279
1280 assign hw2reg.wake_events.module_active.de = 1'b1;
1281 1/1 assign hw2reg.wake_events.module_active.d = usb_aon_wake_detect_active_i;
Tests: T7 T8 T9
1282 assign hw2reg.wake_events.bus_not_idle.de = 1'b1;
1283 1/1 assign hw2reg.wake_events.bus_not_idle.d = usb_aon_bus_not_idle_i;
Tests: T7 T9 T10
1284 assign hw2reg.wake_events.disconnected.de = 1'b1;
1285 1/1 assign hw2reg.wake_events.disconnected.d = usb_aon_sense_lost_i;
Tests: T8 T11 T13
1286 assign hw2reg.wake_events.bus_reset.de = 1'b1;
1287 1/1 assign hw2reg.wake_events.bus_reset.d = usb_aon_bus_reset_i;
Tests: T7 T10 T14
1288
1289 /////////////////////////////////////
1290 // Diagnostic/performance counters //
1291 /////////////////////////////////////
1292
1293 // SW write strobes for the event enables of the counters.
1294 logic ctr_out_ev_qe;
1295 logic ctr_in_ev_qe;
1296 logic ctr_errors_ev_qe;
1297 0/1 ==> assign ctr_out_ev_qe = &{reg2hw.count_out.ign_avsetup.qe,
1298 reg2hw.count_out.drop_avout.qe,
1299 reg2hw.count_out.drop_rx.qe,
1300 reg2hw.count_out.datatog_out.qe};
1301 0/1 ==> assign ctr_in_ev_qe = &{reg2hw.count_in.timeout.qe,
1302 reg2hw.count_in.nak.qe,
1303 reg2hw.count_in.nodata.qe};
1304 0/1 ==> assign ctr_errors_ev_qe = &{reg2hw.count_errors.crc5.qe,
Cond Coverage for Instance : tb.dut
| Total | Covered | Percent |
|---|
| Conditions | 126 | 117 | 92.86 |
| Logical | 126 | 117 | 92.86 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 167
EXPRESSION (event_rx_crc5_err | event_rx_crc16_err)
--------1-------- ---------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T2,T37,T39 |
| 1 | 0 | Covered | T19,T110,T73 |
LINE 220
EXPRESSION (ns_cnt == 6'd47)
--------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 257
EXPRESSION (reg2hw.fifo_ctrl.avsetup_rst.qe & reg2hw.fifo_ctrl.avsetup_rst.q)
---------------1--------------- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T42,T43,T37 |
| 1 | 0 | Covered | T32,T38,T108 |
| 1 | 1 | Covered | T42,T43,T37 |
LINE 258
EXPRESSION (reg2hw.fifo_ctrl.avout_rst.qe & reg2hw.fifo_ctrl.avout_rst.q)
--------------1-------------- --------------2-------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T42,T43,T32 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T42,T43,T32 |
LINE 259
EXPRESSION (reg2hw.fifo_ctrl.rx_rst.qe & reg2hw.fifo_ctrl.rx_rst.q)
-------------1------------ ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T42,T43,T37 |
| 1 | 0 | Covered | T32,T38,T108 |
| 1 | 1 | Covered | T42,T43,T37 |
LINE 263
EXPRESSION (connect_en & ((~avsetup_rvalid)))
-----1---- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T3,T28 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 264
EXPRESSION (connect_en & ((~avout_rvalid)))
-----1---- --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T29,T41 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 266
EXPRESSION ((reg2hw.avsetupbuffer.qe & ((~avsetup_fifo_wready))) | (reg2hw.avoutbuffer.qe & ((~avout_fifo_wready))))
--------------------------1------------------------- ------------------------2-----------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T62,T87 |
| 1 | 0 | Covered | T1,T63,T86 |
LINE 266
SUB-EXPRESSION (reg2hw.avsetupbuffer.qe & ((~avsetup_fifo_wready)))
-----------1----------- ------------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T3,T28 |
| 1 | 1 | Covered | T1,T63,T86 |
LINE 266
SUB-EXPRESSION (reg2hw.avoutbuffer.qe & ((~avout_fifo_wready)))
----------1---------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T29,T41 |
| 1 | 1 | Covered | T62,T87 |
LINE 268
EXPRESSION (connect_en & ((~rx_fifo_rvalid)))
-----1---- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T28,T29 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 316
EXPRESSION (reg2hw.rxfifo.ep.re | reg2hw.rxfifo.setup.re | reg2hw.rxfifo.size.re | reg2hw.rxfifo.buffer.re)
---------1--------- -----------2---------- ----------3---------- -----------4-----------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 1 | Excluded | |
VC_COV_UNR |
| 0 | 0 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 0 | 1 | 0 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 0 | 0 | 0 | Excluded | |
VC_COV_UNR |
LINE 327
EXPRESSION (rx_wready & (rx_depth < 4'((RXFifoDepth - 1))))
----1---- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T30,T37,T38 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 442
EXPRESSION (in_xact_starting ? in_buf[in_xact_start_ep] : in_buf_q)
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T29,T31,T32 |
LINE 443
EXPRESSION (in_xact_starting ? in_size[in_xact_start_ep] : in_size_q)
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T29,T31,T32 |
LINE 447
EXPRESSION (reg2hw.out_data_toggle.status.qe & reg2hw.out_data_toggle.mask.qe)
----------------1--------------- ---------------2--------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Covered | T29,T32,T37 |
LINE 456
EXPRESSION (reg2hw.in_data_toggle.status.qe & reg2hw.in_data_toggle.mask.qe)
---------------1--------------- --------------2--------------
| -1- | -2- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | Excluded | |
VC_COV_UNR |
| 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | Covered | T29,T32,T109 |
LINE 465
EXPRESSION (in_ep_xact_end && in_endpoint_val)
-------1------ -------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
| 1 | 1 | Covered | T29,T32,T33 |
LINE 493
EXPRESSION (rx_wvalid && out_endpoint_val)
----1---- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
| 1 | 1 | Covered | T3,T28,T29 |
LINE 512
EXPRESSION (setup_received & out_endpoint_val)
-------1------ --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
| 1 | 1 | Covered | T3,T28,T30 |
LINE 516
EXPRESSION (in_ep_xact_end & in_endpoint_val)
-------1------ -------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
| 1 | 1 | Covered | T29,T32,T33 |
LINE 542
EXPRESSION (reg2hw.configin[i].rdy.q | reg2hw.configin[i].pend.q)
------------1----------- ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T85,T171,T68 |
| 1 | 0 | Covered | T29,T43,T31 |
LINE 550
EXPRESSION (set_sending[i] | set_sentbit[i] | update_pend[i])
-------1------ -------2------ -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T1,T2,T3 |
| 0 | 1 | 0 | Covered | T29,T32,T33 |
| 1 | 0 | 0 | Covered | T29,T31,T32 |
LINE 551
EXPRESSION (((~set_sentbit[i])) & ((~update_pend[i])))
---------1--------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T29,T32,T33 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 560
EXPRESSION (cfg_pinflip ? 1'b0 : usb_pullup_en)
-----1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T49,T52,T206 |
LINE 561
EXPRESSION (((!cfg_pinflip)) ? 1'b0 : usb_pullup_en)
--------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T49,T52,T206 |
| 1 | Covered | T1,T2,T3 |
LINE 688
EXPRESSION (reg2hw.usbctrl.resume_link_active.qe & reg2hw.usbctrl.resume_link_active.q)
------------------1----------------- -----------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T93,T94,T95 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T93,T94,T95 |
LINE 800
EXPRESSION (usb_mem_b_req | sw_mem_a_req)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T3,T29,T43 |
| 1 | 0 | Covered | T3,T28,T29 |
LINE 801
EXPRESSION (usb_mem_b_req ? usb_mem_b_write : sw_mem_a_write)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T28,T29 |
LINE 802
EXPRESSION (usb_mem_b_req ? usb_mem_b_addr : sw_mem_a_addr)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T28,T29 |
LINE 803
EXPRESSION (usb_mem_b_req ? usb_mem_b_wdata : sw_mem_a_wdata)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T28,T29 |
LINE 826
EXPRESSION (usb_mem_b_req & ((!usb_mem_b_write)))
------1------ ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T28,T29 |
| 1 | 1 | Covered | T29,T31,T32 |
LINE 834
EXPRESSION (gen_no_stubbed_memory.mem_rvalid & ((!gen_no_stubbed_memory.mem_rsteering)))
----------------1--------------- --------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T29,T31,T32 |
| 1 | 1 | Covered | T3,T29,T32 |
LINE 839
EXPRESSION (gen_no_stubbed_memory.mem_b_read_q ? gen_no_stubbed_memory.mem_rdata : gen_no_stubbed_memory.mem_b_rdata_q)
-----------------1----------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T29,T31,T32 |
LINE 902
SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
---------1--------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T207,T208,T209 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T207,T208,T209 |
LINE 1211
EXPRESSION (use_diff_rcvr & ((~link_suspend)))
------1------ --------2--------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T7,T18,T8 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 1220
EXPRESSION (usb_rcvr_ok_counter_q == '0)
--------------1--------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1224
EXPRESSION (use_diff_rcvr & ((!usb_rx_enable_o)))
------1------ ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T7,T18,T8 |
LINE 1226
EXPRESSION (us_tick && (usb_rcvr_ok_counter_q > '0))
---1--- --------------2-------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T203,T204,T205 |
LINE 1248
EXPRESSION (usb_ref_disable ? 1'b0 : event_sof)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T61,T210,T211 |
LINE 1255
EXPRESSION (usb_ref_pulse_o ? 1'b1 : ((((!link_active)) || host_lost || usb_ref_disable) ? 1'b0 : usb_ref_val_q))
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T41,T61,T8 |
LINE 1255
SUB-EXPRESSION ((((!link_active)) || host_lost || usb_ref_disable) ? 1'b0 : usb_ref_val_q)
-------------------------1------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1255
SUB-EXPRESSION (((!link_active)) || host_lost || usb_ref_disable)
--------1------- ----2---- -------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T61,T210,T211 |
| 0 | 1 | 0 | Covered | T66,T67,T68 |
| 1 | 0 | 0 | Covered | T1,T2,T3 |
LINE 1271
EXPRESSION (reg2hw.wake_control.suspend_req.qe & reg2hw.wake_control.suspend_req.q)
-----------------1---------------- ----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T7,T8,T9 |
| 1 | 0 | Covered | T7,T8,T9 |
| 1 | 1 | Covered | T7,T8,T9 |
LINE 1273
EXPRESSION (reg2hw.wake_control.wake_ack.qe & reg2hw.wake_control.wake_ack.q)
---------------1--------------- ---------------2--------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T7,T8,T9 |
| 1 | 0 | Covered | T7,T8,T9 |
| 1 | 1 | Covered | T7,T8,T9 |
LINE 1310
EXPRESSION (reg2hw.count_out.rst.qe & reg2hw.count_out.rst.q)
-----------1----------- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 1336
EXPRESSION (reg2hw.count_in.rst.qe & reg2hw.count_in.rst.q)
-----------1---------- ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 1359
EXPRESSION (reg2hw.count_nodata_in.rst.qe & reg2hw.count_nodata_in.rst.q)
--------------1-------------- --------------2-------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
LINE 1376
EXPRESSION (reg2hw.count_errors.rst.qe & reg2hw.count_errors.rst.q)
-------------1------------ ------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Not Covered | |
Toggle Coverage for Instance : tb.dut
| Total | Covered | Percent |
| Totals |
74 |
68 |
91.89 |
| Total Bits |
440 |
416 |
94.55 |
| Total Bits 0->1 |
220 |
208 |
94.55 |
| Total Bits 1->0 |
220 |
208 |
94.55 |
| | | |
| Ports |
74 |
68 |
91.89 |
| Port Bits |
440 |
416 |
94.55 |
| Port Bits 0->1 |
220 |
208 |
94.55 |
| Port Bits 1->0 |
220 |
208 |
94.55 |
Port Details
| Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
| clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| rst_ni |
Yes |
Yes |
T212,T167,T213 |
Yes |
T1,T2,T3 |
INPUT |
| clk_aon_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| rst_aon_ni |
Yes |
Yes |
T212,T167,T213 |
Yes |
T1,T2,T3 |
INPUT |
| tl_i.d_ready |
Yes |
Yes |
T2,T30,T43 |
Yes |
T1,T2,T3 |
INPUT |
| tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T2,T3,T42 |
Yes |
T2,T3,T42 |
INPUT |
| tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
| tl_i.a_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| tl_i.a_mask[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| tl_i.a_address[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| tl_i.a_source[7:0] |
Yes |
Yes |
T2,T3,T28 |
Yes |
T2,T3,T28 |
INPUT |
| tl_i.a_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
| tl_i.a_opcode[2:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| tl_i.a_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| tl_o.a_ready |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| tl_o.d_error |
Yes |
Yes |
T214,T215,T216 |
Yes |
T214,T215,T216 |
OUTPUT |
| tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| tl_o.d_user.rsp_intg[5:0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| tl_o.d_user.rsp_intg[6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
| tl_o.d_data[31:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T3,T28,T40 |
OUTPUT |
| tl_o.d_sink |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
| tl_o.d_source[7:0] |
Yes |
Yes |
T3,T28,T40 |
Yes |
T1,T3,T28 |
OUTPUT |
| tl_o.d_size[1:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
| tl_o.d_opcode[0] |
Yes |
Yes |
*T1,*T2,*T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
| tl_o.d_valid |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| alert_rx_i[0].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| alert_rx_i[0].ack_p |
Yes |
Yes |
T207,T212,T208 |
Yes |
T207,T212,T208 |
INPUT |
| alert_rx_i[0].ping_n |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
| alert_rx_i[0].ping_p |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
| alert_tx_o[0].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
| alert_tx_o[0].alert_p |
Yes |
Yes |
T207,T212,T208 |
Yes |
T207,T212,T208 |
OUTPUT |
| cio_usb_dp_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| cio_usb_dn_i |
Yes |
Yes |
T2,T3,T28 |
Yes |
T2,T3,T28 |
INPUT |
| usb_rx_d_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
| cio_usb_dp_o |
Yes |
Yes |
T3,T28,T29 |
Yes |
T3,T28,T29 |
OUTPUT |
| cio_usb_dp_en_o |
Yes |
Yes |
T3,T28,T29 |
Yes |
T3,T28,T29 |
OUTPUT |
| cio_usb_dn_o |
Yes |
Yes |
T3,T28,T29 |
Yes |
T3,T28,T29 |
OUTPUT |
| cio_usb_dn_en_o |
Yes |
Yes |
T3,T28,T29 |
Yes |
T3,T28,T29 |
OUTPUT |
| usb_tx_se0_o |
Yes |
Yes |
T3,T28,T29 |
Yes |
T3,T28,T29 |
OUTPUT |
| usb_tx_d_o |
Yes |
Yes |
T3,T28,T29 |
Yes |
T3,T28,T29 |
OUTPUT |
| cio_sense_i |
Yes |
Yes |
T41,T18,T8 |
Yes |
T1,T2,T3 |
INPUT |
| usb_dp_pullup_o |
Yes |
Yes |
T41,T7,T18 |
Yes |
T1,T2,T3 |
OUTPUT |
| usb_dn_pullup_o |
Yes |
Yes |
T14,T97,T217 |
Yes |
T49,T52,T206 |
OUTPUT |
| usb_rx_enable_o |
Yes |
Yes |
T7,T18,T8 |
Yes |
T1,T2,T3 |
OUTPUT |
| usb_tx_use_d_se0_o |
Yes |
Yes |
T167,T218,T219 |
Yes |
T162,T110,T220 |
OUTPUT |
| usb_aon_suspend_req_o |
Yes |
Yes |
T7,T8,T9 |
Yes |
T7,T8,T9 |
OUTPUT |
| usb_aon_wake_ack_o |
Yes |
Yes |
T7,T8,T9 |
Yes |
T7,T8,T9 |
OUTPUT |
| usb_aon_bus_reset_i |
Yes |
Yes |
T7,T10,T14 |
Yes |
T7,T10,T14 |
INPUT |
| usb_aon_sense_lost_i |
Yes |
Yes |
T8,T11,T13 |
Yes |
T8,T11,T13 |
INPUT |
| usb_aon_bus_not_idle_i |
Yes |
Yes |
T7,T9,T10 |
Yes |
T7,T9,T10 |
INPUT |
| usb_aon_wake_detect_active_i |
Yes |
Yes |
T7,T8,T9 |
Yes |
T7,T8,T9 |
INPUT |
| usb_ref_val_o |
Yes |
Yes |
T41,T61,T8 |
Yes |
T41,T61,T8 |
OUTPUT |
| usb_ref_pulse_o |
Yes |
Yes |
T41,T61,T8 |
Yes |
T41,T61,T8 |
OUTPUT |
| ram_cfg_i.rf_cfg.cfg[3:0] |
No |
No |
|
No |
|
INPUT |
| ram_cfg_i.rf_cfg.cfg_en |
No |
No |
|
No |
|
INPUT |
| ram_cfg_i.rf_cfg.test |
No |
No |
|
No |
|
INPUT |
| ram_cfg_i.ram_cfg.cfg[3:0] |
No |
No |
|
No |
|
INPUT |
| ram_cfg_i.ram_cfg.cfg_en |
No |
No |
|
No |
|
INPUT |
| ram_cfg_i.ram_cfg.test |
No |
No |
|
No |
|
INPUT |
| intr_pkt_received_o |
Yes |
Yes |
T49,T51,T52 |
Yes |
T49,T51,T52 |
OUTPUT |
| intr_pkt_sent_o |
Yes |
Yes |
T33,T35,T17 |
Yes |
T33,T35,T17 |
OUTPUT |
| intr_powered_o |
Yes |
Yes |
T221,T222,T223 |
Yes |
T221,T222,T223 |
OUTPUT |
| intr_disconnected_o |
Yes |
Yes |
T41,T64,T65 |
Yes |
T41,T64,T65 |
OUTPUT |
| intr_host_lost_o |
Yes |
Yes |
T66,T221,T222 |
Yes |
T66,T221,T222 |
OUTPUT |
| intr_link_reset_o |
Yes |
Yes |
T50,T221,T223 |
Yes |
T50,T221,T223 |
OUTPUT |
| intr_link_suspend_o |
Yes |
Yes |
T221,T223,T224 |
Yes |
T221,T223,T224 |
OUTPUT |
| intr_link_resume_o |
Yes |
Yes |
T20,T69,T70 |
Yes |
T20,T69,T70 |
OUTPUT |
| intr_av_out_empty_o |
Yes |
Yes |
T53,T221,T223 |
Yes |
T53,T221,T223 |
OUTPUT |
| intr_rx_full_o |
Yes |
Yes |
T21,T56,T57 |
Yes |
T21,T56,T57 |
OUTPUT |
| intr_av_overflow_o |
Yes |
Yes |
T1,T62,T63 |
Yes |
T1,T62,T63 |
OUTPUT |
| intr_link_in_err_o |
Yes |
Yes |
T221,T223,T224 |
Yes |
T221,T223,T224 |
OUTPUT |
| intr_link_out_err_o |
Yes |
Yes |
T37,T39,T71 |
Yes |
T37,T39,T71 |
OUTPUT |
| intr_rx_crc_err_o |
Yes |
Yes |
T19,T73,T74 |
Yes |
T19,T73,T74 |
OUTPUT |
| intr_rx_pid_err_o |
Yes |
Yes |
T23,T75,T77 |
Yes |
T23,T75,T77 |
OUTPUT |
| intr_rx_bitstuff_err_o |
Yes |
Yes |
T2,T80,T81 |
Yes |
T2,T80,T81 |
OUTPUT |
| intr_frame_o |
Yes |
Yes |
T221,T223,T224 |
Yes |
T221,T223,T224 |
OUTPUT |
| intr_av_setup_empty_o |
Yes |
Yes |
T28,T24,T59 |
Yes |
T28,T24,T59 |
OUTPUT |
*Tests covering at least one bit in the range
Branch Coverage for Instance : tb.dut
| Line No. | Total | Covered | Percent |
| Branches |
|
48 |
48 |
100.00 |
| TERNARY |
442 |
2 |
2 |
100.00 |
| TERNARY |
443 |
2 |
2 |
100.00 |
| TERNARY |
560 |
2 |
2 |
100.00 |
| TERNARY |
561 |
2 |
2 |
100.00 |
| TERNARY |
1248 |
2 |
2 |
100.00 |
| TERNARY |
1255 |
3 |
3 |
100.00 |
| TERNARY |
801 |
2 |
2 |
100.00 |
| TERNARY |
802 |
2 |
2 |
100.00 |
| TERNARY |
803 |
2 |
2 |
100.00 |
| TERNARY |
839 |
2 |
2 |
100.00 |
| IF |
222 |
3 |
3 |
100.00 |
| IF |
434 |
2 |
2 |
100.00 |
| IF |
465 |
2 |
2 |
100.00 |
| IF |
493 |
2 |
2 |
100.00 |
| IF |
508 |
4 |
4 |
100.00 |
| IF |
526 |
2 |
2 |
100.00 |
| IF |
718 |
2 |
2 |
100.00 |
| IF |
1224 |
3 |
3 |
100.00 |
| IF |
1232 |
2 |
2 |
100.00 |
| IF |
1259 |
2 |
2 |
100.00 |
| IF |
820 |
3 |
3 |
100.00 |
442 assign in_buf_d = in_xact_starting ? in_buf[in_xact_start_ep] : in_buf_q;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T29,T31,T32 |
| 0 |
Covered |
T1,T2,T3 |
443 assign in_size_d = in_xact_starting ? in_size[in_xact_start_ep] : in_size_q;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T29,T31,T32 |
| 0 |
Covered |
T1,T2,T3 |
560 assign usb_dp_pullup_en = cfg_pinflip ? 1'b0 : usb_pullup_en;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T49,T52,T206 |
| 0 |
Covered |
T1,T2,T3 |
561 assign usb_dn_pullup_en = !cfg_pinflip ? 1'b0 : usb_pullup_en;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T49,T52,T206 |
1248 assign usb_ref_pulse_o = usb_ref_disable ? 1'b0 : event_sof;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T61,T210,T211 |
| 0 |
Covered |
T1,T2,T3 |
1255 assign usb_ref_val_d = usb_ref_pulse_o ? 1'b1 :
-1-
==>
1256 (!link_active || host_lost || usb_ref_disable) ? 1'b0 : usb_ref_val_q;
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T41,T61,T8 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
801 assign mem_write = usb_mem_b_req ? usb_mem_b_write : sw_mem_a_write;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T3,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
802 assign mem_addr = usb_mem_b_req ? usb_mem_b_addr : sw_mem_a_addr;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T3,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
803 assign mem_wdata = usb_mem_b_req ? usb_mem_b_wdata : sw_mem_a_wdata;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T3,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
839 assign usb_mem_b_rdata = mem_b_read_q ? mem_rdata : mem_b_rdata_q;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T29,T31,T32 |
| 0 |
Covered |
T1,T2,T3 |
222 if (!rst_n) begin
-1-
223 ns_cnt <= '0;
==>
224 end else begin
225 if (us_tick) begin
-2-
226 ns_cnt <= '0;
==>
227 end else begin
228 ns_cnt <= ns_cnt + 1'b1;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
434 if (!rst_n) begin
-1-
435 in_buf_q <= '0;
==>
436 in_size_q <= '0;
437 end else begin
438 in_buf_q <= in_buf_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
465 if (in_ep_xact_end && in_endpoint_val) begin
-1-
466 set_sentbit[in_endpoint] = 1'b1;
==>
467 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T29,T32,T33 |
| 0 |
Covered |
T1,T2,T3 |
493 if (rx_wvalid && out_endpoint_val) begin
-1-
494 clear_rxenable_out[out_endpoint] = ep_set_nak_on_out[out_endpoint];
==>
495 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T3,T28,T29 |
| 0 |
Covered |
T1,T2,T3 |
508 if (event_link_reset) begin
-1-
509 clear_rdybit = {NEndpoints{1'b1}};
==>
510 update_pend = {NEndpoints{1'b1}};
511 end else begin
512 if (setup_received & out_endpoint_val) begin
-2-
513 // Clear pending when a SETUP is received
514 clear_rdybit[out_endpoint] = 1'b1;
==>
515 update_pend[out_endpoint] = 1'b1;
516 end else if (in_ep_xact_end & in_endpoint_val) begin
-3-
517 // Clear rdy and sending when an IN transmission was successful
518 clear_rdybit[in_endpoint] = 1'b1;
==>
519 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T3,T28,T30 |
| 0 |
0 |
1 |
Covered |
T29,T32,T33 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
526 if (in_xact_starting) set_sending[in_xact_start_ep] = 1'b1;
-1-
==>
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T29,T31,T32 |
| 0 |
Covered |
T1,T2,T3 |
718 if (setup_received && out_endpoint_val && out_endpoint == 4'(unsigned'(i))) begin
-1-
719 hw2reg.out_stall[i].de = 1'b1;
==>
720 hw2reg.in_stall[i].de = 1'b1;
721 end else begin
722 hw2reg.out_stall[i].de = 1'b0;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T3,T28,T30 |
| 0 |
Covered |
T1,T2,T3 |
1224 if (use_diff_rcvr & !usb_rx_enable_o) begin
-1-
1225 usb_rcvr_ok_counter_d = RcvrWakeTimeWidth'(RcvrWakeTimeUs + 1);
==>
1226 end else if (us_tick && (usb_rcvr_ok_counter_q > '0)) begin
-2-
1227 usb_rcvr_ok_counter_d = usb_rcvr_ok_counter_q - 1;
==>
1228 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T7,T18,T8 |
| 0 |
1 |
Covered |
T203,T204,T205 |
| 0 |
0 |
Covered |
T1,T2,T3 |
1232 if (!rst_n) begin
-1-
1233 usb_rcvr_ok_counter_q <= RcvrWakeTimeWidth'(RcvrWakeTimeUs + 1);
==>
1234 end else begin
1235 usb_rcvr_ok_counter_q <= usb_rcvr_ok_counter_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
1259 if (!rst_n) begin
-1-
1260 usb_ref_val_q <= 1'b0;
==>
1261 end else begin
1262 usb_ref_val_q <= usb_ref_val_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
820 if (!rst_ni) begin
-1-
821 mem_rsteering <= 1'b0;
==>
822 mem_b_read_q <= 1'b0;
823 mem_b_rdata_q <= {SramDw{1'b0}};
824 end else begin
825 mem_rsteering <= usb_mem_b_req;
826 mem_b_read_q <= usb_mem_b_req & !usb_mem_b_write;
827 // Capture the `usb` read data.
828 if (mem_b_read_q)
-2-
829 mem_b_rdata_q <= mem_rdata;
==>
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T29,T31,T32 |
| 0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut
Assertion Details
AlertsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
CIODnEnKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
CIODnKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
CIODpEnKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
CIODpKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
FpvSecCmRegWeOnehotCheck_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
70 |
0 |
0 |
| T5 |
78155 |
0 |
0 |
0 |
| T6 |
93188 |
0 |
0 |
0 |
| T62 |
6774 |
0 |
0 |
0 |
| T64 |
6563 |
0 |
0 |
0 |
| T80 |
10645 |
0 |
0 |
0 |
| T109 |
29672 |
0 |
0 |
0 |
| T110 |
23113 |
0 |
0 |
0 |
| T212 |
23969 |
20 |
0 |
0 |
| T213 |
0 |
10 |
0 |
0 |
| T225 |
0 |
10 |
0 |
0 |
| T226 |
0 |
20 |
0 |
0 |
| T227 |
0 |
10 |
0 |
0 |
| T228 |
7672 |
0 |
0 |
0 |
| T229 |
1531 |
0 |
0 |
0 |
TlOAReadyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
TlODValidKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBAonSuspendReqKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBAonWakeAckKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBDnPUKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBDpPUKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBIntrAvOutEmptyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBIntrAvOverKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBIntrAvSetupEmptyKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBIntrDisConKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBIntrFrameKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBIntrHostLostKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBIntrLinkInErrKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBIntrLinkOutErrKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBIntrLinkResKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBIntrLinkRstKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBIntrLinkSusKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBIntrPktRcvdKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBIntrPktSentKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBIntrPwrdKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBIntrRxBitstuffErrKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBIntrRxCrCErrKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBIntrRxFullKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBIntrRxPidErrKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBRefPulseKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBRefValKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBRxEnableKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBTxDKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
USBTxSe0Known_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
586533067 |
586232617 |
0 |
0 |
| T1 |
6313 |
6244 |
0 |
0 |
| T2 |
8483 |
8429 |
0 |
0 |
| T3 |
10220 |
10144 |
0 |
0 |
| T28 |
8434 |
8382 |
0 |
0 |
| T29 |
19184 |
19133 |
0 |
0 |
| T30 |
12616 |
12552 |
0 |
0 |
| T40 |
2350 |
2274 |
0 |
0 |
| T41 |
6622 |
6558 |
0 |
0 |
| T42 |
16481 |
16406 |
0 |
0 |
| T43 |
55030 |
54950 |
0 |
0 |
