Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9768032	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

10329546

1

T1

7

T2

17

T3

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	19450571	1			T1	10		T2	15		T3	7
values[0x0]	323273	1			T1	4		T2	5		T3	9
values[0x1]	323734	1			T1	6		T2	2		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7764558	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

12333020

1

T1

10

T2

17

T3

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	61092	1			T31	1		T36	3		T38	21
valid_sources[0x01]	62874	1			T3	1		T38	2		T49	3
valid_sources[0x02]	71077	1			T36	4		T38	8		T7	1
valid_sources[0x03]	60280	1			T3	1		T36	1		T38	7
valid_sources[0x04]	59402	1			T38	19		T49	2		T52	4
valid_sources[0x05]	135811	1			T36	8		T38	13		T205	1
valid_sources[0x06]	59184	1			T36	3		T38	13		T92	1
valid_sources[0x07]	60332	1			T88	1		T37	1		T38	9
valid_sources[0x08]	59907	1			T32	1		T88	2		T34	1
valid_sources[0x09]	82725	1			T88	1		T36	4		T38	15
valid_sources[0x0a]	61053	1			T36	4		T38	22		T49	3
valid_sources[0x0b]	59132	1			T36	4		T38	10		T49	1
valid_sources[0x0c]	78439	1			T30	1		T36	9		T38	8
valid_sources[0x0d]	85534	1			T36	26		T37	1		T38	17
valid_sources[0x0e]	165929	1			T36	8		T38	19		T20	1
valid_sources[0x0f]	97981	1			T38	22		T49	1		T20	1
valid_sources[0x10]	127554	1			T36	5		T37	1		T38	14
valid_sources[0x11]	75242	1			T32	3		T35	2		T36	2
valid_sources[0x12]	91867	1			T36	3		T38	12		T49	1
valid_sources[0x13]	59668	1			T36	1		T38	3		T51	12
valid_sources[0x14]	59620	1			T2	2		T38	2		T51	3
valid_sources[0x15]	71187	1			T36	7		T38	14		T49	1
valid_sources[0x16]	59992	1			T38	8		T25	1		T51	7
valid_sources[0x17]	157433	1			T34	1		T37	1		T38	7
valid_sources[0x18]	60764	1			T41	2		T36	4		T38	5
valid_sources[0x19]	152662	1			T30	2		T38	7		T49	3
valid_sources[0x1a]	60686	1			T32	1		T34	1		T38	22
valid_sources[0x1b]	60894	1			T32	1		T36	1		T38	7
valid_sources[0x1c]	81034	1			T2	4		T88	1		T36	8
valid_sources[0x1d]	121436	1			T3	1		T36	6		T38	16
valid_sources[0x1e]	60762	1			T1	1		T41	2		T32	3
valid_sources[0x1f]	60118	1			T40	7		T88	1		T36	3
valid_sources[0x20]	62751	1			T36	2		T38	8		T49	1
valid_sources[0x21]	60124	1			T1	3		T37	4		T38	25
valid_sources[0x22]	60864	1			T36	2		T38	12		T51	4
valid_sources[0x23]	59406	1			T88	1		T36	2		T38	19
valid_sources[0x24]	59130	1			T36	15		T38	6		T49	2
valid_sources[0x25]	60037	1			T3	2		T33	13		T36	4
valid_sources[0x26]	60893	1			T38	12		T49	2		T157	1
valid_sources[0x27]	79628	1			T34	1		T36	1		T38	8
valid_sources[0x28]	60493	1			T36	15		T38	15		T49	2
valid_sources[0x29]	60512	1			T1	1		T36	2		T38	3
valid_sources[0x2a]	60375	1			T38	22		T7	12		T19	1
valid_sources[0x2b]	59979	1			T31	1		T34	1		T38	10
valid_sources[0x2c]	78463	1			T39	12		T30	1		T38	7
valid_sources[0x2d]	159357	1			T36	2		T38	17		T49	2
valid_sources[0x2e]	59913	1			T32	1		T36	5		T38	14
valid_sources[0x2f]	159384	1			T36	11		T38	26		T49	1
valid_sources[0x30]	58331	1			T88	1		T36	7		T38	25
valid_sources[0x31]	97320	1			T88	1		T36	5		T38	12
valid_sources[0x32]	123636	1			T36	2		T38	12		T49	2
valid_sources[0x33]	115621	1			T2	3		T34	1		T36	8
valid_sources[0x34]	60065	1			T3	1		T38	5		T214	3
valid_sources[0x35]	60231	1			T38	9		T7	2		T18	3
valid_sources[0x36]	60169	1			T36	1		T38	9		T49	4
valid_sources[0x37]	59502	1			T38	14		T49	1		T7	1
valid_sources[0x38]	89683	1			T38	19		T49	1		T7	1
valid_sources[0x39]	83587	1			T36	3		T38	9		T49	3
valid_sources[0x3a]	95981	1			T36	3		T38	5		T25	2
valid_sources[0x3b]	60689	1			T36	1		T38	6		T51	3
valid_sources[0x3c]	95155	1			T34	1		T36	2		T38	10
valid_sources[0x3d]	60324	1			T32	2		T36	6		T38	3
valid_sources[0x3e]	160973	1			T38	9		T18	1		T51	4
valid_sources[0x3f]	59983	1			T34	1		T36	2		T38	13
valid_sources[0x40]	60194	1			T38	7		T49	1		T18	1
valid_sources[0x41]	62057	1			T34	1		T38	17		T51	4
valid_sources[0x42]	79362	1			T88	3		T36	14		T38	9
valid_sources[0x43]	59622	1			T34	1		T36	9		T38	13
valid_sources[0x44]	60251	1			T41	3		T32	1		T36	1
valid_sources[0x45]	68543	1			T36	4		T38	17		T49	2
valid_sources[0x46]	85195	1			T88	1		T36	3		T38	16
valid_sources[0x47]	59825	1			T30	1		T36	10		T38	8
valid_sources[0x48]	60547	1			T28	163		T36	11		T38	19
valid_sources[0x49]	59188	1			T88	3		T38	14		T7	1
valid_sources[0x4a]	61948	1			T36	2		T38	10		T89	1
valid_sources[0x4b]	85878	1			T36	6		T38	10		T49	1
valid_sources[0x4c]	61101	1			T3	2		T36	1		T38	15
valid_sources[0x4d]	70150	1			T36	2		T37	1		T38	8
valid_sources[0x4e]	59126	1			T36	5		T38	9		T49	3
valid_sources[0x4f]	183653	1			T88	5		T36	2		T38	8
valid_sources[0x50]	60349	1			T36	4		T38	11		T49	1
valid_sources[0x51]	268380	1			T31	2		T88	4		T37	4
valid_sources[0x52]	61890	1			T36	3		T38	6		T49	2
valid_sources[0x53]	60093	1			T36	9		T38	13		T20	1
valid_sources[0x54]	59997	1			T32	5		T87	12		T36	4
valid_sources[0x55]	117178	1			T30	2		T32	1		T36	9
valid_sources[0x56]	120656	1			T35	2		T36	8		T38	8
valid_sources[0x57]	58943	1			T36	4		T37	1		T38	2
valid_sources[0x58]	80752	1			T38	17		T49	1		T24	2
valid_sources[0x59]	60461	1			T34	1		T36	1		T37	1
valid_sources[0x5a]	98515	1			T88	1		T36	10		T38	11
valid_sources[0x5b]	96846	1			T36	2		T38	16		T49	2
valid_sources[0x5c]	80166	1			T41	1		T36	17		T38	10
valid_sources[0x5d]	69997	1			T88	2		T36	2		T38	3
valid_sources[0x5e]	60577	1			T88	2		T36	3		T38	11
valid_sources[0x5f]	78313	1			T36	2		T38	12		T7	3
valid_sources[0x60]	60362	1			T36	2		T37	1		T38	13
valid_sources[0x61]	59975	1			T2	2		T38	13		T49	1
valid_sources[0x62]	67512	1			T36	2		T38	7		T18	2
valid_sources[0x63]	72980	1			T2	1		T3	1		T32	1
valid_sources[0x64]	140189	1			T36	1		T38	15		T49	1
valid_sources[0x65]	58892	1			T36	5		T38	25		T49	1
valid_sources[0x66]	60313	1			T36	4		T38	16		T51	7
valid_sources[0x67]	171027	1			T30	1		T38	12		T7	10
valid_sources[0x68]	87995	1			T36	2		T38	12		T49	2
valid_sources[0x69]	59096	1			T2	4		T36	1		T37	2
valid_sources[0x6a]	58612	1			T36	5		T38	11		T7	2
valid_sources[0x6b]	59994	1			T36	2		T38	13		T22	2
valid_sources[0x6c]	60780	1			T88	2		T34	2		T36	4
valid_sources[0x6d]	62456	1			T38	3		T49	1		T18	1
valid_sources[0x6e]	59300	1			T31	2		T36	7		T38	19
valid_sources[0x6f]	60501	1			T36	1		T38	8		T49	2
valid_sources[0x70]	60676	1			T34	1		T36	5		T38	15
valid_sources[0x71]	95532	1			T38	17		T18	2		T51	3
valid_sources[0x72]	59954	1			T38	10		T49	3		T7	1
valid_sources[0x73]	77556	1			T38	23		T49	3		T24	1
valid_sources[0x74]	79082	1			T32	3		T88	1		T36	10
valid_sources[0x75]	60213	1			T36	2		T37	3		T38	9
valid_sources[0x76]	61711	1			T36	11		T38	15		T205	1
valid_sources[0x77]	60335	1			T36	1		T38	11		T49	2
valid_sources[0x78]	59446	1			T36	13		T38	7		T7	2
valid_sources[0x79]	60374	1			T88	1		T36	3		T38	8
valid_sources[0x7a]	60089	1			T36	3		T38	8		T49	1
valid_sources[0x7b]	58624	1			T1	4		T36	7		T37	2
valid_sources[0x7c]	60226	1			T36	2		T38	13		T7	1
valid_sources[0x7d]	155069	1			T36	1		T38	11		T51	10
valid_sources[0x7e]	70619	1			T41	1		T88	3		T36	3
valid_sources[0x7f]	61271	1			T32	1		T38	3		T18	2
valid_sources[0x80]	87240	1			T36	5		T38	11		T49	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9807529

1

T1

1

T2

12

T3

1

values[0x0]

all_enables

biggest_size

269818

1

T1

3

T2

4

T3

3

values[0x1]

all_enables

biggest_size

252199

1

T1

3

T2

1

T3

1