Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

9781577

1

T1

13

T2

5

T3

17

full_word

10330482

1

T1

7

T2

17

T3

5

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	20111799	1			T1	20		T2	22		T3	22
auto[TlIntgErrCmd]	78	1			T253	5		T261	3		T262	3
auto[TlIntgErrData]	102	1			T253	9		T261	4		T262	3
auto[TlIntgErrBoth]	80	1			T253	6		T261	3		T262	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19452267

1

T1

10

T2

15

T3

7

auto[1]

659792

1

T1

10

T2

7

T3

15

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	9644462	1			T1	9		T2	3		T3	6
auto[TlIntgErrNone]	partial	auto[1]	136876	1			T1	4		T2	2		T3	11
auto[TlIntgErrNone]	full_word	auto[0]	9807694	1			T1	1		T2	12		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	522767	1			T1	6		T2	5		T3	4
auto[TlIntgErrCmd]	partial	auto[0]	32	1			T253	4		T261	1		T262	2
auto[TlIntgErrCmd]	partial	auto[1]	43	1			T253	1		T261	2		T262	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T314	1		T589	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	1	1			T590	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	43	1			T253	4		T261	1		T279	4
auto[TlIntgErrData]	partial	auto[1]	47	1			T253	4		T261	3		T262	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T262	1		T591	1		T587	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T253	1		T262	1		T275	2
auto[TlIntgErrBoth]	partial	auto[0]	28	1			T253	2		T261	3		T262	2
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T253	4		T262	2		T279	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T592	1		T593	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T279	1		T314	1		T591	1