Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.99	97.53	92.86	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	588873310	11206	0	0
ep_in_enable_rd_A	588873310	2282	0	0
ep_out_enable_rd_A	588873310	2427	0	0
in_iso_rd_A	588873310	2322	0	0
intr_enable_rd_A	588873310	3235	0	0
out_iso_rd_A	588873310	2264	0	0
phy_config_rd_A	588873310	1655	0	0
phy_pins_drive_rd_A	588873310	2027	0	0
rxenable_setup_rd_A	588873310	2551	0	0
set_nak_out_rd_A	588873310	2536	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588873310	11206	0	0
T228	6601	19	0	0
T229	4583	317	0	0
T230	13904	748	0	0
T253	26493	4	0	0
T261	37214	3	0	0
T262	15585	1	0	0
T263	5472	446	0	0
T268	4341	291	0	0
T277	6273	17	0	0
T278	4452	11	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588873310	2282	0	0
T261	37214	192	0	0
T272	11251	50	0	0
T279	19851	256	0	0
T293	2865	4	0	0
T298	10110	110	0	0
T310	54667	211	0	0
T311	79468	111	0	0
T312	42469	132	0	0
T313	4070	1	0	0
T314	28456	150	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588873310	2427	0	0
T261	37214	87	0	0
T272	11251	10	0	0
T279	19851	320	0	0
T280	4586	3	0	0
T293	2865	8	0	0
T298	10110	85	0	0
T310	54667	242	0	0
T311	79468	115	0	0
T312	42469	134	0	0
T314	28456	109	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588873310	2322	0	0
T230	13904	9	0	0
T261	37214	74	0	0
T272	11251	121	0	0
T279	19851	195	0	0
T280	4586	4	0	0
T298	10110	127	0	0
T310	54667	222	0	0
T311	79468	136	0	0
T312	42469	106	0	0
T314	28456	247	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588873310	3235	0	0
T261	37214	169	0	0
T279	19851	260	0	0
T280	4586	37	0	0
T293	2865	8	0	0
T298	10110	91	0	0
T310	54667	196	0	0
T311	79468	149	0	0
T312	42469	135	0	0
T313	4070	4	0	0
T315	3237	8	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588873310	2264	0	0
T261	37214	67	0	0
T272	11251	25	0	0
T279	19851	275	0	0
T280	4586	33	0	0
T293	2865	5	0	0
T298	10110	116	0	0
T310	54667	235	0	0
T311	79468	172	0	0
T312	42469	120	0	0
T314	28456	139	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588873310	1655	0	0
T261	37214	69	0	0
T272	11251	68	0	0
T279	19851	199	0	0
T280	4586	1	0	0
T298	10110	102	0	0
T310	54667	190	0	0
T311	79468	171	0	0
T312	42469	106	0	0
T314	28456	140	0	0
T316	4250	31	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588873310	2027	0	0
T261	37214	106	0	0
T272	11251	14	0	0
T279	19851	245	0	0
T293	2865	8	0	0
T298	10110	80	0	0
T310	54667	220	0	0
T311	79468	143	0	0
T312	42469	123	0	0
T314	28456	196	0	0
T316	4250	9	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588873310	2551	0	0
T230	13904	5	0	0
T261	37214	77	0	0
T279	19851	240	0	0
T280	4586	7	0	0
T293	2865	5	0	0
T298	10110	117	0	0
T310	54667	221	0	0
T311	79468	103	0	0
T312	42469	157	0	0
T313	4070	28	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	588873310	2536	0	0
T261	37214	143	0	0
T272	11251	70	0	0
T279	19851	185	0	0
T280	4586	2	0	0
T298	10110	120	0	0
T310	54667	204	0	0
T311	79468	149	0	0
T312	42469	167	0	0
T313	4070	14	0	0
T314	28456	148	0	0