Unified Coverage Report :: Module :: tlul_adapter_sram

Module : tlul_adapter_sram

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.37	98.55	78.63			92.31	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_no_stubbed_memory.u_tlul2sram	92.37	98.55	78.63			92.31	100.00

---

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.37	98.55	78.63			92.31	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.91	86.78	75.75			81.11	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
89.84	93.83	70.15	93.58		91.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_err	67.62	76.92	68.57			25.00	100.00
u_reqfifo	88.33	95.00	75.00			83.33	100.00
u_rsp_gen	91.67	83.33					100.00
u_rspfifo	89.32	95.00	77.27			85.00	100.00
u_sram_byte	100.00	100.00
u_sramreqfifo	87.64	95.00	72.22			83.33	100.00
u_tlul_data_integ_enc_data	0.00	0.00
u_tlul_data_integ_enc_instr	0.00	0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : tlul_adapter_sram

	Line No.	Total	Covered	Percent
TOTAL		69	68	98.55
ALWAYS	94	3	3	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	226	1	1	100.00
ALWAYS	231	8	7	87.50
ALWAYS	251	6	6	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	288	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
CONT_ASSIGN	311	1	1	100.00
ALWAYS	314	3	3	100.00
CONT_ASSIGN	321	1	1	100.00
CONT_ASSIGN	341	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	343	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
ALWAYS	374	6	6	100.00
ALWAYS	386	5	5	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	402	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	407	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	426	1	1	100.00
CONT_ASSIGN	428	1	1	100.00
CONT_ASSIGN	435	1	1	100.00
ALWAYS	453	3	3	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	462	1	1	100.00
CONT_ASSIGN	467	1	1	100.00
CONT_ASSIGN	472	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
95	1	1
96	1	1
97		unreachable
			MISSING_ELSE
103	1	1
108	1	1
115	1	1
140	1	1
152	1	1
224	1	1
225	1	1
226	1	1
231	1	1
233	1	1
234	1	1
236	0	1
237	1	1
238	1	1
241	1	1
244	1	1
251	1	1
253	1	1
254	1	1
255	1	1
257	1	1
260	1	1
265	1	1
269	1	1
288	1	1
293	1	1
299	1	1
311	1	1
314	1	1
315	1	1
317	1	1
321	1	1
341	1	1
342	1	1
343	1	1
344	1	1
374	1	1
375	1	1
377	1	1
378	1	1
379	1	1
380	1	1
			MISSING_ELSE
386	1	1
387	1	1
389	1	1
390	1	1
391	1	1
			MISSING_ELSE
401	1	1
402	1	1
403	1	1
407	1	1
408	1	1
410	1	1
411	1	1
418	1	1
421	1	1
425	1	1
426	1	1
428	1	1
435	1	1
453	1	1
454	1	1
455	1	1
459	1	1
462	1	1
467	1	1
472		unreachable

---

Cond Coverage for Module : tlul_adapter_sram

	Total	Covered	Percent
Conditions	117	92	78.63
Logical	117	92	78.63
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Unreachable
1	0	Unreachable

 LINE       103
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T2,T3,T4
0	0	1	Not Covered
0	1	0	Unreachable
1	0	0	Unreachable

 LINE       108
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       108
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       108
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T2,T19,T21
1	0	Covered	T2,T3,T4

 LINE       108
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       108
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       140
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T2,T4,T17
0	0	0	0	0	1	Unreachable
0	0	0	0	1	0	Covered	T2,T3,T4
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Unreachable
0	1	0	0	0	0	Unreachable
1	0	0	0	0	0	Not Covered

 LINE       224
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T4,T17
1	1	Covered	T2,T4,T17

 LINE       225
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T17,T19
1	1	Covered	T2,T4,T17

 LINE       226
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T15,T16,T114
1	1	Covered	T2,T4,T17

 LINE       237
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T19,T15
1	Covered	T2,T4,T17

 LINE       254
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T19,T15
1	Covered	T2,T4,T17

 LINE       255
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T17
0	1	Not Covered
1	0	Not Covered

 LINE       265
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Covered	T2,T4,T17

 LINE       265
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T4,T17

 LINE       293
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T4,T17

 LINE       293
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T4,T17

 LINE       299
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T17
1	1	Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T4,T17

 LINE       311
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T4,T17
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       321
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T4,T19,T15

 LINE       321
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T4,T17
1	1	Covered	T4,T19,T15

 LINE       321
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       321
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T4,T17

 LINE       321
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T4,T17

 LINE       321
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T17
1	1	Not Covered

 LINE       321
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready)
             -------------1------------   -------2------   ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T4
1	0	1	Covered	T4,T17,T19
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       321
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Not Covered
1	0	Covered	T2,T3,T4

 LINE       341
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T4,T17
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T17

 LINE       343
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T4,T17
1	1	Covered	T4,T19,T15

 LINE       344
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T4,T17

 LINE       380
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Covered	T2,T4,T17
1	Covered	T4,T19,T15

 LINE       380
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T4,T17
1	1	Covered	T4,T19,T15

 LINE       403
 EXPRESSION (((|wmask_intg)) & ((|wdata_intg)))
             -------1-------   -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T17,T106
1	1	Covered	T2,T4,T17

 LINE       411
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       411
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       425
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T4,T19,T15
1	1	Covered	T2,T4,T17

 LINE       428
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T17,T19
1	0	Not Covered
1	1	Covered	T2,T4,T17

 LINE       467
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T4,T17

 LINE       467
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Not Covered
1	1	Covered	T2,T4,T17

 LINE       467
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T4,T17

---

Branch Coverage for Module : tlul_adapter_sram

	Line No.	Total	Covered	Percent
Branches		26	24	92.31
TERNARY	108	2	2	100.00
TERNARY	293	2	2	100.00
TERNARY	299	3	2	66.67
TERNARY	344	2	2	100.00
TERNARY	467	2	2	100.00
IF	94	2	2	100.00
IF	233	4	3	75.00
IF	253	3	3	100.00
IF	314	2	2	100.00
IF	377	2	2	100.00
IF	389	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	108	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	293	((vld_rd_rsp & (~d_error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T17
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	299	((vld_rd_rsp && reqfifo_rdata.error)) ? 
-2-:	299	(vld_rd_rsp) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T2,T4,T17
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	344	(tl_i_int.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T17
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	467	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T17
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	94	if ((!rst_ni))
-2-:	96	if ((intg_error || rsp_fifo_error))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Unreachable
0	0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	233	if (reqfifo_rvalid)
-2-:	234	if (reqfifo_rdata.error)
-3-:	237	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Not Covered
1	0	1	Covered	T2,T4,T17
1	0	0	Covered	T4,T19,T15
0	-	-	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	253	if (reqfifo_rvalid)
-2-:	254	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T4,T17
1	0	Covered	T4,T19,T15
0	-	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	314	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	377	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T17
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	389	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T17
0	Covered	T2,T3,T4

---

Assert Coverage for Module : tlul_adapter_sram

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrOutKnown_A	724486299	724355018	0	0
DataIntgOptions_A	1693	1693	0	0
ReqOutKnown_A	724486299	724355018	0	0
SramDwHasByteGranularity_A	1693	1693	0	0
SramDwIsMultipleOfTlulWidth_A	1693	1693	0	0
TlOutKnownIfFifoKnown_A	724486299	724355018	0	0
TlOutValidKnown_A	724486299	724355018	0	0
WdataOutKnown_A	724486299	724355018	0	0
WeOutKnown_A	724486299	724355018	0	0
WmaskOutKnown_A	724486299	724355018	0	0
adapterNoReadOrWrite	1693	1693	0	0
rvalidHighReqFifoEmpty	724486299	198099	0	0
rvalidHighWhenRspFifoFull	724486299	198099	0	0

AddrOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724486299	724355018	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

DataIntgOptions_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1693	1693	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

ReqOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724486299	724355018	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

SramDwHasByteGranularity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1693	1693	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

SramDwIsMultipleOfTlulWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1693	1693	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

TlOutKnownIfFifoKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724486299	724355018	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

TlOutValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724486299	724355018	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

WdataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724486299	724355018	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

WeOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724486299	724355018	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

WmaskOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	724486299	724355018	0	0
T2	403840	403767	0	0
T3	402866	402788	0	0
T4	956550	956492	0	0
T5	554152	554092	0	0
T17	413886	413835	0	0
T18	408275	408217	0	0
T19	405467	405415	0	0
T20	403721	403628	0	0
T21	401860	401763	0	0
T22	406112	406058	0	0

adapterNoReadOrWrite

Name	Attempts	Real Successes	Failures	Incomplete
Total	1693	1693	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

rvalidHighReqFifoEmpty

Name	Attempts	Real Successes	Failures	Incomplete
Total	724486299	198099	0	0
T2	403840	16	0	0
T3	402866	0	0	0
T4	956550	3318	0	0
T5	554152	0	0	0
T17	413886	34	0	0
T18	408275	0	0	0
T19	405467	15	0	0
T20	403721	0	0	0
T21	401860	0	0	0
T22	406112	16	0	0
T75	0	4	0	0
T76	0	9	0	0
T109	0	8	0	0
T111	0	16	0	0
T112	0	5	0	0

rvalidHighWhenRspFifoFull

Name	Attempts	Real Successes	Failures	Incomplete
Total	724486299	198099	0	0
T2	403840	16	0	0
T3	402866	0	0	0
T4	956550	3318	0	0
T5	554152	0	0	0
T17	413886	34	0	0
T18	408275	0	0	0
T19	405467	15	0	0
T20	403721	0	0	0
T21	401860	0	0	0
T22	406112	16	0	0
T75	0	4	0	0
T76	0	9	0	0
T109	0	8	0	0
T111	0	16	0	0
T112	0	5	0	0