ac0bef2ce| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 16.678m | 5.449ms | 5 | 5 | 100.00 |
| V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 16.678m | 5.449ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_idx1 | 17.774m | 5.499ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx2 | 15.550m | 4.826ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx3 | 16.802m | 5.972ms | 5 | 5 | 100.00 | ||
| V1 | chip_sw_uart_rand_baudrate | chip_sw_uart_rand_baudrate | 1.037h | 23.009ms | 20 | 20 | 100.00 |
| V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 44.137m | 13.371ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 35.474m | 23.198ms | 4 | 5 | 80.00 | ||
| V1 | chip_sw_gpio_out | chip_sw_gpio | 5.838m | 3.681ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_in | chip_sw_gpio | 5.838m | 3.681ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_irq | chip_sw_gpio | 5.838m | 3.681ms | 3 | 3 | 100.00 |
| V1 | chip_sw_example_tests | chip_sw_example_flash | 4.637m | 2.230ms | 3 | 3 | 100.00 |
| chip_sw_example_rom | 2.258m | 1.964ms | 3 | 3 | 100.00 | ||
| chip_sw_example_manufacturer | 3.840m | 2.789ms | 3 | 3 | 100.00 | ||
| chip_sw_example_concurrency | 5.330m | 3.060ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest_signed | 5.149m | 3.800ms | 0 | 3 | 0.00 | ||
| V1 | csr_hw_reset | chip_csr_hw_reset | 8.105m | 7.583ms | 5 | 5 | 100.00 |
| V1 | csr_rw | chip_csr_rw | 11.923m | 5.262ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | chip_csr_bit_bash | 1.308h | 52.158ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | chip_csr_aliasing | 2.424h | 64.702ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | chip_csr_mem_rw_with_rand_reset | 8.196m | 7.989ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 2.424h | 64.702ms | 5 | 5 | 100.00 |
| chip_csr_rw | 11.923m | 5.262ms | 20 | 20 | 100.00 | ||
| V1 | xbar_smoke | xbar_smoke | 11.990s | 230.537us | 100 | 100 | 100.00 |
| V1 | TOTAL | 219 | 223 | 98.21 | |||
| V2 | chip_sw_spi_device_tx_rx | chip_sw_spi_device_tx_rx | 8.351m | 3.545ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_flash_mode | chip_sw_uart_tx_rx_bootstrap | 3.040h | 59.514ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 14.917m | 7.133ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 11.495m | 4.867ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 6.375m | 3.472ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 4.682m | 2.307ms | 3 | 3 | 100.00 |
| V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 10.322m | 3.917ms | 3 | 3 | 100.00 |
| chip_sw_i2c_host_tx_rx_idx1 | 8.833m | 4.080ms | 3 | 3 | 100.00 | ||
| chip_sw_i2c_host_tx_rx_idx2 | 11.238m | 4.679ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 13.340m | 4.405ms | 3 | 3 | 100.00 |
| V2 | chip_sw_usbdev_dpi | chip_sw_usbdev_dpi | 26.575m | 7.716ms | 1 | 1 | 100.00 |
| V2 | chip_pin_mux | chip_padctrl_attributes | 7.219m | 3.943ms | 10 | 10 | 100.00 |
| V2 | chip_padctrl_attributes | chip_padctrl_attributes | 7.219m | 3.943ms | 10 | 10 | 100.00 |
| V2 | chip_sw_sleep_pin_mio_dio_val | chip_sw_sleep_pin_mio_dio_val | 5.107m | 3.029ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 7.344m | 5.660ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 5.922m | 3.631ms | 3 | 3 | 100.00 |
| V2 | chip_sw_tap_strap_sampling | chip_tap_straps_dev | 19.425m | 11.850ms | 5 | 5 | 100.00 |
| chip_tap_straps_testunlock0 | 7.897m | 5.687ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 14.001m | 7.692ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 26.442m | 14.786ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_pattgen_ios | chip_sw_pattgen_ios | 6.725m | 3.347ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pwm_pulses | chip_sw_sleep_pwm_pulses | 23.223m | 8.372ms | 3 | 3 | 100.00 |
| V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 13.871m | 6.153ms | 6 | 6 | 100.00 |
| V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 13.871m | 6.153ms | 6 | 6 | 100.00 |
| V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 34.414m | 19.933ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_mem_access | chip_jtag_mem_access | 23.921m | 12.929ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 9.119m | 4.545ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 9.461m | 4.252ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 10.738m | 5.256ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_jtag_tap_sel | chip_tap_straps_rma | 14.001m | 7.692ms | 5 | 5 | 100.00 |
| V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 12.286m | 15.601ms | 3 | 3 | 100.00 |
| V2 | chip_sw_timer | chip_sw_rv_timer_irq | 5.254m | 3.266ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 6.494m | 3.959ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wakeup | chip_sw_pwrmgr_smoketest | 7.430m | 5.714ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 6.494m | 3.959ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 11.363m | 6.162ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 15.391m | 9.977ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 15.391m | 9.977ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 8.338m | 6.081ms | 5 | 5 | 100.00 |
| V2 | chip_sw_plic_all_irqs | chip_plic_all_irqs | 31.700m | 8.300ms | 3 | 3 | 100.00 |
| V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 5.386m | 3.103ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_idle_trans | chip_sw_otbn_randomness | 10.672m | 5.641ms | 3 | 3 | 100.00 |
| chip_sw_aes_idle | 5.714m | 2.936ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_idle | 4.649m | 3.263ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_idle | 5.410m | 2.608ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 8.251m | 4.097ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_off_hmac_trans | 9.682m | 4.517ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_kmac_trans | 8.156m | 4.870ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_otbn_trans | 7.466m | 5.541ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_peri | chip_sw_clkmgr_off_peri | 26.484m | 10.048ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_div | chip_sw_clkmgr_external_clk_src_for_lc | 18.721m | 10.041ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 11.103m | 3.870ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 11.596m | 4.699ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 10.644m | 3.709ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 10.777m | 4.567ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 10.074m | 3.727ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 12.460m | 4.527ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_external_clk_src_for_lc | chip_sw_clkmgr_external_clk_src_for_lc | 18.721m | 10.041ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_external_clk_src_for_sw | chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 11.103m | 3.870ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 11.596m | 4.699ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 10.644m | 3.709ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 10.777m | 4.567ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 10.074m | 3.727ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 12.460m | 4.527ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_jitter | chip_sw_flash_ctrl_ops_jitter_en | 15.617m | 5.229ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.825m | 6.028ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 59.577m | 21.147ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 5.484m | 2.256ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 19.956m | 6.119ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 5.839m | 2.868ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 7.462m | 5.058ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.561m | 3.602ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 11.089m | 4.650ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 3.953m | 2.641ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 4.350m | 3.006ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 15.714m | 5.816ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 22.117m | 7.880ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 1.084h | 28.094ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 4.550m | 2.848ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 5.480m | 2.773ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 7.699m | 5.282ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 4.785m | 3.102ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 9.306m | 4.552ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_init_reduced_freq | 36.854m | 21.824ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 55.703m | 17.769ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 17.311m | 7.632ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 10.944m | 5.088ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 7.068m | 3.229ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 15.350m | 6.137ms | 100 | 100 | 100.00 |
| V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 10.144m | 8.521ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_wake_ups | chip_sw_pwrmgr_random_sleep_all_wake_ups | 37.572m | 20.315ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_all_wake_ups | chip_sw_pwrmgr_normal_sleep_all_wake_ups | 6.671m | 7.377ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_all_reset_reqs | chip_sw_aon_timer_wdog_bite_reset | 15.391m | 9.977ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_wake_ups | chip_sw_pwrmgr_deep_sleep_all_wake_ups | 23.034m | 18.621ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 47.526m | 27.620ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 29.579m | 15.510ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 11.030m | 4.399ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 10.144m | 8.521ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 8.131m | 4.601ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 53.161m | 38.290ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 8.515m | 7.552ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 8.670m | 6.056ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_reset_reqs | chip_sw_pwrmgr_random_sleep_all_reset_reqs | 51.903m | 26.519ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 22.979m | 7.456ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_b2b_sleep_reset_req | chip_sw_pwrmgr_b2b_sleep_reset_req | 40.520m | 28.077ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 4.591m | 2.478ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 15.350m | 6.137ms | 100 | 100 | 100.00 |
| V2 | chip_sw_rstmgr_non_sys_reset_info | chip_sw_pwrmgr_smoketest | 7.430m | 5.714ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 9.119m | 4.545ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 12.855m | 5.308ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 7.927m | 5.008ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 37.643m | 14.845ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 4.794m | 2.763ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 15.350m | 6.137ms | 100 | 100 | 100.00 |
| V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 5.556m | 3.115ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 9.762m | 5.027ms | 3 | 3 | 100.00 |
| V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 15.350m | 6.137ms | 100 | 100 | 100.00 |
| V2 | chip_sw_alert_handler_irqs | chip_plic_all_irqs | 31.700m | 8.300ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 5.952m | 3.815ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 37.643m | 14.845ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 7.210m | 5.248ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 10.726m | 4.386ms | 90 | 90 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 24.809m | 12.162ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 33.599m | 8.469ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 32.575m | 8.170ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 3.229h | 255.045ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 9.762m | 5.027ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_jtag_access | chip_tap_straps_dev | 19.425m | 11.850ms | 5 | 5 | 100.00 |
| chip_tap_straps_rma | 14.001m | 7.692ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 26.442m | 14.786ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_otp_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | 4.734m | 2.451ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 18.644m | 9.422ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 18.644m | 9.422ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 18.644m | 9.422ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_key_derivation_prod | 10.130m | 3.891ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_broadcast | chip_sw_flash_ctrl_lc_rw_en | 11.006m | 4.381ms | 3 | 3 | 100.00 |
| chip_sw_flash_rma_unlocked | 1.304h | 42.563ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 12.537m | 3.845ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_dev | 18.640m | 8.206ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 24.286m | 7.911ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 19.457m | 8.589ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 18.644m | 9.422ms | 15 | 15 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 8.792m | 3.690ms | 3 | 3 | 100.00 | ||
| chip_sw_rom_ctrl_integrity_check | 9.120m | 9.034ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_execution_main | 16.364m | 9.740ms | 3 | 3 | 100.00 | ||
| chip_prim_tl_access | 9.031m | 11.810ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_lc | 18.721m | 10.041ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 11.103m | 3.870ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 11.596m | 4.699ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 10.644m | 3.709ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 10.777m | 4.567ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 10.074m | 3.727ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 12.460m | 4.527ms | 3 | 3 | 100.00 | ||
| chip_tap_straps_dev | 19.425m | 11.850ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 14.001m | 7.692ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 26.442m | 14.786ms | 5 | 5 | 100.00 | ||
| chip_rv_dm_lc_disabled | 12.286m | 15.601ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sysrst_ctrl_inputs | chip_sw_sysrst_ctrl_inputs | 4.996m | 3.485ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_outputs | chip_sw_sysrst_ctrl_outputs | 7.916m | 3.701ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_in_irq | chip_sw_sysrst_ctrl_in_irq | 8.066m | 4.667ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_wakeup | chip_sw_sysrst_ctrl_reset | 30.634m | 24.266ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_reset | chip_sw_sysrst_ctrl_reset | 30.634m | 24.266ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_reset | chip_sw_sysrst_ctrl_reset | 30.634m | 24.266ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ec_rst_l | chip_sw_sysrst_ctrl_ec_rst_l | 59.194m | 20.646ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_flash_wp_l | chip_sw_sysrst_ctrl_ec_rst_l | 59.194m | 20.646ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ulp_z3_wakeup | chip_sw_sysrst_ctrl_ulp_z3_wakeup | 8.432m | 6.449ms | 3 | 3 | 100.00 |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 9.024m | 19.398ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_adc_ctrl_debug_cable_irq | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 9.024m | 19.398ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 9.024m | 19.398ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_enc | chip_sw_aes_enc | 4.186m | 2.930ms | 3 | 3 | 100.00 |
| chip_sw_aes_enc_jitter_en | 5.484m | 2.256ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 5.050m | 2.907ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_idle | chip_sw_aes_idle | 5.714m | 2.936ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_sideload | chip_sw_keymgr_sideload_aes | 10.828m | 5.211ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 5.887m | 3.393ms | 3 | 3 | 100.00 |
| chip_sw_hmac_enc_jitter_en | 5.839m | 2.868ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 4.649m | 3.263ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 5.191m | 3.340ms | 3 | 3 | 100.00 |
| chip_sw_kmac_mode_kmac | 6.165m | 2.969ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.561m | 3.602ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_key_derivation | 8.792m | 3.690ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 18.644m | 9.422ms | 15 | 15 | 100.00 |
| V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 5.023m | 3.178ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 4.700m | 2.645ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 5.410m | 2.608ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_ast_rng_req | chip_sw_entropy_src_ast_rng_req | 5.280m | 3.347ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 21.359m | 5.790ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fuse_en_fw_read | chip_sw_entropy_src_fuse_en_fw_read_test | 13.564m | 5.793ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_known_answer_tests | chip_sw_entropy_src_kat_test | 4.383m | 3.140ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 21.359m | 5.790ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 9.144m | 4.692ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_lc_hw_debug_en | chip_sw_csrng_lc_hw_debug_en_test | 15.139m | 7.501ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 3.942m | 2.956ms | 3 | 3 | 100.00 |
| V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 48.302m | 12.272ms | 3 | 3 | 100.00 |
| chip_sw_edn_entropy_reqs | 16.721m | 5.042ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_keymgr_key_derivation | chip_sw_keymgr_key_derivation | 8.792m | 3.690ms | 3 | 3 | 100.00 |
| chip_sw_keymgr_key_derivation_jitter_en | 7.462m | 5.058ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_keymgr_sideload_kmac | chip_sw_keymgr_sideload_kmac | 7.720m | 4.917ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_aes | chip_sw_keymgr_sideload_aes | 10.828m | 5.211ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_otbn | chip_sw_keymgr_sideload_otbn | 46.538m | 8.590ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_op | chip_sw_otbn_ecdsa_op_irq | 1.089h | 19.930ms | 3 | 3 | 100.00 |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 59.577m | 21.147ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otbn_rnd_entropy | chip_sw_otbn_randomness | 10.672m | 5.641ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_urnd_entropy | chip_sw_otbn_randomness | 10.672m | 5.641ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_idle | chip_sw_otbn_randomness | 10.672m | 5.641ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otbn_mem_scramble | chip_sw_otbn_mem_scramble | 8.800m | 3.939ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 9.120m | 9.034ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 9.120m | 9.034ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 7.877m | 4.988ms | 3 | 3 | 100.00 |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 11.089m | 4.650ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sleep_sram_ret_contents | chip_sw_sleep_sram_ret_contents | 22.395m | 11.574ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 16.364m | 9.740ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 15.350m | 6.137ms | 100 | 100 | 100.00 |
| chip_sw_data_integrity_escalation | 13.871m | 6.153ms | 6 | 6 | 100.00 | ||
| V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 18.644m | 9.422ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_keys | chip_sw_flash_init | 40.170m | 19.685ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 8.800m | 3.939ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 8.792m | 3.690ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 7.877m | 4.988ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 5.864m | 3.151ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_entropy | chip_sw_flash_init | 40.170m | 19.685ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 8.800m | 3.939ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 8.792m | 3.690ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 7.877m | 4.988ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 5.864m | 3.151ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 18.644m | 9.422ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 8.468m | 4.478ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_hw_cfg | chip_sw_lc_ctrl_otp_hw_cfg | 4.734m | 2.451ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_lc_signals | chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 12.537m | 3.845ms | 3 | 3 | 100.00 |
| chip_sw_otp_ctrl_lc_signals_dev | 18.640m | 8.206ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 24.286m | 7.911ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 19.457m | 8.589ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 18.644m | 9.422ms | 15 | 15 | 100.00 | ||
| chip_prim_tl_access | 9.031m | 11.810ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 9.031m | 11.810ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_init | chip_sw_flash_init | 40.170m | 19.685ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_host_access | chip_sw_flash_ctrl_access | 17.309m | 6.337ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.825m | 6.028ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_ctrl_ops | chip_sw_flash_ctrl_ops | 14.905m | 4.691ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en | 15.617m | 5.229ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_rma_unlocked | chip_sw_flash_rma_unlocked | 1.304h | 42.563ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_scramble | chip_sw_flash_init | 40.170m | 19.685ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_idle_low_power | chip_sw_flash_ctrl_idle_low_power | 6.984m | 3.039ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_keymgr_seeds | chip_sw_keymgr_key_derivation | 8.792m | 3.690ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_creator_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 11.006m | 4.381ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_creator_seed_wipe_on_rma | chip_sw_flash_rma_unlocked | 1.304h | 42.563ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_owner_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 11.006m | 4.381ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 11.006m | 4.381ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_wr_en | chip_sw_flash_ctrl_lc_rw_en | 11.006m | 4.381ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_seed_hw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 11.006m | 4.381ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_escalate_en | chip_sw_all_escalation_resets | 15.350m | 6.137ms | 100 | 100 | 100.00 |
| V2 | chip_sw_flash_prim_tl_access | chip_prim_tl_access | 9.031m | 11.810ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_clock_freqs | chip_sw_flash_ctrl_clock_freqs | 18.733m | 5.322ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_escalation_reset | chip_sw_flash_crash_alert | 13.205m | 6.305ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 17.311m | 7.632ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_clk_rst_inputs | chip_sw_ast_clk_rst_inputs | 15.152m | 11.854ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_sys_clk_jitter | chip_sw_flash_ctrl_ops_jitter_en | 15.617m | 5.229ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 19.825m | 6.028ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 59.577m | 21.147ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 5.484m | 2.256ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 19.956m | 6.119ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 5.839m | 2.868ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 7.462m | 5.058ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.561m | 3.602ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 11.089m | 4.650ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 3.953m | 2.641ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_ast_usb_clk_calib | chip_sw_usb_ast_clk_calib | 5.680m | 2.934ms | 1 | 1 | 100.00 |
| V2 | chip_sw_ast_alerts | chip_sw_sensor_ctrl_alert | 27.233m | 9.724ms | 5 | 5 | 100.00 |
| V2 | chip_sw_sensor_ctrl_ast_alerts | chip_sw_sensor_ctrl_alert | 27.233m | 9.724ms | 5 | 5 | 100.00 |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 6.963m | 5.137ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sensor_ctrl_ast_status | chip_sw_sensor_ctrl_status | 3.693m | 3.169ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 6.963m | 5.137ms | 3 | 3 | 100.00 |
| V2 | chip_sw_nmi_irq | chip_sw_rv_core_ibex_nmi_irq | 14.500m | 4.779ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_rnd | chip_sw_rv_core_ibex_rnd | 17.063m | 5.223ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_address_translation | chip_sw_rv_core_ibex_address_translation | 4.850m | 3.448ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_icache_scrambled_access | chip_sw_rv_core_ibex_icache_invalidate | 5.864m | 3.151ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_fault_dump | chip_sw_rstmgr_cpu_info | 12.855m | 5.308ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_core_ibex_double_fault | chip_sw_rstmgr_cpu_info | 12.855m | 5.308ms | 3 | 3 | 100.00 |
| V2 | chip_sw_smoketest | chip_sw_flash_scrambling_smoketest | 4.332m | 2.299ms | 3 | 3 | 100.00 |
| chip_sw_aes_smoketest | 4.772m | 2.842ms | 3 | 3 | 100.00 | ||
| chip_sw_aon_timer_smoketest | 5.870m | 2.416ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_smoketest | 5.295m | 2.971ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_smoketest | 4.898m | 2.806ms | 3 | 3 | 100.00 | ||
| chip_sw_entropy_src_smoketest | 9.673m | 4.124ms | 3 | 3 | 100.00 | ||
| chip_sw_gpio_smoketest | 4.930m | 2.864ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_smoketest | 5.530m | 2.413ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_smoketest | 6.545m | 3.171ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_smoketest | 44.531m | 11.518ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_smoketest | 4.165m | 2.399ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 7.430m | 5.714ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_usbdev_smoketest | 10.674m | 5.278ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_plic_smoketest | 3.728m | 2.513ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_timer_smoketest | 4.598m | 2.747ms | 3 | 3 | 100.00 | ||
| chip_sw_rstmgr_smoketest | 4.931m | 2.688ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_smoketest | 4.077m | 2.800ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest | 5.518m | 2.712ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_rom_functests | rom_keymgr_functest | 10.483m | 4.641ms | 3 | 3 | 100.00 |
| V2 | chip_sw_signed | chip_sw_uart_smoketest_signed | 5.149m | 3.800ms | 0 | 3 | 0.00 |
| V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 3.040h | 59.514ms | 3 | 3 | 100.00 |
| V2 | chip_sw_secure_boot | rom_e2e_smoke | 5.092m | 3.469ms | 0 | 3 | 0.00 |
| V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 3.354m | 3.465ms | 1 | 1 | 100.00 |
| chip_sw_lc_ctrl_raw_to_scrap | 2.901m | 3.777ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 3.364m | 3.788ms | 0 | 1 | 0.00 | ||
| chip_sw_lc_ctrl_rand_to_scrap | 3.065m | 2.769ms | 2 | 3 | 66.67 | ||
| V2 | chip_lc_test_locked | chip_sw_lc_walkthrough_testunlocks | 35.681m | 25.309ms | 3 | 3 | 100.00 |
| chip_rv_dm_lc_disabled | 12.286m | 15.601ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 1.517h | 49.528ms | 3 | 3 | 100.00 |
| chip_sw_lc_walkthrough_prod | 1.509h | 50.893ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_prodend | 16.700m | 12.507ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_rma | 1.439h | 47.016ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_testunlocks | 35.681m | 25.309ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 5.272m | 3.973ms | 3 | 3 | 100.00 |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 5.758m | 4.468ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_96mhz | 6.346m | 3.905ms | 3 | 3 | 100.00 | ||
| rom_volatile_raw_unlock | 5.274h | 119.382ms | 1 | 3 | 33.33 | ||
| V2 | chip_sw_power_idle_load | chip_sw_power_idle_load | 11.049m | 4.167ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_sleep_load | chip_sw_power_sleep_load | 8.421m | 9.654ms | 3 | 3 | 100.00 |
| V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 2.098h | 49.121ms | 3 | 3 | 100.00 |
| V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 2.534h | 53.087ms | 3 | 3 | 100.00 |
| V2 | tl_d_oob_addr_access | chip_tl_errors | 8.035m | 3.657ms | 30 | 30 | 100.00 |
| V2 | tl_d_illegal_access | chip_tl_errors | 8.035m | 3.657ms | 30 | 30 | 100.00 |
| V2 | tl_d_outstanding_access | chip_csr_aliasing | 2.424h | 64.702ms | 5 | 5 | 100.00 |
| chip_same_csr_outstanding | 1.061h | 26.678ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 8.105m | 7.583ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 11.923m | 5.262ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | chip_csr_aliasing | 2.424h | 64.702ms | 5 | 5 | 100.00 |
| chip_same_csr_outstanding | 1.061h | 26.678ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 8.105m | 7.583ms | 5 | 5 | 100.00 | ||
| chip_csr_rw | 11.923m | 5.262ms | 20 | 20 | 100.00 | ||
| V2 | xbar_base_random_sequence | xbar_random | 1.744m | 2.286ms | 100 | 100 | 100.00 |
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 8.450s | 49.425us | 100 | 100 | 100.00 |
| xbar_smoke_large_delays | 2.038m | 9.756ms | 100 | 100 | 100.00 | ||
| xbar_smoke_slow_rsp | 2.247m | 6.257ms | 100 | 100 | 100.00 | ||
| xbar_random_zero_delays | 1.204m | 606.288us | 100 | 100 | 100.00 | ||
| xbar_random_large_delays | 20.943m | 113.141ms | 100 | 100 | 100.00 | ||
| xbar_random_slow_rsp | 23.810m | 70.089ms | 100 | 100 | 100.00 | ||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 1.322m | 1.412ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 1.093m | 1.354ms | 100 | 100 | 100.00 | ||
| V2 | xbar_error_cases | xbar_error_random | 1.757m | 2.623ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 1.093m | 1.354ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 3.251m | 3.699ms | 100 | 100 | 100.00 |
| xbar_access_same_device_slow_rsp | 50.484m | 178.318ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 1.529m | 2.568ms | 100 | 100 | 100.00 |
| V2 | xbar_stress_all | xbar_stress_all | 12.750m | 18.505ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_error | 15.167m | 18.851ms | 100 | 100 | 100.00 | ||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 18.225m | 18.805ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_reset_error | 15.657m | 20.504ms | 100 | 100 | 100.00 | ||
| V2 | rom_e2e_smoke | rom_e2e_smoke | 5.092m | 3.469ms | 0 | 3 | 0.00 |
| V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 4.856m | 3.100ms | 0 | 3 | 0.00 |
| V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 4.707m | 3.673ms | 0 | 3 | 0.00 |
| V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 4.378m | 2.675ms | 0 | 1 | 0.00 |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 4.735m | 3.922ms | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 5.455m | 3.820ms | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 4.270m | 3.238ms | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 3.106m | 3.316ms | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 4.357m | 3.023ms | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 3.862m | 3.996ms | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 4.884m | 2.696ms | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 4.786m | 3.711ms | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 3.635m | 3.146ms | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 3.701m | 2.744ms | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 3.011m | 3.517ms | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 4.080m | 3.366ms | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 4.630m | 3.412ms | 0 | 1 | 0.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 4.805m | 3.194ms | 0 | 1 | 0.00 | ||
| V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 3.914m | 3.603ms | 0 | 1 | 0.00 |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 4.171m | 3.356ms | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 4.842m | 3.135ms | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 4.043m | 2.660ms | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 4.461m | 3.051ms | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 3.890m | 3.383ms | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 4.763m | 2.969ms | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 3.841m | 2.874ms | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 4.171m | 3.303ms | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 4.108m | 3.177ms | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 5.679m | 3.599ms | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 4.164m | 2.836ms | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 5.600m | 3.540ms | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 3.414m | 3.489ms | 0 | 1 | 0.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 4.030m | 2.959ms | 0 | 1 | 0.00 | ||
| V2 | rom_e2e_sigverify_mod_exp | rom_e2e_sigverify_mod_exp_test_unlocked0_otbn | 3.802m | 2.636ms | 0 | 3 | 0.00 |
| rom_e2e_sigverify_mod_exp_test_unlocked0_sw | 4.328m | 3.163ms | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_dev_otbn | 24.829m | 8.221ms | 1 | 3 | 33.33 | ||
| rom_e2e_sigverify_mod_exp_dev_sw | 4.793m | 4.026ms | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_prod_otbn | 4.623m | 3.803ms | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_prod_sw | 4.386m | 2.570ms | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_prod_end_otbn | 4.710m | 3.330ms | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_prod_end_sw | 4.078m | 2.935ms | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_rma_otbn | 5.363m | 3.713ms | 0 | 3 | 0.00 | ||
| rom_e2e_sigverify_mod_exp_rma_sw | 4.514m | 2.631ms | 0 | 3 | 0.00 | ||
| V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 5.152m | 3.536ms | 0 | 3 | 0.00 |
| rom_e2e_asm_init_dev | 4.841m | 3.613ms | 0 | 3 | 0.00 | ||
| rom_e2e_asm_init_prod | 5.025m | 3.603ms | 0 | 3 | 0.00 | ||
| rom_e2e_asm_init_prod_end | 4.335m | 3.684ms | 0 | 3 | 0.00 | ||
| rom_e2e_asm_init_rma | 4.108m | 2.579ms | 0 | 3 | 0.00 | ||
| V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 4.289m | 3.304ms | 0 | 3 | 0.00 |
| rom_e2e_keymgr_init_rom_ext_no_meas | 4.158m | 3.158ms | 0 | 3 | 0.00 | ||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 4.325m | 3.084ms | 0 | 3 | 0.00 | ||
| V2 | rom_e2e_static_critical | rom_e2e_static_critical | 4.701m | 3.434ms | 0 | 3 | 0.00 |
| V2 | TOTAL | 2552 | 2651 | 96.27 | |||
| V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 5.549m | 3.312ms | 3 | 3 | 100.00 |
| V2S | chip_sw_rv_core_ibex_lockstep_glitch | chip_sw_rv_core_ibex_lockstep_glitch | 4.865m | 2.649ms | 3 | 3 | 100.00 |
| V2S | TOTAL | 6 | 6 | 100.00 | |||
| V3 | chip_sw_spi_device_pass_through_flash_model | chip_sw_spi_device_pass_through_flash_model | 0 | 0 | -- | ||
| V3 | chip_sw_spi_device_output_when_disabled_or_sleeping | chip_sw_spi_device_output_when_disabled_or_sleeping | 0 | 0 | -- | ||
| V3 | chip_sw_usb_fs_tx_rx | chip_sw_usbdev_stream | 52.919m | 13.495ms | 1 | 1 | 100.00 |
| V3 | chip_sw_usb_vbus | chip_sw_usb_vbus | 0 | 0 | -- | ||
| V3 | chip_sw_usb_suspend | chip_sw_usb_suspend | 0 | 0 | -- | ||
| V3 | chip_usb_sof | chip_usb_sof | 0 | 0 | -- | ||
| V3 | chip_usb_wake_debug | chip_usb_wake_debug | 0 | 0 | -- | ||
| V3 | chip_usb_enumeration | chip_usb_enumeration | 0 | 0 | -- | ||
| V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 29.508m | 10.838ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 34.693m | 10.591ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 29.658m | 11.517ms | 1 | 1 | 100.00 | ||
| V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 9.978m | 4.610ms | 3 | 3 | 100.00 |
| V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 15.350m | 6.137ms | 100 | 100 | 100.00 |
| V3 | chip_sw_lc_ctrl_kmac_error | chip_sw_lc_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_csrng_edn_error | chip_sw_csrng_edn_error | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_sideload_kmac_error | chip_sw_keymgr_sideload_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_rom_ctrl_kmac_error | chip_sw_rom_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 4.887m | 2.928ms | 3 | 3 | 100.00 |
| V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 11.505m | 5.338ms | 1 | 1 | 100.00 |
| V3 | chip_sw_rv_core_ibex_alerts | chip_sw_rv_core_ibex_alerts | 0 | 0 | -- | ||
| V3 | chip_sw_coremark | chip_sw_coremark | 3.240s | 0 | 1 | 0.00 | |
| V3 | chip_sw_power_max_load | chip_sw_power_virus | 36.347m | 9.769ms | 3 | 3 | 100.00 |
| V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 29.508m | 10.838ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 34.693m | 10.591ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 29.658m | 11.517ms | 1 | 1 | 100.00 | ||
| V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 52.387m | 41.869ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_inject_dev | 52.357m | 41.800ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_inject_rma | 1.074h | 40.569ms | 1 | 1 | 100.00 | ||
| V3 | rom_bootstrap_rma | rom_bootstrap_rma | 0 | 0 | -- | ||
| V3 | rom_e2e_weak_straps | rom_e2e_weak_straps | 0 | 0 | -- | ||
| V3 | TOTAL | 17 | 18 | 94.44 | |||
| Unmapped tests | chip_sw_rstmgr_rst_cnsty_escalation | 12.423m | 4.807ms | 3 | 3 | 100.00 | |
| TOTAL | 2797 | 2901 | 96.42 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 1 | 100.00 |
| V1 | 19 | 19 | 17 | 89.47 |
| V2 | 270 | 270 | 215 | 79.63 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 26 | 12 | 11 | 42.31 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.62 | 95.61 | 94.03 | 98.15 | -- | 94.50 | 97.74 | 99.66 |
Offending '(!dst_pulse_o)' has 100 failures:
Test rom_e2e_smoke has 3 failures.
0.rom_e2e_smoke.267842904
Line 1069, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_smoke/latest/run.log
Offending '(!dst_pulse_o)'
UVM_ERROR @ 3099.722000 us: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
UVM_INFO @ 3099.722000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_e2e_smoke.3055245547
Line 1071, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_smoke/latest/run.log
Offending '(!dst_pulse_o)'
UVM_ERROR @ 3917.960000 us: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
UVM_INFO @ 3917.960000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test rom_e2e_shutdown_exception_c has 3 failures.
0.rom_e2e_shutdown_exception_c.394880276
Line 1085, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_exception_c/latest/run.log
Offending '(!dst_pulse_o)'
UVM_ERROR @ 3672.569000 us: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
UVM_INFO @ 3672.569000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_e2e_shutdown_exception_c.3390352868
Line 1088, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_exception_c/latest/run.log
Offending '(!dst_pulse_o)'
UVM_ERROR @ 3402.711500 us: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
UVM_INFO @ 3402.711500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test rom_e2e_shutdown_output has 3 failures.
0.rom_e2e_shutdown_output.2089870977
Line 1097, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log
Offending '(!dst_pulse_o)'
UVM_ERROR @ 3184.956000 us: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
UVM_INFO @ 3184.956000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rom_e2e_shutdown_output.263404232
Line 1093, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_output/latest/run.log
Offending '(!dst_pulse_o)'
UVM_ERROR @ 3099.543000 us: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
UVM_INFO @ 3099.543000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 has 1 failures.
0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.3384321407
Line 1124, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest/run.log
Offending '(!dst_pulse_o)'
UVM_ERROR @ 2675.452000 us: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
UVM_INFO @ 2675.452000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rom_e2e_boot_policy_valid_a_good_b_good_dev has 1 failures.
0.rom_e2e_boot_policy_valid_a_good_b_good_dev.1631276178
Line 1120, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest/run.log
Offending '(!dst_pulse_o)'
UVM_ERROR @ 3921.892000 us: (prim_pulse_sync.sv:96) [ASSERT FAILED] DstPulseCheck_A
UVM_INFO @ 3921.892000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 49 more tests.
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3006428677
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest/run.log
Job ID: smart:f49c718f-e93b-4ce7-ad24-8dffde62b45a
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:716) [chip_sw_lc_ctrl_scrap_vseq] Check failed (status_val) >> dummy.num() == * (* [*] vs * [*]) Unexpected status error b37c* has 1 failures:
0.chip_sw_lc_ctrl_test_locked0_to_scrap.3033103348
Line 1081, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest/run.log
UVM_ERROR @ 3788.017003 us: (chip_sw_base_vseq.sv:716) [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] Check failed (status_val) >> dummy.num() == 0 (735168 [0xb37c0] vs 0 [0x0]) Unexpected status error b37c0000
UVM_INFO @ 3788.017003 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (uart_logger.sv:25) [m_logger] Check failed (!logs_output_fd) Failed to open log for writing has 1 failures:
0.chip_sw_coremark.2852157353
Line 1042, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log
UVM_FATAL @ 0.000000 us: (uart_logger.sv:25) [uvm_test_top.env.m_uart_agent0.m_logger] Check failed (!logs_output_fd) Failed to open uvm_test_top.env.m_uart_agent0.m_logger.log for writing
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:716) [chip_sw_lc_ctrl_scrap_vseq] Check failed (status_val) >> dummy.num() == * (* [*] vs * [*]) Unexpected status error *cdf* has 1 failures:
2.chip_sw_lc_ctrl_rand_to_scrap.2922715976
Line 1083, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_lc_ctrl_rand_to_scrap/latest/run.log
UVM_ERROR @ 2769.023835 us: (chip_sw_base_vseq.sv:716) [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] Check failed (status_val) >> dummy.num() == 0 (183792 [0x2cdf0] vs 0 [0x0]) Unexpected status error 2cdf0000
UVM_INFO @ 2769.023835 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---