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Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
73.12 12.50 100.00 100.00 80.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
57.89 58.82 46.43 61.85 75.00 47.37 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
reqfifo 40.00 0.00 80.00
rspfifo 52.50 25.00 80.00


Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
57.89 58.82 46.43 61.85 75.00 47.37 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
reqfifo 100.00 100.00 100.00
rspfifo 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.74 92.86 88.64 89.47 100.00 u_socket


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
reqfifo 100.00 100.00 100.00
rspfifo 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.50 50.00 100.00 100.00 80.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.74 92.86 88.64 89.47 100.00 u_socket


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
reqfifo 65.00 50.00 80.00
rspfifo 65.00 50.00 80.00


Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.74 92.86 88.64 89.47 100.00 u_socket


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
reqfifo 100.00 100.00 100.00
rspfifo 100.00 100.00 100.00

Go back
Module Instances:
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i
TotalCoveredPercent
Conditions44100.00
Logical44100.00
Non-Logical00
Event00

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------
-1-StatusTests
0CoveredT13,T14,T15
1CoveredT16,T17,T18 

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------
-1-StatusTests
0CoveredT13,T14,T15
1CoveredT16,T17,T18
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 66 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	66	((tl_d_i.d_opcode == AccessAckData)) ?

Branches:
-1-StatusTests
1 Covered T16,T17,T18
0 Covered T13,T14,T15

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d
TotalCoveredPercent
Conditions44100.00
Logical44100.00
Non-Logical00
Event00

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------
-1-StatusTests
0CoveredT13,T14,T15
1CoveredT19,T20,T16 

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------
-1-StatusTests
0CoveredT13,T14,T15
1CoveredT19,T20,T16
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 66 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	66	((tl_d_i.d_opcode == AccessAckData)) ?

Branches:
-1-StatusTests
1 Covered T19,T20,T16
0 Covered T13,T14,T15

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h
TotalCoveredPercent
Conditions44100.00
Logical44100.00
Non-Logical00
Event00

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 66 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	66	((tl_d_i.d_opcode == AccessAckData)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T6

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d
TotalCoveredPercent
Conditions44100.00
Logical44100.00
Non-Logical00
Event00

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T2,T3 

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 66 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	66	((tl_d_i.d_opcode == AccessAckData)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T6

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d
TotalCoveredPercent
Conditions44100.00
Logical44100.00
Non-Logical00
Event00

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT2,T7,T42 

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT2,T7,T42
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 66 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	66	((tl_d_i.d_opcode == AccessAckData)) ?

Branches:
-1-StatusTests
1 Covered T2,T7,T42
0 Covered T4,T5,T6

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