Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo	40.00	0.00					80.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo	52.50	25.00					80.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo	75.00	50.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	530842302	265891	0	0
DepthKnown_A	530842302	530724310	0	0
RvalidKnown_A	530842302	530724310	0	0
WreadyKnown_A	530842302	530724310	0	0
gen_passthru_fifo.paramCheckPass	11626	11626	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530842302	265891	0	0
T1	407000	22075	0	0
T2	371554	19282	0	0
T3	338752	10320	0	0
T4	302546	8485	0	0
T5	358298	17449	0	0
T6	300046	8571	0	0
T7	333706	15511	0	0
T8	280340	7390	0	0
T9	294528	7517	0	0
T10	252120	8803	0	0
T11	223776	50	0	0
T12	173088	54	0	0
T13	361832	106	0	0
T18	264684	1511	0	0
T19	774998	198	0	0
T20	367070	100	0	0
T29	149746	50	0	0
T32	616334	48	0	0
T42	179628	78	0	0
T53	193516	5	0	0
T79	248238	138	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530842302	530724310	0	0
T1	814000	813372	0	0
T2	743108	742424	0	0
T3	677504	676848	0	0
T4	605092	604420	0	0
T5	716596	715896	0	0
T6	600092	599392	0	0
T7	667412	666756	0	0
T8	560680	560008	0	0
T9	589056	588400	0	0
T10	504240	503568	0	0
T11	671328	670344	0	0
T12	519264	518586	0	0
T13	1085496	1084818	0	0
T18	794052	793986	0	0
T20	1101210	1100574	0	0
T29	449238	448602	0	0
T36	1812714	1810026	0	0
T38	232092	231438	0	0
T41	2288478	2287824	0	0
T42	538884	538248	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530842302	530724310	0	0
T1	814000	813372	0	0
T2	743108	742424	0	0
T3	677504	676848	0	0
T4	605092	604420	0	0
T5	716596	715896	0	0
T6	600092	599392	0	0
T7	667412	666756	0	0
T8	560680	560008	0	0
T9	589056	588400	0	0
T10	504240	503568	0	0
T11	671328	670344	0	0
T12	519264	518586	0	0
T13	1085496	1084818	0	0
T18	794052	793986	0	0
T20	1101210	1100574	0	0
T29	449238	448602	0	0
T36	1812714	1810026	0	0
T38	232092	231438	0	0
T41	2288478	2287824	0	0
T42	538884	538248	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	530842302	530724310	0	0
T1	814000	813372	0	0
T2	743108	742424	0	0
T3	677504	676848	0	0
T4	605092	604420	0	0
T5	716596	715896	0	0
T6	600092	599392	0	0
T7	667412	666756	0	0
T8	560680	560008	0	0
T9	589056	588400	0	0
T10	504240	503568	0	0
T11	671328	670344	0	0
T12	519264	518586	0	0
T13	1085496	1084818	0	0
T18	794052	793986	0	0
T20	1101210	1100574	0	0
T29	449238	448602	0	0
T36	1812714	1810026	0	0
T38	232092	231438	0	0
T41	2288478	2287824	0	0
T42	538884	538248	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	11626	11626	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T8	4	4	0	0
T9	4	4	0	0
T10	4	4	0	0
T14	6	6	0	0
T15	6	6	0	0
T16	6	6	0	0
T17	6	6	0	0
T31	6	6	0	0
T33	6	6	0	0
T49	6	6	0	0
T56	6	6	0	0
T57	6	6	0	0
T58	6	6	0	0