Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	0.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	0.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
52.50	25.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
52.50	25.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	0	0.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	45	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	0	1
45	0	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	8183835	0	0	0
DepthKnown_A	8183835	8181487	0	0
RvalidKnown_A	8183835	8181487	0	0
WreadyKnown_A	8183835	8181487	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8183835	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8183835	8181487	0	0
T1	203500	203343	0	0
T2	185777	185606	0	0
T3	169376	169212	0	0
T4	151273	151105	0	0
T5	179149	178974	0	0
T6	150023	149848	0	0
T7	166853	166689	0	0
T8	140170	140002	0	0
T9	147264	147100	0	0
T10	126060	125892	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8183835	8181487	0	0
T1	203500	203343	0	0
T2	185777	185606	0	0
T3	169376	169212	0	0
T4	151273	151105	0	0
T5	179149	178974	0	0
T6	150023	149848	0	0
T7	166853	166689	0	0
T8	140170	140002	0	0
T9	147264	147100	0	0
T10	126060	125892	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8183835	8181487	0	0
T1	203500	203343	0	0
T2	185777	185606	0	0
T3	169376	169212	0	0
T4	151273	151105	0	0
T5	179149	178974	0	0
T6	150023	149848	0	0
T7	166853	166689	0	0
T8	140170	140002	0	0
T9	147264	147100	0	0
T10	126060	125892	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	1	25.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	0	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	8183835	0	0	0
DepthKnown_A	8183835	8181487	0	0
RvalidKnown_A	8183835	8181487	0	0
WreadyKnown_A	8183835	8181487	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8183835	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8183835	8181487	0	0
T1	203500	203343	0	0
T2	185777	185606	0	0
T3	169376	169212	0	0
T4	151273	151105	0	0
T5	179149	178974	0	0
T6	150023	149848	0	0
T7	166853	166689	0	0
T8	140170	140002	0	0
T9	147264	147100	0	0
T10	126060	125892	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8183835	8181487	0	0
T1	203500	203343	0	0
T2	185777	185606	0	0
T3	169376	169212	0	0
T4	151273	151105	0	0
T5	179149	178974	0	0
T6	150023	149848	0	0
T7	166853	166689	0	0
T8	140170	140002	0	0
T9	147264	147100	0	0
T10	126060	125892	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8183835	8181487	0	0
T1	203500	203343	0	0
T2	185777	185606	0	0
T3	169376	169212	0	0
T4	151273	151105	0	0
T5	179149	178974	0	0
T6	150023	149848	0	0
T7	166853	166689	0	0
T8	140170	140002	0	0
T9	147264	147100	0	0
T10	126060	125892	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	8183835	43576	0	0
DepthKnown_A	8183835	8181487	0	0
RvalidKnown_A	8183835	8181487	0	0
WreadyKnown_A	8183835	8181487	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8183835	43576	0	0
T1	203500	4518	0	0
T2	185777	4111	0	0
T3	169376	6416	0	0
T4	151273	5299	0	0
T5	179149	3441	0	0
T6	150023	5445	0	0
T7	166853	3172	0	0
T8	140170	4590	0	0
T9	147264	4525	0	0
T10	126060	1825	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8183835	8181487	0	0
T1	203500	203343	0	0
T2	185777	185606	0	0
T3	169376	169212	0	0
T4	151273	151105	0	0
T5	179149	178974	0	0
T6	150023	149848	0	0
T7	166853	166689	0	0
T8	140170	140002	0	0
T9	147264	147100	0	0
T10	126060	125892	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8183835	8181487	0	0
T1	203500	203343	0	0
T2	185777	185606	0	0
T3	169376	169212	0	0
T4	151273	151105	0	0
T5	179149	178974	0	0
T6	150023	149848	0	0
T7	166853	166689	0	0
T8	140170	140002	0	0
T9	147264	147100	0	0
T10	126060	125892	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8183835	8181487	0	0
T1	203500	203343	0	0
T2	185777	185606	0	0
T3	169376	169212	0	0
T4	151273	151105	0	0
T5	179149	178974	0	0
T6	150023	149848	0	0
T7	166853	166689	0	0
T8	140170	140002	0	0
T9	147264	147100	0	0
T10	126060	125892	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	8183835	82549	0	0
DepthKnown_A	8183835	8181487	0	0
RvalidKnown_A	8183835	8181487	0	0
WreadyKnown_A	8183835	8181487	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8183835	82549	0	0
T1	203500	17557	0	0
T2	185777	15171	0	0
T3	169376	3904	0	0
T4	151273	3186	0	0
T5	179149	14008	0	0
T6	150023	3126	0	0
T7	166853	12339	0	0
T8	140170	2800	0	0
T9	147264	2992	0	0
T10	126060	6978	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8183835	8181487	0	0
T1	203500	203343	0	0
T2	185777	185606	0	0
T3	169376	169212	0	0
T4	151273	151105	0	0
T5	179149	178974	0	0
T6	150023	149848	0	0
T7	166853	166689	0	0
T8	140170	140002	0	0
T9	147264	147100	0	0
T10	126060	125892	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8183835	8181487	0	0
T1	203500	203343	0	0
T2	185777	185606	0	0
T3	169376	169212	0	0
T4	151273	151105	0	0
T5	179149	178974	0	0
T6	150023	149848	0	0
T7	166853	166689	0	0
T8	140170	140002	0	0
T9	147264	147100	0	0
T10	126060	125892	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8183835	8181487	0	0
T1	203500	203343	0	0
T2	185777	185606	0	0
T3	169376	169212	0	0
T4	151273	151105	0	0
T5	179149	178974	0	0
T6	150023	149848	0	0
T7	166853	166689	0	0
T8	140170	140002	0	0
T9	147264	147100	0	0
T10	126060	125892	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	83017827	33344	0	0
DepthKnown_A	83017827	82999727	0	0
RvalidKnown_A	83017827	82999727	0	0
WreadyKnown_A	83017827	82999727	0	0
gen_passthru_fifo.paramCheckPass	1927	1927	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83017827	33344	0	0
T11	111888	25	0	0
T12	86544	27	0	0
T13	180916	53	0	0
T18	132342	620	0	0
T19	387499	98	0	0
T20	183535	49	0	0
T29	74873	25	0	0
T32	308167	24	0	0
T42	89814	39	0	0
T79	124119	69	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83017827	82999727	0	0
T11	111888	111724	0	0
T12	86544	86431	0	0
T13	180916	180803	0	0
T18	132342	132331	0	0
T20	183535	183429	0	0
T29	74873	74767	0	0
T36	302119	301671	0	0
T38	38682	38573	0	0
T41	381413	381304	0	0
T42	89814	89708	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83017827	82999727	0	0
T11	111888	111724	0	0
T12	86544	86431	0	0
T13	180916	180803	0	0
T18	132342	132331	0	0
T20	183535	183429	0	0
T29	74873	74767	0	0
T36	302119	301671	0	0
T38	38682	38573	0	0
T41	381413	381304	0	0
T42	89814	89708	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83017827	82999727	0	0
T11	111888	111724	0	0
T12	86544	86431	0	0
T13	180916	180803	0	0
T18	132342	132331	0	0
T20	183535	183429	0	0
T29	74873	74767	0	0
T36	302119	301671	0	0
T38	38682	38573	0	0
T41	381413	381304	0	0
T42	89814	89708	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T31	1	1	0	0
T33	1	1	0	0
T49	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	83017827	36539	0	0
DepthKnown_A	83017827	82999727	0	0
RvalidKnown_A	83017827	82999727	0	0
WreadyKnown_A	83017827	82999727	0	0
gen_passthru_fifo.paramCheckPass	1927	1927	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83017827	36539	0	0
T11	111888	25	0	0
T12	86544	27	0	0
T13	180916	53	0	0
T18	132342	891	0	0
T19	387499	100	0	0
T20	183535	51	0	0
T29	74873	25	0	0
T32	308167	24	0	0
T42	89814	39	0	0
T79	124119	69	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83017827	82999727	0	0
T11	111888	111724	0	0
T12	86544	86431	0	0
T13	180916	180803	0	0
T18	132342	132331	0	0
T20	183535	183429	0	0
T29	74873	74767	0	0
T36	302119	301671	0	0
T38	38682	38573	0	0
T41	381413	381304	0	0
T42	89814	89708	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83017827	82999727	0	0
T11	111888	111724	0	0
T12	86544	86431	0	0
T13	180916	180803	0	0
T18	132342	132331	0	0
T20	183535	183429	0	0
T29	74873	74767	0	0
T36	302119	301671	0	0
T38	38682	38573	0	0
T41	381413	381304	0	0
T42	89814	89708	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83017827	82999727	0	0
T11	111888	111724	0	0
T12	86544	86431	0	0
T13	180916	180803	0	0
T18	132342	132331	0	0
T20	183535	183429	0	0
T29	74873	74767	0	0
T36	302119	301671	0	0
T38	38682	38573	0	0
T41	381413	381304	0	0
T42	89814	89708	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T31	1	1	0	0
T33	1	1	0	0
T49	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	83017827	16	0	0
DepthKnown_A	83017827	82999727	0	0
RvalidKnown_A	83017827	82999727	0	0
WreadyKnown_A	83017827	82999727	0	0
gen_passthru_fifo.paramCheckPass	1927	1927	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83017827	16	0	0
T53	193516	5	0	0
T77	167803	4	0	0
T78	187807	1	0	0
T84	143464	0	0	0
T225	228368	0	0	0
T227	142923	0	0	0
T350	103821	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83017827	82999727	0	0
T11	111888	111724	0	0
T12	86544	86431	0	0
T13	180916	180803	0	0
T18	132342	132331	0	0
T20	183535	183429	0	0
T29	74873	74767	0	0
T36	302119	301671	0	0
T38	38682	38573	0	0
T41	381413	381304	0	0
T42	89814	89708	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83017827	82999727	0	0
T11	111888	111724	0	0
T12	86544	86431	0	0
T13	180916	180803	0	0
T18	132342	132331	0	0
T20	183535	183429	0	0
T29	74873	74767	0	0
T36	302119	301671	0	0
T38	38682	38573	0	0
T41	381413	381304	0	0
T42	89814	89708	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83017827	82999727	0	0
T11	111888	111724	0	0
T12	86544	86431	0	0
T13	180916	180803	0	0
T18	132342	132331	0	0
T20	183535	183429	0	0
T29	74873	74767	0	0
T36	302119	301671	0	0
T38	38682	38573	0	0
T41	381413	381304	0	0
T42	89814	89708	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T31	1	1	0	0
T33	1	1	0	0
T49	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	83017827	16	0	0
DepthKnown_A	83017827	82999727	0	0
RvalidKnown_A	83017827	82999727	0	0
WreadyKnown_A	83017827	82999727	0	0
gen_passthru_fifo.paramCheckPass	1927	1927	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83017827	16	0	0
T53	193516	5	0	0
T77	167803	4	0	0
T78	187807	1	0	0
T84	143464	0	0	0
T225	228368	0	0	0
T227	142923	0	0	0
T350	103821	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83017827	82999727	0	0
T11	111888	111724	0	0
T12	86544	86431	0	0
T13	180916	180803	0	0
T18	132342	132331	0	0
T20	183535	183429	0	0
T29	74873	74767	0	0
T36	302119	301671	0	0
T38	38682	38573	0	0
T41	381413	381304	0	0
T42	89814	89708	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83017827	82999727	0	0
T11	111888	111724	0	0
T12	86544	86431	0	0
T13	180916	180803	0	0
T18	132342	132331	0	0
T20	183535	183429	0	0
T29	74873	74767	0	0
T36	302119	301671	0	0
T38	38682	38573	0	0
T41	381413	381304	0	0
T42	89814	89708	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83017827	82999727	0	0
T11	111888	111724	0	0
T12	86544	86431	0	0
T13	180916	180803	0	0
T18	132342	132331	0	0
T20	183535	183429	0	0
T29	74873	74767	0	0
T36	302119	301671	0	0
T38	38682	38573	0	0
T41	381413	381304	0	0
T42	89814	89708	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T31	1	1	0	0
T33	1	1	0	0
T49	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	83017827	33328	0	0
DepthKnown_A	83017827	82999727	0	0
RvalidKnown_A	83017827	82999727	0	0
WreadyKnown_A	83017827	82999727	0	0
gen_passthru_fifo.paramCheckPass	1927	1927	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83017827	33328	0	0
T11	111888	25	0	0
T12	86544	27	0	0
T13	180916	53	0	0
T18	132342	620	0	0
T19	387499	98	0	0
T20	183535	49	0	0
T29	74873	25	0	0
T32	308167	24	0	0
T42	89814	39	0	0
T79	124119	69	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83017827	82999727	0	0
T11	111888	111724	0	0
T12	86544	86431	0	0
T13	180916	180803	0	0
T18	132342	132331	0	0
T20	183535	183429	0	0
T29	74873	74767	0	0
T36	302119	301671	0	0
T38	38682	38573	0	0
T41	381413	381304	0	0
T42	89814	89708	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83017827	82999727	0	0
T11	111888	111724	0	0
T12	86544	86431	0	0
T13	180916	180803	0	0
T18	132342	132331	0	0
T20	183535	183429	0	0
T29	74873	74767	0	0
T36	302119	301671	0	0
T38	38682	38573	0	0
T41	381413	381304	0	0
T42	89814	89708	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83017827	82999727	0	0
T11	111888	111724	0	0
T12	86544	86431	0	0
T13	180916	180803	0	0
T18	132342	132331	0	0
T20	183535	183429	0	0
T29	74873	74767	0	0
T36	302119	301671	0	0
T38	38682	38573	0	0
T41	381413	381304	0	0
T42	89814	89708	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T31	1	1	0	0
T33	1	1	0	0
T49	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	83017827	36523	0	0
DepthKnown_A	83017827	82999727	0	0
RvalidKnown_A	83017827	82999727	0	0
WreadyKnown_A	83017827	82999727	0	0
gen_passthru_fifo.paramCheckPass	1927	1927	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83017827	36523	0	0
T11	111888	25	0	0
T12	86544	27	0	0
T13	180916	53	0	0
T18	132342	891	0	0
T19	387499	100	0	0
T20	183535	51	0	0
T29	74873	25	0	0
T32	308167	24	0	0
T42	89814	39	0	0
T79	124119	69	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83017827	82999727	0	0
T11	111888	111724	0	0
T12	86544	86431	0	0
T13	180916	180803	0	0
T18	132342	132331	0	0
T20	183535	183429	0	0
T29	74873	74767	0	0
T36	302119	301671	0	0
T38	38682	38573	0	0
T41	381413	381304	0	0
T42	89814	89708	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83017827	82999727	0	0
T11	111888	111724	0	0
T12	86544	86431	0	0
T13	180916	180803	0	0
T18	132342	132331	0	0
T20	183535	183429	0	0
T29	74873	74767	0	0
T36	302119	301671	0	0
T38	38682	38573	0	0
T41	381413	381304	0	0
T42	89814	89708	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	83017827	82999727	0	0
T11	111888	111724	0	0
T12	86544	86431	0	0
T13	180916	180803	0	0
T18	132342	132331	0	0
T20	183535	183429	0	0
T29	74873	74767	0	0
T36	302119	301671	0	0
T38	38682	38573	0	0
T41	381413	381304	0	0
T42	89814	89708	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T31	1	1	0	0
T33	1	1	0	0
T49	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0