Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo	40.00	0.00					80.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo	52.50	25.00					80.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo	75.00	50.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	583595012	260560	0	0
DepthKnown_A	583595012	583476620	0	0
RvalidKnown_A	583595012	583476620	0	0
WreadyKnown_A	583595012	583476620	0	0
gen_passthru_fifo.paramCheckPass	11626	11626	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583595012	260560	0	0
T1	373032	19053	0	0
T2	323640	15676	0	0
T3	301644	14153	0	0
T4	351054	10454	0	0
T5	356048	17136	0	0
T6	333776	10430	0	0
T7	307214	14025	0	0
T8	283310	7367	0	0
T9	305854	13883	0	0
T10	285998	6654	0	0
T11	374294	100	0	0
T12	224918	68	0	0
T13	426892	148	0	0
T19	468640	1042	0	0
T20	444044	101	0	0
T49	322335	62	0	0
T50	398646	152	0	0
T51	306832	100	0	0
T67	205448	50	0	0
T74	170296	76	0	0
T89	102772	6	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583595012	583476620	0	0
T1	746064	745420	0	0
T2	647280	646624	0	0
T3	603288	602588	0	0
T4	702108	701452	0	0
T5	712096	711424	0	0
T6	667552	666852	0	0
T7	614428	613756	0	0
T8	566620	565948	0	0
T9	611708	610964	0	0
T10	571996	571296	0	0
T11	1122882	1121550	0	0
T12	674754	674058	0	0
T13	1280676	1280022	0	0
T19	1405920	1405818	0	0
T20	1332132	1331412	0	0
T49	644670	643686	0	0
T50	1195938	1195284	0	0
T51	920496	919842	0	0
T67	616344	615378	0	0
T74	510888	510276	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583595012	583476620	0	0
T1	746064	745420	0	0
T2	647280	646624	0	0
T3	603288	602588	0	0
T4	702108	701452	0	0
T5	712096	711424	0	0
T6	667552	666852	0	0
T7	614428	613756	0	0
T8	566620	565948	0	0
T9	611708	610964	0	0
T10	571996	571296	0	0
T11	1122882	1121550	0	0
T12	674754	674058	0	0
T13	1280676	1280022	0	0
T19	1405920	1405818	0	0
T20	1332132	1331412	0	0
T49	644670	643686	0	0
T50	1195938	1195284	0	0
T51	920496	919842	0	0
T67	616344	615378	0	0
T74	510888	510276	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	583595012	583476620	0	0
T1	746064	745420	0	0
T2	647280	646624	0	0
T3	603288	602588	0	0
T4	702108	701452	0	0
T5	712096	711424	0	0
T6	667552	666852	0	0
T7	614428	613756	0	0
T8	566620	565948	0	0
T9	611708	610964	0	0
T10	571996	571296	0	0
T11	1122882	1121550	0	0
T12	674754	674058	0	0
T13	1280676	1280022	0	0
T19	1405920	1405818	0	0
T20	1332132	1331412	0	0
T49	644670	643686	0	0
T50	1195938	1195284	0	0
T51	920496	919842	0	0
T67	616344	615378	0	0
T74	510888	510276	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	11626	11626	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T8	4	4	0	0
T9	4	4	0	0
T10	4	4	0	0
T14	6	6	0	0
T15	6	6	0	0
T16	6	6	0	0
T17	6	6	0	0
T18	6	6	0	0
T38	6	6	0	0
T52	6	6	0	0
T61	6	6	0	0
T62	6	6	0	0
T63	6	6	0	0