Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	0.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
40.00	0.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
52.50	25.00					80.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
52.50	25.00					80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	0	0.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	45	1	0	0.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	0	1
45	0	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	7445450	0	0	0
DepthKnown_A	7445450	7443068	0	0
RvalidKnown_A	7445450	7443068	0	0
WreadyKnown_A	7445450	7443068	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7445450	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7445450	7443068	0	0
T1	186516	186355	0	0
T2	161820	161656	0	0
T3	150822	150647	0	0
T4	175527	175363	0	0
T5	178024	177856	0	0
T6	166888	166713	0	0
T7	153607	153439	0	0
T8	141655	141487	0	0
T9	152927	152741	0	0
T10	142999	142824	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7445450	7443068	0	0
T1	186516	186355	0	0
T2	161820	161656	0	0
T3	150822	150647	0	0
T4	175527	175363	0	0
T5	178024	177856	0	0
T6	166888	166713	0	0
T7	153607	153439	0	0
T8	141655	141487	0	0
T9	152927	152741	0	0
T10	142999	142824	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7445450	7443068	0	0
T1	186516	186355	0	0
T2	161820	161656	0	0
T3	150822	150647	0	0
T4	175527	175363	0	0
T5	178024	177856	0	0
T6	166888	166713	0	0
T7	153607	153439	0	0
T8	141655	141487	0	0
T9	152927	152741	0	0
T10	142999	142824	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	1	25.00
CONT_ASSIGN	44	1	0	0.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	0	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	4	80.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	4	80.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	7445450	0	0	0
DepthKnown_A	7445450	7443068	0	0
RvalidKnown_A	7445450	7443068	0	0
WreadyKnown_A	7445450	7443068	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7445450	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7445450	7443068	0	0
T1	186516	186355	0	0
T2	161820	161656	0	0
T3	150822	150647	0	0
T4	175527	175363	0	0
T5	178024	177856	0	0
T6	166888	166713	0	0
T7	153607	153439	0	0
T8	141655	141487	0	0
T9	152927	152741	0	0
T10	142999	142824	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7445450	7443068	0	0
T1	186516	186355	0	0
T2	161820	161656	0	0
T3	150822	150647	0	0
T4	175527	175363	0	0
T5	178024	177856	0	0
T6	166888	166713	0	0
T7	153607	153439	0	0
T8	141655	141487	0	0
T9	152927	152741	0	0
T10	142999	142824	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7445450	7443068	0	0
T1	186516	186355	0	0
T2	161820	161656	0	0
T3	150822	150647	0	0
T4	175527	175363	0	0
T5	178024	177856	0	0
T6	166888	166713	0	0
T7	153607	153439	0	0
T8	141655	141487	0	0
T9	152927	152741	0	0
T10	142999	142824	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	7445450	41946	0	0
DepthKnown_A	7445450	7443068	0	0
RvalidKnown_A	7445450	7443068	0	0
WreadyKnown_A	7445450	7443068	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7445450	41946	0	0
T1	186516	3932	0	0
T2	161820	3512	0	0
T3	150822	3146	0	0
T4	175527	6448	0	0
T5	178024	3426	0	0
T6	166888	6678	0	0
T7	153607	3252	0	0
T8	141655	4497	0	0
T9	152927	2961	0	0
T10	142999	3860	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7445450	7443068	0	0
T1	186516	186355	0	0
T2	161820	161656	0	0
T3	150822	150647	0	0
T4	175527	175363	0	0
T5	178024	177856	0	0
T6	166888	166713	0	0
T7	153607	153439	0	0
T8	141655	141487	0	0
T9	152927	152741	0	0
T10	142999	142824	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7445450	7443068	0	0
T1	186516	186355	0	0
T2	161820	161656	0	0
T3	150822	150647	0	0
T4	175527	175363	0	0
T5	178024	177856	0	0
T6	166888	166713	0	0
T7	153607	153439	0	0
T8	141655	141487	0	0
T9	152927	152741	0	0
T10	142999	142824	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7445450	7443068	0	0
T1	186516	186355	0	0
T2	161820	161656	0	0
T3	150822	150647	0	0
T4	175527	175363	0	0
T5	178024	177856	0	0
T6	166888	166713	0	0
T7	153607	153439	0	0
T8	141655	141487	0	0
T9	152927	152741	0	0
T10	142999	142824	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	7445450	87920	0	0
DepthKnown_A	7445450	7443068	0	0
RvalidKnown_A	7445450	7443068	0	0
WreadyKnown_A	7445450	7443068	0	0
gen_passthru_fifo.paramCheckPass	16	16	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7445450	87920	0	0
T1	186516	15121	0	0
T2	161820	12164	0	0
T3	150822	11007	0	0
T4	175527	4006	0	0
T5	178024	13710	0	0
T6	166888	3752	0	0
T7	153607	10773	0	0
T8	141655	2870	0	0
T9	152927	10922	0	0
T10	142999	2794	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7445450	7443068	0	0
T1	186516	186355	0	0
T2	161820	161656	0	0
T3	150822	150647	0	0
T4	175527	175363	0	0
T5	178024	177856	0	0
T6	166888	166713	0	0
T7	153607	153439	0	0
T8	141655	141487	0	0
T9	152927	152741	0	0
T10	142999	142824	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7445450	7443068	0	0
T1	186516	186355	0	0
T2	161820	161656	0	0
T3	150822	150647	0	0
T4	175527	175363	0	0
T5	178024	177856	0	0
T6	166888	166713	0	0
T7	153607	153439	0	0
T8	141655	141487	0	0
T9	152927	152741	0	0
T10	142999	142824	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7445450	7443068	0	0
T1	186516	186355	0	0
T2	161820	161656	0	0
T3	150822	150647	0	0
T4	175527	175363	0	0
T5	178024	177856	0	0
T6	166888	166713	0	0
T7	153607	153439	0	0
T8	141655	141487	0	0
T9	152927	152741	0	0
T10	142999	142824	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	16	16	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	92302202	31007	0	0
DepthKnown_A	92302202	92284058	0	0
RvalidKnown_A	92302202	92284058	0	0
WreadyKnown_A	92302202	92284058	0	0
gen_passthru_fifo.paramCheckPass	1927	1927	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92302202	31007	0	0
T11	187147	50	0	0
T12	112459	34	0	0
T13	213446	74	0	0
T19	234320	521	0	0
T20	222022	49	0	0
T49	107445	29	0	0
T50	199323	76	0	0
T51	153416	50	0	0
T67	102724	25	0	0
T74	85148	38	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92302202	92284058	0	0
T11	187147	186925	0	0
T12	112459	112343	0	0
T13	213446	213337	0	0
T19	234320	234303	0	0
T20	222022	221902	0	0
T49	107445	107281	0	0
T50	199323	199214	0	0
T51	153416	153307	0	0
T67	102724	102563	0	0
T74	85148	85046	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92302202	92284058	0	0
T11	187147	186925	0	0
T12	112459	112343	0	0
T13	213446	213337	0	0
T19	234320	234303	0	0
T20	222022	221902	0	0
T49	107445	107281	0	0
T50	199323	199214	0	0
T51	153416	153307	0	0
T67	102724	102563	0	0
T74	85148	85046	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92302202	92284058	0	0
T11	187147	186925	0	0
T12	112459	112343	0	0
T13	213446	213337	0	0
T19	234320	234303	0	0
T20	222022	221902	0	0
T49	107445	107281	0	0
T50	199323	199214	0	0
T51	153416	153307	0	0
T67	102724	102563	0	0
T74	85148	85046	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T38	1	1	0	0
T52	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	92302202	34340	0	0
DepthKnown_A	92302202	92284058	0	0
RvalidKnown_A	92302202	92284058	0	0
WreadyKnown_A	92302202	92284058	0	0
gen_passthru_fifo.paramCheckPass	1927	1927	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92302202	34340	0	0
T11	187147	50	0	0
T12	112459	34	0	0
T13	213446	74	0	0
T19	234320	521	0	0
T20	222022	52	0	0
T49	107445	29	0	0
T50	199323	76	0	0
T51	153416	50	0	0
T67	102724	25	0	0
T74	85148	38	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92302202	92284058	0	0
T11	187147	186925	0	0
T12	112459	112343	0	0
T13	213446	213337	0	0
T19	234320	234303	0	0
T20	222022	221902	0	0
T49	107445	107281	0	0
T50	199323	199214	0	0
T51	153416	153307	0	0
T67	102724	102563	0	0
T74	85148	85046	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92302202	92284058	0	0
T11	187147	186925	0	0
T12	112459	112343	0	0
T13	213446	213337	0	0
T19	234320	234303	0	0
T20	222022	221902	0	0
T49	107445	107281	0	0
T50	199323	199214	0	0
T51	153416	153307	0	0
T67	102724	102563	0	0
T74	85148	85046	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92302202	92284058	0	0
T11	187147	186925	0	0
T12	112459	112343	0	0
T13	213446	213337	0	0
T19	234320	234303	0	0
T20	222022	221902	0	0
T49	107445	107281	0	0
T50	199323	199214	0	0
T51	153416	153307	0	0
T67	102724	102563	0	0
T74	85148	85046	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T38	1	1	0	0
T52	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	92302202	19	0	0
DepthKnown_A	92302202	92284058	0	0
RvalidKnown_A	92302202	92284058	0	0
WreadyKnown_A	92302202	92284058	0	0
gen_passthru_fifo.paramCheckPass	1927	1927	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92302202	19	0	0
T49	107445	4	0	0
T89	102772	6	0	0
T90	168081	3	0	0
T264	103799	6	0	0
T265	118907	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92302202	92284058	0	0
T11	187147	186925	0	0
T12	112459	112343	0	0
T13	213446	213337	0	0
T19	234320	234303	0	0
T20	222022	221902	0	0
T49	107445	107281	0	0
T50	199323	199214	0	0
T51	153416	153307	0	0
T67	102724	102563	0	0
T74	85148	85046	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92302202	92284058	0	0
T11	187147	186925	0	0
T12	112459	112343	0	0
T13	213446	213337	0	0
T19	234320	234303	0	0
T20	222022	221902	0	0
T49	107445	107281	0	0
T50	199323	199214	0	0
T51	153416	153307	0	0
T67	102724	102563	0	0
T74	85148	85046	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92302202	92284058	0	0
T11	187147	186925	0	0
T12	112459	112343	0	0
T13	213446	213337	0	0
T19	234320	234303	0	0
T20	222022	221902	0	0
T49	107445	107281	0	0
T50	199323	199214	0	0
T51	153416	153307	0	0
T67	102724	102563	0	0
T74	85148	85046	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T38	1	1	0	0
T52	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	92302202	19	0	0
DepthKnown_A	92302202	92284058	0	0
RvalidKnown_A	92302202	92284058	0	0
WreadyKnown_A	92302202	92284058	0	0
gen_passthru_fifo.paramCheckPass	1927	1927	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92302202	19	0	0
T49	107445	4	0	0
T89	102772	6	0	0
T90	168081	3	0	0
T264	103799	6	0	0
T265	118907	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92302202	92284058	0	0
T11	187147	186925	0	0
T12	112459	112343	0	0
T13	213446	213337	0	0
T19	234320	234303	0	0
T20	222022	221902	0	0
T49	107445	107281	0	0
T50	199323	199214	0	0
T51	153416	153307	0	0
T67	102724	102563	0	0
T74	85148	85046	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92302202	92284058	0	0
T11	187147	186925	0	0
T12	112459	112343	0	0
T13	213446	213337	0	0
T19	234320	234303	0	0
T20	222022	221902	0	0
T49	107445	107281	0	0
T50	199323	199214	0	0
T51	153416	153307	0	0
T67	102724	102563	0	0
T74	85148	85046	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92302202	92284058	0	0
T11	187147	186925	0	0
T12	112459	112343	0	0
T13	213446	213337	0	0
T19	234320	234303	0	0
T20	222022	221902	0	0
T49	107445	107281	0	0
T50	199323	199214	0	0
T51	153416	153307	0	0
T67	102724	102563	0	0
T74	85148	85046	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T38	1	1	0	0
T52	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	92302202	30988	0	0
DepthKnown_A	92302202	92284058	0	0
RvalidKnown_A	92302202	92284058	0	0
WreadyKnown_A	92302202	92284058	0	0
gen_passthru_fifo.paramCheckPass	1927	1927	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92302202	30988	0	0
T11	187147	50	0	0
T12	112459	34	0	0
T13	213446	74	0	0
T19	234320	521	0	0
T20	222022	49	0	0
T49	107445	25	0	0
T50	199323	76	0	0
T51	153416	50	0	0
T67	102724	25	0	0
T74	85148	38	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92302202	92284058	0	0
T11	187147	186925	0	0
T12	112459	112343	0	0
T13	213446	213337	0	0
T19	234320	234303	0	0
T20	222022	221902	0	0
T49	107445	107281	0	0
T50	199323	199214	0	0
T51	153416	153307	0	0
T67	102724	102563	0	0
T74	85148	85046	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92302202	92284058	0	0
T11	187147	186925	0	0
T12	112459	112343	0	0
T13	213446	213337	0	0
T19	234320	234303	0	0
T20	222022	221902	0	0
T49	107445	107281	0	0
T50	199323	199214	0	0
T51	153416	153307	0	0
T67	102724	102563	0	0
T74	85148	85046	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92302202	92284058	0	0
T11	187147	186925	0	0
T12	112459	112343	0	0
T13	213446	213337	0	0
T19	234320	234303	0	0
T20	222022	221902	0	0
T49	107445	107281	0	0
T50	199323	199214	0	0
T51	153416	153307	0	0
T67	102724	102563	0	0
T74	85148	85046	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T38	1	1	0	0
T52	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	92302202	34321	0	0
DepthKnown_A	92302202	92284058	0	0
RvalidKnown_A	92302202	92284058	0	0
WreadyKnown_A	92302202	92284058	0	0
gen_passthru_fifo.paramCheckPass	1927	1927	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92302202	34321	0	0
T11	187147	50	0	0
T12	112459	34	0	0
T13	213446	74	0	0
T19	234320	521	0	0
T20	222022	52	0	0
T49	107445	25	0	0
T50	199323	76	0	0
T51	153416	50	0	0
T67	102724	25	0	0
T74	85148	38	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92302202	92284058	0	0
T11	187147	186925	0	0
T12	112459	112343	0	0
T13	213446	213337	0	0
T19	234320	234303	0	0
T20	222022	221902	0	0
T49	107445	107281	0	0
T50	199323	199214	0	0
T51	153416	153307	0	0
T67	102724	102563	0	0
T74	85148	85046	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92302202	92284058	0	0
T11	187147	186925	0	0
T12	112459	112343	0	0
T13	213446	213337	0	0
T19	234320	234303	0	0
T20	222022	221902	0	0
T49	107445	107281	0	0
T50	199323	199214	0	0
T51	153416	153307	0	0
T67	102724	102563	0	0
T74	85148	85046	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	92302202	92284058	0	0
T11	187147	186925	0	0
T12	112459	112343	0	0
T13	213446	213337	0	0
T19	234320	234303	0	0
T20	222022	221902	0	0
T49	107445	107281	0	0
T50	199323	199214	0	0
T51	153416	153307	0	0
T67	102724	102563	0	0
T74	85148	85046	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1927	1927	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T38	1	1	0	0
T52	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0