Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_plic_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.80 99.94 99.75 99.52 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_plic.u_reg 99.80 99.94 99.75 99.52 100.00

Line Coverage for Module : rv_plic_reg_top
Line No.TotalCoveredPercent
TOTAL1552155199.94
ALWAYS714375.00
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CONT_ASSIGN9311100.00
CONT_ASSIGN12111100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN1649411100.00
CONT_ASSIGN1650811100.00
CONT_ASSIGN1654211100.00
CONT_ASSIGN1655611100.00
ALWAYS16562202202100.00
CONT_ASSIGN1676611100.00
ALWAYS1677011100.00
CONT_ASSIGN1697511100.00
CONT_ASSIGN1697711100.00
CONT_ASSIGN1697811100.00
CONT_ASSIGN1698011100.00
CONT_ASSIGN1698111100.00
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CONT_ASSIGN1699011100.00
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CONT_ASSIGN1703711100.00
CONT_ASSIGN1703811100.00
CONT_ASSIGN1704011100.00
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CONT_ASSIGN1748211100.00
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CONT_ASSIGN1752111100.00
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CONT_ASSIGN1752411100.00
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CONT_ASSIGN1760311100.00
CONT_ASSIGN1760511100.00
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ALWAYS17922202202100.00
ALWAYS18128561561100.00
CONT_ASSIGN1930300
CONT_ASSIGN1931111100.00
CONT_ASSIGN1931211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
71 1 1
72 1 1
73 1 1
74 0 1
MISSING_ELSE
80 1 1
92 1 1
93 1 1
121 1 1
122 1 1
16494 1 1
16508 1 1
16542 1 1
16556 1 1
16562 1 1
16563 1 1
16564 1 1
16565 1 1
16566 1 1
16567 1 1
16568 1 1
16569 1 1
16570 1 1
16571 1 1
16572 1 1
16573 1 1
16574 1 1
16575 1 1
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16577 1 1
16578 1 1
16579 1 1
16580 1 1
16581 1 1
16582 1 1
16583 1 1
16584 1 1
16585 1 1
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16589 1 1
16590 1 1
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16592 1 1
16593 1 1
16594 1 1
16595 1 1
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16599 1 1
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16601 1 1
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19228 1 1
19229 1 1
19230 1 1
19231 1 1
19232 1 1
19233 1 1
19234 1 1
19235 1 1
19236 1 1
19237 1 1
19238 1 1
19239 1 1
19240 1 1
19241 1 1
19242 1 1
19243 1 1
19244 1 1
19245 1 1
19249 1 1
19250 1 1
19251 1 1
19252 1 1
19253 1 1
19254 1 1
19255 1 1
19256 1 1
19257 1 1
19258 1 1
19259 1 1
19260 1 1
19261 1 1
19262 1 1
19263 1 1
19264 1 1
19265 1 1
19266 1 1
19267 1 1
19268 1 1
19269 1 1
19270 1 1
19271 1 1
19272 1 1
19273 1 1
19277 1 1
19281 1 1
19285 1 1
19289 1 1
19303 unreachable
19311 1 1
19312 1 1


Cond Coverage for Module : rv_plic_reg_top
TotalCoveredPercent
Conditions2015201099.75
Logical2015201099.75
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
61-1674298.94
16743-16770100.00
16770100.00
16770-17224100.00
17227-17855100.00
17906-1791695.00

Branch Coverage for Module : rv_plic_reg_top
Line No.TotalCoveredPercent
Branches 207 206 99.52
TERNARY 16766 2 2 100.00
IF 71 3 2 66.67
CASE 18129 202 202 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 16766 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T14,T18,T38
0 Covered T14,T15,T16


LineNo. Expression -1-: 71 if ((!rst_ni)) -2-: 73 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T11,T12,T13
0 1 Not Covered
0 0 Covered T11,T12,T13


LineNo. Expression -1-: 18129 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T14,T15,T16
addr_hit[1] Covered T11,T12,T13
addr_hit[2] Covered T11,T12,T13
addr_hit[3] Covered T11,T12,T13
addr_hit[4] Covered T11,T12,T13
addr_hit[5] Covered T11,T12,T13
addr_hit[6] Covered T11,T12,T13
addr_hit[7] Covered T11,T12,T13
addr_hit[8] Covered T11,T12,T13
addr_hit[9] Covered T11,T12,T13
addr_hit[10] Covered T11,T13,T19
addr_hit[11] Covered T11,T12,T13
addr_hit[12] Covered T11,T12,T13
addr_hit[13] Covered T11,T12,T13
addr_hit[14] Covered T11,T12,T13
addr_hit[15] Covered T11,T13,T19
addr_hit[16] Covered T11,T12,T13
addr_hit[17] Covered T11,T12,T13
addr_hit[18] Covered T11,T12,T13
addr_hit[19] Covered T11,T12,T13
addr_hit[20] Covered T11,T12,T13
addr_hit[21] Covered T11,T12,T13
addr_hit[22] Covered T11,T13,T19
addr_hit[23] Covered T11,T12,T13
addr_hit[24] Covered T11,T12,T13
addr_hit[25] Covered T11,T12,T13
addr_hit[26] Covered T11,T13,T19
addr_hit[27] Covered T11,T12,T13
addr_hit[28] Covered T11,T12,T13
addr_hit[29] Covered T11,T12,T13
addr_hit[30] Covered T11,T12,T13
addr_hit[31] Covered T11,T12,T13
addr_hit[32] Covered T11,T12,T13
addr_hit[33] Covered T11,T12,T13
addr_hit[34] Covered T11,T12,T13
addr_hit[35] Covered T11,T12,T13
addr_hit[36] Covered T11,T12,T13
addr_hit[37] Covered T11,T12,T13
addr_hit[38] Covered T11,T12,T13
addr_hit[39] Covered T11,T12,T13
addr_hit[40] Covered T11,T12,T13
addr_hit[41] Covered T11,T12,T13
addr_hit[42] Covered T11,T12,T13
addr_hit[43] Covered T11,T12,T13
addr_hit[44] Covered T11,T12,T13
addr_hit[45] Covered T11,T12,T13
addr_hit[46] Covered T11,T12,T13
addr_hit[47] Covered T11,T12,T13
addr_hit[48] Covered T11,T12,T13
addr_hit[49] Covered T11,T12,T13
addr_hit[50] Covered T11,T12,T13
addr_hit[51] Covered T11,T12,T13
addr_hit[52] Covered T11,T12,T13
addr_hit[53] Covered T11,T12,T13
addr_hit[54] Covered T11,T13,T19
addr_hit[55] Covered T11,T13,T19
addr_hit[56] Covered T11,T12,T13
addr_hit[57] Covered T11,T13,T19
addr_hit[58] Covered T11,T13,T19
addr_hit[59] Covered T11,T12,T13
addr_hit[60] Covered T11,T12,T13
addr_hit[61] Covered T11,T12,T13
addr_hit[62] Covered T11,T12,T13
addr_hit[63] Covered T11,T12,T13
addr_hit[64] Covered T11,T12,T13
addr_hit[65] Covered T11,T12,T13
addr_hit[66] Covered T11,T12,T13
addr_hit[67] Covered T11,T12,T13
addr_hit[68] Covered T11,T12,T13
addr_hit[69] Covered T11,T12,T13
addr_hit[70] Covered T11,T12,T13
addr_hit[71] Covered T11,T12,T13
addr_hit[72] Covered T11,T12,T13
addr_hit[73] Covered T11,T12,T13
addr_hit[74] Covered T11,T12,T13
addr_hit[75] Covered T11,T12,T13
addr_hit[76] Covered T11,T13,T19
addr_hit[77] Covered T11,T12,T13
addr_hit[78] Covered T11,T12,T13
addr_hit[79] Covered T11,T12,T13
addr_hit[80] Covered T11,T12,T13
addr_hit[81] Covered T11,T12,T13
addr_hit[82] Covered T11,T12,T13
addr_hit[83] Covered T11,T12,T13
addr_hit[84] Covered T11,T12,T13
addr_hit[85] Covered T11,T12,T13
addr_hit[86] Covered T11,T12,T13
addr_hit[87] Covered T11,T12,T13
addr_hit[88] Covered T11,T12,T13
addr_hit[89] Covered T11,T12,T13
addr_hit[90] Covered T11,T12,T13
addr_hit[91] Covered T11,T12,T13
addr_hit[92] Covered T11,T12,T13
addr_hit[93] Covered T11,T12,T13
addr_hit[94] Covered T11,T13,T19
addr_hit[95] Covered T11,T12,T13
addr_hit[96] Covered T11,T12,T13
addr_hit[97] Covered T11,T12,T13
addr_hit[98] Covered T11,T12,T13
addr_hit[99] Covered T11,T12,T13
addr_hit[100] Covered T11,T12,T13
addr_hit[101] Covered T11,T13,T19
addr_hit[102] Covered T11,T12,T13
addr_hit[103] Covered T11,T12,T13
addr_hit[104] Covered T11,T12,T13
addr_hit[105] Covered T11,T12,T13
addr_hit[106] Covered T11,T12,T13
addr_hit[107] Covered T11,T12,T13
addr_hit[108] Covered T11,T12,T13
addr_hit[109] Covered T11,T12,T13
addr_hit[110] Covered T11,T12,T13
addr_hit[111] Covered T11,T12,T13
addr_hit[112] Covered T11,T12,T13
addr_hit[113] Covered T11,T12,T13
addr_hit[114] Covered T11,T12,T13
addr_hit[115] Covered T11,T12,T13
addr_hit[116] Covered T11,T12,T13
addr_hit[117] Covered T11,T12,T13
addr_hit[118] Covered T11,T12,T13
addr_hit[119] Covered T11,T12,T13
addr_hit[120] Covered T11,T12,T13
addr_hit[121] Covered T11,T12,T13
addr_hit[122] Covered T11,T12,T13
addr_hit[123] Covered T11,T12,T13
addr_hit[124] Covered T11,T12,T13
addr_hit[125] Covered T11,T12,T13
addr_hit[126] Covered T11,T12,T13
addr_hit[127] Covered T11,T12,T13
addr_hit[128] Covered T11,T12,T13
addr_hit[129] Covered T11,T12,T13
addr_hit[130] Covered T11,T12,T13
addr_hit[131] Covered T11,T12,T13
addr_hit[132] Covered T11,T12,T13
addr_hit[133] Covered T11,T13,T19
addr_hit[134] Covered T11,T13,T19
addr_hit[135] Covered T11,T12,T13
addr_hit[136] Covered T11,T12,T13
addr_hit[137] Covered T11,T12,T13
addr_hit[138] Covered T11,T12,T13
addr_hit[139] Covered T11,T12,T13
addr_hit[140] Covered T11,T12,T13
addr_hit[141] Covered T11,T12,T13
addr_hit[142] Covered T11,T13,T19
addr_hit[143] Covered T11,T12,T13
addr_hit[144] Covered T11,T12,T13
addr_hit[145] Covered T11,T12,T13
addr_hit[146] Covered T11,T12,T13
addr_hit[147] Covered T11,T12,T13
addr_hit[148] Covered T11,T12,T13
addr_hit[149] Covered T11,T12,T13
addr_hit[150] Covered T11,T12,T13
addr_hit[151] Covered T11,T13,T19
addr_hit[152] Covered T11,T12,T13
addr_hit[153] Covered T11,T12,T13
addr_hit[154] Covered T11,T12,T13
addr_hit[155] Covered T11,T13,T19
addr_hit[156] Covered T11,T12,T13
addr_hit[157] Covered T11,T13,T19
addr_hit[158] Covered T11,T12,T13
addr_hit[159] Covered T11,T12,T13
addr_hit[160] Covered T11,T12,T13
addr_hit[161] Covered T11,T12,T13
addr_hit[162] Covered T11,T12,T13
addr_hit[163] Covered T11,T12,T13
addr_hit[164] Covered T11,T12,T13
addr_hit[165] Covered T11,T12,T13
addr_hit[166] Covered T11,T12,T13
addr_hit[167] Covered T11,T12,T13
addr_hit[168] Covered T11,T12,T13
addr_hit[169] Covered T11,T12,T13
addr_hit[170] Covered T11,T12,T13
addr_hit[171] Covered T11,T12,T13
addr_hit[172] Covered T11,T12,T13
addr_hit[173] Covered T11,T12,T13
addr_hit[174] Covered T11,T12,T13
addr_hit[175] Covered T11,T12,T13
addr_hit[176] Covered T11,T12,T13
addr_hit[177] Covered T11,T12,T13
addr_hit[178] Covered T11,T12,T13
addr_hit[179] Covered T11,T12,T13
addr_hit[180] Covered T11,T13,T19
addr_hit[181] Covered T11,T12,T19
addr_hit[182] Covered T11,T13,T19
addr_hit[183] Covered T11,T12,T13
addr_hit[184] Covered T11,T12,T13
addr_hit[185] Covered T11,T12,T13
addr_hit[186] Covered T11,T12,T13
addr_hit[187] Covered T11,T12,T13
addr_hit[188] Covered T11,T12,T13
addr_hit[189] Covered T11,T12,T13
addr_hit[190] Covered T11,T12,T13
addr_hit[191] Covered T11,T12,T13
addr_hit[192] Covered T11,T12,T13
addr_hit[193] Covered T11,T12,T13
addr_hit[194] Covered T11,T12,T13
addr_hit[195] Covered T11,T12,T13
addr_hit[196] Covered T11,T12,T13
addr_hit[197] Covered T11,T12,T13
addr_hit[198] Covered T11,T12,T13
addr_hit[199] Covered T11,T12,T13
addr_hit[200] Covered T11,T13,T19
default Covered T14,T15,T16


Assert Coverage for Module : rv_plic_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 92302202 192436 0 0
reAfterRv 92302202 192436 0 0
rePulse 92302202 147341 0 0
wePulse 92302202 45095 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 92302202 192436 0 0
T11 187147 402 0 0
T12 112459 43 0 0
T13 213446 112 0 0
T19 234320 4558 0 0
T20 222022 543 0 0
T49 107445 205 0 0
T50 199323 118 0 0
T51 153416 64 0 0
T67 102724 201 0 0
T74 85148 34 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 92302202 192436 0 0
T11 187147 402 0 0
T12 112459 43 0 0
T13 213446 112 0 0
T19 234320 4558 0 0
T20 222022 543 0 0
T49 107445 205 0 0
T50 199323 118 0 0
T51 153416 64 0 0
T67 102724 201 0 0
T74 85148 34 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 92302202 147341 0 0
T11 187147 402 0 0
T13 213446 1 0 0
T19 234320 2248 0 0
T20 222022 342 0 0
T21 341071 605 0 0
T22 366772 598 0 0
T35 257918 2106 0 0
T39 0 2183 0 0
T49 107445 201 0 0
T67 102724 201 0 0
T68 172370 0 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 92302202 45095 0 0
T12 112459 43 0 0
T13 213446 111 0 0
T19 234320 2310 0 0
T20 222022 201 0 0
T21 341071 402 0 0
T22 0 402 0 0
T49 107445 4 0 0
T50 199323 118 0 0
T51 153416 64 0 0
T67 102724 0 0 0
T74 85148 34 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%