Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_pwm_aon.u_reg.u_cfg_cdc

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.05	99.16	97.20			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	0	1
145	0	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T73,T71,T19

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T19,T20,T21
1	-	Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22582741	122486	0	0
DstReqKnown_A	239959	205788	0	0
SrcAckBusyChk_A	22582741	302	0	0
SrcBusyKnown_A	22582741	22447745	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	122486	0	0
T19	582923	5026	0	0
T20	54582	420	0	0
T21	83189	625	0	0
T22	89377	815	0	0
T35	645101	987	0	0
T39	741269	7955	0	0
T53	49581	0	0	0
T55	0	5761	0	0
T64	42173	264	0	0
T65	0	1115	0	0
T66	0	317	0	0
T67	26833	0	0	0
T68	42532	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239959	205788	0	0
T11	1871	1147	0	0
T12	543	318	0	0
T13	740	516	0	0
T19	5442	5153	0	0
T20	727	501	0	0
T49	909	621	0	0
T50	686	462	0	0
T51	637	413	0	0
T67	795	508	0	0
T74	437	214	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	302	0	0
T19	582923	13	0	0
T20	54582	1	0	0
T21	83189	2	0	0
T22	89377	2	0	0
T35	645101	3	0	0
T39	741269	18	0	0
T53	49581	0	0	0
T55	0	14	0	0
T64	42173	1	0	0
T65	0	3	0	0
T66	0	1	0	0
T67	26833	0	0	0
T68	42532	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	22447745	0	0
T11	48049	46723	0	0
T12	27978	27325	0	0
T13	52216	51566	0	0
T19	582923	581982	0	0
T20	54582	53622	0	0
T49	27846	26802	0	0
T50	49100	48177	0	0
T51	37843	37157	0	0
T67	26833	25632	0	0
T74	21774	20772	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	0	1
145	0	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T73,T19,T20

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T19,T20,T21
1	-	Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22582741	111636	0	0
DstReqKnown_A	239959	205788	0	0
SrcAckBusyChk_A	22582741	276	0	0
SrcBusyKnown_A	22582741	22447745	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	111636	0	0
T19	582923	6859	0	0
T20	54582	438	0	0
T21	83189	620	0	0
T22	89377	819	0	0
T35	645101	6324	0	0
T39	741269	5014	0	0
T53	49581	0	0	0
T55	0	5832	0	0
T64	42173	348	0	0
T65	0	797	0	0
T66	0	278	0	0
T67	26833	0	0	0
T68	42532	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239959	205788	0	0
T11	1871	1147	0	0
T12	543	318	0	0
T13	740	516	0	0
T19	5442	5153	0	0
T20	727	501	0	0
T49	909	621	0	0
T50	686	462	0	0
T51	637	413	0	0
T67	795	508	0	0
T74	437	214	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	276	0	0
T19	582923	17	0	0
T20	54582	1	0	0
T21	83189	2	0	0
T22	89377	2	0	0
T35	645101	16	0	0
T39	741269	11	0	0
T53	49581	0	0	0
T55	0	14	0	0
T64	42173	1	0	0
T65	0	2	0	0
T66	0	1	0	0
T67	26833	0	0	0
T68	42532	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	22447745	0	0
T11	48049	46723	0	0
T12	27978	27325	0	0
T13	52216	51566	0	0
T19	582923	581982	0	0
T20	54582	53622	0	0
T49	27846	26802	0	0
T50	49100	48177	0	0
T51	37843	37157	0	0
T67	26833	25632	0	0
T74	21774	20772	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	0	1
145	0	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T72,T70,T75

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T19,T20,T21
1	-	Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22582741	114780	0	0
DstReqKnown_A	239959	205788	0	0
SrcAckBusyChk_A	22582741	282	0	0
SrcBusyKnown_A	22582741	22447745	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	114780	0	0
T19	582923	5499	0	0
T20	54582	364	0	0
T21	83189	678	0	0
T22	89377	820	0	0
T35	645101	5953	0	0
T39	741269	8887	0	0
T53	49581	0	0	0
T55	0	6609	0	0
T64	42173	323	0	0
T65	0	827	0	0
T66	0	359	0	0
T67	26833	0	0	0
T68	42532	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239959	205788	0	0
T11	1871	1147	0	0
T12	543	318	0	0
T13	740	516	0	0
T19	5442	5153	0	0
T20	727	501	0	0
T49	909	621	0	0
T50	686	462	0	0
T51	637	413	0	0
T67	795	508	0	0
T74	437	214	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	282	0	0
T19	582923	14	0	0
T20	54582	1	0	0
T21	83189	2	0	0
T22	89377	2	0	0
T35	645101	15	0	0
T39	741269	20	0	0
T53	49581	0	0	0
T55	0	16	0	0
T64	42173	1	0	0
T65	0	2	0	0
T66	0	1	0	0
T67	26833	0	0	0
T68	42532	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	22447745	0	0
T11	48049	46723	0	0
T12	27978	27325	0	0
T13	52216	51566	0	0
T19	582923	581982	0	0
T20	54582	53622	0	0
T49	27846	26802	0	0
T50	49100	48177	0	0
T51	37843	37157	0	0
T67	26833	25632	0	0
T74	21774	20772	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	0	1
145	0	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T19,T20,T21
1	-	Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22582741	120065	0	0
DstReqKnown_A	239959	205788	0	0
SrcAckBusyChk_A	22582741	296	0	0
SrcBusyKnown_A	22582741	22447745	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	120065	0	0
T19	582923	5271	0	0
T20	54582	447	0	0
T21	83189	514	0	0
T22	89377	867	0	0
T35	645101	3166	0	0
T39	741269	8503	0	0
T53	49581	0	0	0
T55	0	4675	0	0
T64	42173	287	0	0
T65	0	1435	0	0
T66	0	247	0	0
T67	26833	0	0	0
T68	42532	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239959	205788	0	0
T11	1871	1147	0	0
T12	543	318	0	0
T13	740	516	0	0
T19	5442	5153	0	0
T20	727	501	0	0
T49	909	621	0	0
T50	686	462	0	0
T51	637	413	0	0
T67	795	508	0	0
T74	437	214	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	296	0	0
T19	582923	13	0	0
T20	54582	1	0	0
T21	83189	2	0	0
T22	89377	2	0	0
T35	645101	8	0	0
T39	741269	19	0	0
T53	49581	0	0	0
T55	0	11	0	0
T64	42173	1	0	0
T65	0	4	0	0
T66	0	1	0	0
T67	26833	0	0	0
T68	42532	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	22447745	0	0
T11	48049	46723	0	0
T12	27978	27325	0	0
T13	52216	51566	0	0
T19	582923	581982	0	0
T20	54582	53622	0	0
T49	27846	26802	0	0
T50	49100	48177	0	0
T51	37843	37157	0	0
T67	26833	25632	0	0
T74	21774	20772	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	0	1
145	0	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T72,T73,T19

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T19,T20,T21
1	-	Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22582741	113981	0	0
DstReqKnown_A	239959	205788	0	0
SrcAckBusyChk_A	22582741	284	0	0
SrcBusyKnown_A	22582741	22447745	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	113981	0	0
T19	582923	1449	0	0
T20	54582	411	0	0
T21	83189	515	0	0
T22	89377	884	0	0
T35	645101	4226	0	0
T39	741269	2229	0	0
T53	49581	0	0	0
T55	0	3468	0	0
T64	42173	287	0	0
T65	0	334	0	0
T66	0	322	0	0
T67	26833	0	0	0
T68	42532	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239959	205788	0	0
T11	1871	1147	0	0
T12	543	318	0	0
T13	740	516	0	0
T19	5442	5153	0	0
T20	727	501	0	0
T49	909	621	0	0
T50	686	462	0	0
T51	637	413	0	0
T67	795	508	0	0
T74	437	214	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	284	0	0
T19	582923	4	0	0
T20	54582	1	0	0
T21	83189	2	0	0
T22	89377	2	0	0
T35	645101	11	0	0
T39	741269	5	0	0
T53	49581	0	0	0
T55	0	8	0	0
T64	42173	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	26833	0	0	0
T68	42532	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	22447745	0	0
T11	48049	46723	0	0
T12	27978	27325	0	0
T13	52216	51566	0	0
T19	582923	581982	0	0
T20	54582	53622	0	0
T49	27846	26802	0	0
T50	49100	48177	0	0
T51	37843	37157	0	0
T67	26833	25632	0	0
T74	21774	20772	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	0	1
145	0	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T76,T70,T19

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T19,T20,T21
1	-	Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22582741	107803	0	0
DstReqKnown_A	239959	205788	0	0
SrcAckBusyChk_A	22582741	267	0	0
SrcBusyKnown_A	22582741	22447745	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	107803	0	0
T19	582923	2229	0	0
T20	54582	413	0	0
T21	83189	540	0	0
T22	89377	820	0	0
T35	645101	4219	0	0
T39	741269	5426	0	0
T53	49581	0	0	0
T55	0	8040	0	0
T64	42173	314	0	0
T65	0	2667	0	0
T66	0	343	0	0
T67	26833	0	0	0
T68	42532	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239959	205788	0	0
T11	1871	1147	0	0
T12	543	318	0	0
T13	740	516	0	0
T19	5442	5153	0	0
T20	727	501	0	0
T49	909	621	0	0
T50	686	462	0	0
T51	637	413	0	0
T67	795	508	0	0
T74	437	214	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	267	0	0
T19	582923	6	0	0
T20	54582	1	0	0
T21	83189	2	0	0
T22	89377	2	0	0
T35	645101	11	0	0
T39	741269	12	0	0
T53	49581	0	0	0
T55	0	19	0	0
T64	42173	1	0	0
T65	0	7	0	0
T66	0	1	0	0
T67	26833	0	0	0
T68	42532	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	22447745	0	0
T11	48049	46723	0	0
T12	27978	27325	0	0
T13	52216	51566	0	0
T19	582923	581982	0	0
T20	54582	53622	0	0
T49	27846	26802	0	0
T50	49100	48177	0	0
T51	37843	37157	0	0
T67	26833	25632	0	0
T74	21774	20772	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	0	1
145	0	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T70,T77,T19

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T19,T20,T21
1	-	Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22582741	94930	0	0
DstReqKnown_A	239959	205788	0	0
SrcAckBusyChk_A	22582741	237	0	0
SrcBusyKnown_A	22582741	22447745	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	94930	0	0
T19	582923	3156	0	0
T20	54582	465	0	0
T21	83189	638	0	0
T22	89377	844	0	0
T35	645101	4242	0	0
T39	741269	6559	0	0
T53	49581	0	0	0
T55	0	2205	0	0
T64	42173	357	0	0
T65	0	2624	0	0
T66	0	253	0	0
T67	26833	0	0	0
T68	42532	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239959	205788	0	0
T11	1871	1147	0	0
T12	543	318	0	0
T13	740	516	0	0
T19	5442	5153	0	0
T20	727	501	0	0
T49	909	621	0	0
T50	686	462	0	0
T51	637	413	0	0
T67	795	508	0	0
T74	437	214	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	237	0	0
T19	582923	8	0	0
T20	54582	1	0	0
T21	83189	2	0	0
T22	89377	2	0	0
T35	645101	11	0	0
T39	741269	15	0	0
T53	49581	0	0	0
T55	0	5	0	0
T64	42173	1	0	0
T65	0	7	0	0
T66	0	1	0	0
T67	26833	0	0	0
T68	42532	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	22447745	0	0
T11	48049	46723	0	0
T12	27978	27325	0	0
T13	52216	51566	0	0
T19	582923	581982	0	0
T20	54582	53622	0	0
T49	27846	26802	0	0
T50	49100	48177	0	0
T51	37843	37157	0	0
T67	26833	25632	0	0
T74	21774	20772	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	0	1
145	0	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T71,T19,T78

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T19,T20,T21
1	-	Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22582741	127110	0	0
DstReqKnown_A	239959	205788	0	0
SrcAckBusyChk_A	22582741	313	0	0
SrcBusyKnown_A	22582741	22447745	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	127110	0	0
T19	582923	5293	0	0
T20	54582	441	0	0
T21	83189	644	0	0
T22	89377	924	0	0
T35	645101	7485	0	0
T39	741269	6607	0	0
T53	49581	0	0	0
T55	0	2298	0	0
T64	42173	283	0	0
T65	0	5553	0	0
T66	0	331	0	0
T67	26833	0	0	0
T68	42532	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239959	205788	0	0
T11	1871	1147	0	0
T12	543	318	0	0
T13	740	516	0	0
T19	5442	5153	0	0
T20	727	501	0	0
T49	909	621	0	0
T50	686	462	0	0
T51	637	413	0	0
T67	795	508	0	0
T74	437	214	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	313	0	0
T19	582923	13	0	0
T20	54582	1	0	0
T21	83189	2	0	0
T22	89377	2	0	0
T35	645101	19	0	0
T39	741269	15	0	0
T53	49581	0	0	0
T55	0	5	0	0
T64	42173	1	0	0
T65	0	14	0	0
T66	0	1	0	0
T67	26833	0	0	0
T68	42532	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	22447745	0	0
T11	48049	46723	0	0
T12	27978	27325	0	0
T13	52216	51566	0	0
T19	582923	581982	0	0
T20	54582	53622	0	0
T49	27846	26802	0	0
T50	49100	48177	0	0
T51	37843	37157	0	0
T67	26833	25632	0	0
T74	21774	20772	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T79,T19,T80

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22582741	110386	0	0
DstReqKnown_A	239959	205788	0	0
SrcAckBusyChk_A	22582741	277	0	0
SrcBusyKnown_A	22582741	22447745	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	110386	0	0
T19	582923	5623	0	0
T20	54582	461	0	0
T21	83189	601	0	0
T22	89377	806	0	0
T35	645101	8233	0	0
T39	741269	6042	0	0
T53	49581	0	0	0
T55	0	4614	0	0
T64	42173	350	0	0
T65	0	737	0	0
T66	0	332	0	0
T67	26833	0	0	0
T68	42532	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239959	205788	0	0
T11	1871	1147	0	0
T12	543	318	0	0
T13	740	516	0	0
T19	5442	5153	0	0
T20	727	501	0	0
T49	909	621	0	0
T50	686	462	0	0
T51	637	413	0	0
T67	795	508	0	0
T74	437	214	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	277	0	0
T19	582923	14	0	0
T20	54582	1	0	0
T21	83189	2	0	0
T22	89377	2	0	0
T35	645101	21	0	0
T39	741269	14	0	0
T53	49581	0	0	0
T55	0	11	0	0
T64	42173	1	0	0
T65	0	2	0	0
T66	0	1	0	0
T67	26833	0	0	0
T68	42532	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	22447745	0	0
T11	48049	46723	0	0
T12	27978	27325	0	0
T13	52216	51566	0	0
T19	582923	581982	0	0
T20	54582	53622	0	0
T49	27846	26802	0	0
T50	49100	48177	0	0
T51	37843	37157	0	0
T67	26833	25632	0	0
T74	21774	20772	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T81,T19,T20

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22582741	97522	0	0
DstReqKnown_A	239959	205788	0	0
SrcAckBusyChk_A	22582741	243	0	0
SrcBusyKnown_A	22582741	22447745	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	97522	0	0
T19	582923	1523	0	0
T20	54582	409	0	0
T21	83189	559	0	0
T22	89377	803	0	0
T35	645101	7658	0	0
T39	741269	3094	0	0
T53	49581	0	0	0
T55	0	1341	0	0
T64	42173	285	0	0
T65	0	1125	0	0
T66	0	258	0	0
T67	26833	0	0	0
T68	42532	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239959	205788	0	0
T11	1871	1147	0	0
T12	543	318	0	0
T13	740	516	0	0
T19	5442	5153	0	0
T20	727	501	0	0
T49	909	621	0	0
T50	686	462	0	0
T51	637	413	0	0
T67	795	508	0	0
T74	437	214	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	243	0	0
T19	582923	4	0	0
T20	54582	1	0	0
T21	83189	2	0	0
T22	89377	2	0	0
T35	645101	19	0	0
T39	741269	7	0	0
T53	49581	0	0	0
T55	0	3	0	0
T64	42173	1	0	0
T65	0	3	0	0
T66	0	1	0	0
T67	26833	0	0	0
T68	42532	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	22447745	0	0
T11	48049	46723	0	0
T12	27978	27325	0	0
T13	52216	51566	0	0
T19	582923	581982	0	0
T20	54582	53622	0	0
T49	27846	26802	0	0
T50	49100	48177	0	0
T51	37843	37157	0	0
T67	26833	25632	0	0
T74	21774	20772	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T73,T82,T71

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22582741	104123	0	0
DstReqKnown_A	239959	205788	0	0
SrcAckBusyChk_A	22582741	260	0	0
SrcBusyKnown_A	22582741	22447745	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	104123	0	0
T19	582923	2742	0	0
T20	54582	468	0	0
T21	83189	531	0	0
T22	89377	830	0	0
T35	645101	3563	0	0
T39	741269	5018	0	0
T53	49581	0	0	0
T55	0	3052	0	0
T64	42173	289	0	0
T65	0	4265	0	0
T66	0	287	0	0
T67	26833	0	0	0
T68	42532	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239959	205788	0	0
T11	1871	1147	0	0
T12	543	318	0	0
T13	740	516	0	0
T19	5442	5153	0	0
T20	727	501	0	0
T49	909	621	0	0
T50	686	462	0	0
T51	637	413	0	0
T67	795	508	0	0
T74	437	214	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	260	0	0
T19	582923	7	0	0
T20	54582	1	0	0
T21	83189	2	0	0
T22	89377	2	0	0
T35	645101	9	0	0
T39	741269	11	0	0
T53	49581	0	0	0
T55	0	7	0	0
T64	42173	1	0	0
T65	0	11	0	0
T66	0	1	0	0
T67	26833	0	0	0
T68	42532	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	22447745	0	0
T11	48049	46723	0	0
T12	27978	27325	0	0
T13	52216	51566	0	0
T19	582923	581982	0	0
T20	54582	53622	0	0
T49	27846	26802	0	0
T50	49100	48177	0	0
T51	37843	37157	0	0
T67	26833	25632	0	0
T74	21774	20772	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T73,T81,T19

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22582741	117652	0	0
DstReqKnown_A	239959	205788	0	0
SrcAckBusyChk_A	22582741	290	0	0
SrcBusyKnown_A	22582741	22447745	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	117652	0	0
T19	582923	5112	0	0
T20	54582	443	0	0
T21	83189	616	0	0
T22	89377	839	0	0
T35	645101	5671	0	0
T39	741269	8837	0	0
T53	49581	0	0	0
T55	0	4372	0	0
T64	42173	327	0	0
T65	0	1812	0	0
T66	0	345	0	0
T67	26833	0	0	0
T68	42532	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239959	205788	0	0
T11	1871	1147	0	0
T12	543	318	0	0
T13	740	516	0	0
T19	5442	5153	0	0
T20	727	501	0	0
T49	909	621	0	0
T50	686	462	0	0
T51	637	413	0	0
T67	795	508	0	0
T74	437	214	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	290	0	0
T19	582923	13	0	0
T20	54582	1	0	0
T21	83189	2	0	0
T22	89377	2	0	0
T35	645101	14	0	0
T39	741269	20	0	0
T53	49581	0	0	0
T55	0	10	0	0
T64	42173	1	0	0
T65	0	5	0	0
T66	0	1	0	0
T67	26833	0	0	0
T68	42532	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	22447745	0	0
T11	48049	46723	0	0
T12	27978	27325	0	0
T13	52216	51566	0	0
T19	582923	581982	0	0
T20	54582	53622	0	0
T49	27846	26802	0	0
T50	49100	48177	0	0
T51	37843	37157	0	0
T67	26833	25632	0	0
T74	21774	20772	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T61,T73,T70

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22582741	115574	0	0
DstReqKnown_A	239959	205788	0	0
SrcAckBusyChk_A	22582741	285	0	0
SrcBusyKnown_A	22582741	22447745	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	115574	0	0
T19	582923	2436	0	0
T20	54582	422	0	0
T21	83189	539	0	0
T22	89377	833	0	0
T35	645101	4719	0	0
T39	741269	7090	0	0
T53	49581	0	0	0
T55	0	7127	0	0
T64	42173	359	0	0
T65	0	1485	0	0
T66	0	305	0	0
T67	26833	0	0	0
T68	42532	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239959	205788	0	0
T11	1871	1147	0	0
T12	543	318	0	0
T13	740	516	0	0
T19	5442	5153	0	0
T20	727	501	0	0
T49	909	621	0	0
T50	686	462	0	0
T51	637	413	0	0
T67	795	508	0	0
T74	437	214	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	285	0	0
T19	582923	6	0	0
T20	54582	1	0	0
T21	83189	2	0	0
T22	89377	2	0	0
T35	645101	12	0	0
T39	741269	16	0	0
T53	49581	0	0	0
T55	0	17	0	0
T64	42173	1	0	0
T65	0	4	0	0
T66	0	1	0	0
T67	26833	0	0	0
T68	42532	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	22447745	0	0
T11	48049	46723	0	0
T12	27978	27325	0	0
T13	52216	51566	0	0
T19	582923	581982	0	0
T20	54582	53622	0	0
T49	27846	26802	0	0
T50	49100	48177	0	0
T51	37843	37157	0	0
T67	26833	25632	0	0
T74	21774	20772	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T14,T73,T81

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22582741	98150	0	0
DstReqKnown_A	239959	205788	0	0
SrcAckBusyChk_A	22582741	243	0	0
SrcBusyKnown_A	22582741	22447745	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	98150	0	0
T19	582923	5237	0	0
T20	54582	443	0	0
T21	83189	678	0	0
T22	89377	809	0	0
T35	645101	1945	0	0
T39	741269	5358	0	0
T53	49581	0	0	0
T55	0	2926	0	0
T64	42173	307	0	0
T65	0	1850	0	0
T66	0	353	0	0
T67	26833	0	0	0
T68	42532	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239959	205788	0	0
T11	1871	1147	0	0
T12	543	318	0	0
T13	740	516	0	0
T19	5442	5153	0	0
T20	727	501	0	0
T49	909	621	0	0
T50	686	462	0	0
T51	637	413	0	0
T67	795	508	0	0
T74	437	214	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	243	0	0
T19	582923	13	0	0
T20	54582	1	0	0
T21	83189	2	0	0
T22	89377	2	0	0
T35	645101	5	0	0
T39	741269	12	0	0
T53	49581	0	0	0
T55	0	7	0	0
T64	42173	1	0	0
T65	0	5	0	0
T66	0	1	0	0
T67	26833	0	0	0
T68	42532	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	22447745	0	0
T11	48049	46723	0	0
T12	27978	27325	0	0
T13	52216	51566	0	0
T19	582923	581982	0	0
T20	54582	53622	0	0
T49	27846	26802	0	0
T50	49100	48177	0	0
T51	37843	37157	0	0
T67	26833	25632	0	0
T74	21774	20772	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T79,T19,T83

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22582741	96353	0	0
DstReqKnown_A	239959	205788	0	0
SrcAckBusyChk_A	22582741	241	0	0
SrcBusyKnown_A	22582741	22447745	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	96353	0	0
T19	582923	4310	0	0
T20	54582	405	0	0
T21	83189	601	0	0
T22	89377	836	0	0
T35	645101	1791	0	0
T39	741269	4524	0	0
T53	49581	0	0	0
T55	0	1754	0	0
T64	42173	338	0	0
T65	0	4009	0	0
T66	0	310	0	0
T67	26833	0	0	0
T68	42532	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239959	205788	0	0
T11	1871	1147	0	0
T12	543	318	0	0
T13	740	516	0	0
T19	5442	5153	0	0
T20	727	501	0	0
T49	909	621	0	0
T50	686	462	0	0
T51	637	413	0	0
T67	795	508	0	0
T74	437	214	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	241	0	0
T19	582923	11	0	0
T20	54582	1	0	0
T21	83189	2	0	0
T22	89377	2	0	0
T35	645101	5	0	0
T39	741269	10	0	0
T53	49581	0	0	0
T55	0	4	0	0
T64	42173	1	0	0
T65	0	10	0	0
T66	0	1	0	0
T67	26833	0	0	0
T68	42532	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	22447745	0	0
T11	48049	46723	0	0
T12	27978	27325	0	0
T13	52216	51566	0	0
T19	582923	581982	0	0
T20	54582	53622	0	0
T49	27846	26802	0	0
T50	49100	48177	0	0
T51	37843	37157	0	0
T67	26833	25632	0	0
T74	21774	20772	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T14,T84,T19

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T19,T20,T21
1	1	Covered	T19,T20,T21

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T19,T20,T21
0	0	1	Covered	T19,T20,T21
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	22582741	117321	0	0
DstReqKnown_A	239959	205788	0	0
SrcAckBusyChk_A	22582741	291	0	0
SrcBusyKnown_A	22582741	22447745	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	117321	0	0
T19	582923	5123	0	0
T20	54582	399	0	0
T21	83189	654	0	0
T22	89377	759	0	0
T35	645101	5925	0	0
T39	741269	6062	0	0
T53	49581	0	0	0
T55	0	4251	0	0
T64	42173	308	0	0
T65	0	1439	0	0
T66	0	259	0	0
T67	26833	0	0	0
T68	42532	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239959	205788	0	0
T11	1871	1147	0	0
T12	543	318	0	0
T13	740	516	0	0
T19	5442	5153	0	0
T20	727	501	0	0
T49	909	621	0	0
T50	686	462	0	0
T51	637	413	0	0
T67	795	508	0	0
T74	437	214	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	291	0	0
T19	582923	13	0	0
T20	54582	1	0	0
T21	83189	2	0	0
T22	89377	2	0	0
T35	645101	15	0	0
T39	741269	14	0	0
T53	49581	0	0	0
T55	0	10	0	0
T64	42173	1	0	0
T65	0	4	0	0
T66	0	1	0	0
T67	26833	0	0	0
T68	42532	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22582741	22447745	0	0
T11	48049	46723	0	0
T12	27978	27325	0	0
T13	52216	51566	0	0
T19	582923	581982	0	0
T20	54582	53622	0	0
T49	27846	26802	0	0
T50	49100	48177	0	0
T51	37843	37157	0	0
T67	26833	25632	0	0
T74	21774	20772	0	0