Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3556761	1			T14	1955		T15	535		T16	12520
values[2]	722842	1			T15	178		T16	1926		T29	154
values[3]	102795	1			T15	37		T16	65		T29	1
values[4]	53668	1			T16	43		T53	107		T207	429
values[5]	36175	1			T16	51		T53	92		T207	264
values[6]	26764	1			T16	29		T53	75		T207	161
values[7]	21442	1			T16	25		T53	53		T207	120
values[8]	18101	1			T16	26		T53	14		T207	51
values[9]	16508	1			T16	40		T53	22		T207	36
values[10]	15018	1			T16	50		T53	16		T207	22
values[11]	14361	1			T16	25		T53	9		T207	16
values[12]	13409	1			T16	34		T53	5		T207	18
values[13]	12526	1			T16	27		T53	5		T207	11
values[14]	12142	1			T16	16		T53	1		T207	16
values[15]	11908	1			T16	17		T207	17		T303	6
values[16]	11384	1			T16	17		T207	21		T303	6
values[17]	10837	1			T16	23		T207	42		T303	6
values[18]	10561	1			T16	11		T207	15		T303	6
values[19]	10243	1			T16	16		T207	6		T303	6
values[20]	9870	1			T16	27		T207	6		T303	6
values[21]	9601	1			T16	39		T207	8		T303	6
values[22]	9366	1			T16	31		T207	4		T303	7
values[23]	8982	1			T16	36		T207	7		T303	6
values[24]	8834	1			T16	19		T207	7		T303	6
values[25]	8472	1			T16	18		T207	15		T303	6
values[26]	8194	1			T16	24		T207	22		T303	6
values[27]	7826	1			T16	10		T207	6		T303	6
values[28]	7412	1			T16	12		T207	8		T303	6
values[29]	6782	1			T16	10		T207	7		T303	6
values[30]	6307	1			T16	8		T207	11		T303	6
values[31]	5830	1			T16	11		T207	6		T303	6
values[32]	5436	1			T16	12		T207	1		T303	6
values[33]	5278	1			T16	17		T207	1		T303	6
values[34]	4738	1			T16	14		T207	8		T303	6
values[35]	4380	1			T16	14		T207	5		T303	6
values[36]	4169	1			T16	6		T207	4		T303	6
values[37]	3968	1			T16	7		T207	2		T303	6
values[38]	3879	1			T16	7		T207	5		T303	7
values[39]	3752	1			T16	7		T207	1		T303	6
values[40]	3613	1			T16	1		T207	1		T303	6
values[41]	3436	1			T16	1		T207	3		T303	6
values[42]	3392	1			T16	1		T207	6		T303	6
values[43]	3308	1			T207	3		T303	6		T71	7
values[44]	3266	1			T207	1		T303	7		T71	6
values[45]	3199	1			T207	2		T303	6		T71	5
values[46]	3093	1			T207	3		T303	6		T71	12
values[47]	3041	1			T207	3		T303	6		T71	6
values[48]	2999	1			T207	2		T303	6		T71	6
values[49]	2931	1			T207	2		T303	7		T71	5
values[50]	2885	1			T207	1		T303	6		T71	11
values[51]	2797	1			T207	3		T303	6		T71	1
values[52]	2764	1			T207	1		T303	6		T71	4
values[53]	2732	1			T207	1		T303	6		T308	2
values[54]	2595	1			T207	1		T303	6		T308	2
values[55]	2566	1			T207	2		T303	7		T308	2
values[56]	2544	1			T207	7		T303	6		T308	2
values[57]	2518	1			T207	2		T303	6		T308	2
values[58]	2490	1			T207	1		T303	6		T308	2
values[59]	2484	1			T207	1		T303	6		T308	2
values[60]	2445	1			T207	4		T303	6		T308	2
values[61]	2715	1			T207	16		T303	7		T308	2
values[62]	4294	1			T207	28		T303	6		T308	2
values[63]	16785	1			T207	35		T303	73		T308	3
values[64]	232145	1			T207	38		T303	1097		T308	403

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4583485	1			T14	2007		T15	690		T16	14955
values[2]	762971	1			T15	223		T16	2814		T29	182
values[3]	73965	1			T15	49		T16	89		T29	9
values[4]	13717	1			T15	14		T16	9		T29	4
values[5]	5292	1			T15	5		T16	2		T29	1
values[6]	3230	1			T15	1		T55	1		T207	30
values[7]	2335	1			T15	1		T55	1		T207	26
values[8]	1952	1			T15	2		T55	1		T207	9
values[9]	1729	1			T207	9		T303	1		T71	2
values[10]	1521	1			T207	8		T303	1		T71	2
values[11]	1488	1			T207	11		T303	1		T71	3
values[12]	1417	1			T207	22		T303	1		T71	2
values[13]	1363	1			T207	15		T303	1		T71	2
values[14]	1262	1			T207	11		T303	1		T71	2
values[15]	1082	1			T207	20		T303	1		T71	2
values[16]	1040	1			T207	18		T303	1		T71	2
values[17]	968	1			T207	13		T303	1		T71	3
values[18]	939	1			T207	15		T303	1		T71	2
values[19]	870	1			T207	14		T303	1		T71	2
values[20]	790	1			T207	5		T303	1		T71	2
values[21]	781	1			T303	1		T71	2		T78	8
values[22]	708	1			T303	1		T71	2		T78	17
values[23]	681	1			T303	1		T71	2		T78	8
values[24]	692	1			T303	1		T71	2		T78	4
values[25]	737	1			T303	1		T71	2		T78	8
values[26]	734	1			T303	1		T71	2		T78	5
values[27]	673	1			T303	1		T71	2		T78	8
values[28]	596	1			T303	1		T71	2		T78	11
values[29]	606	1			T303	1		T71	2		T78	5
values[30]	631	1			T303	1		T71	2		T78	6
values[31]	621	1			T303	1		T71	2		T78	3
values[32]	579	1			T303	1		T71	2		T78	7
values[33]	532	1			T303	1		T71	2		T78	6
values[34]	528	1			T303	1		T71	2		T78	5
values[35]	507	1			T303	1		T71	2		T78	2
values[36]	529	1			T303	1		T71	2		T78	8
values[37]	524	1			T303	1		T71	2		T78	7
values[38]	480	1			T303	1		T71	2		T78	7
values[39]	466	1			T303	1		T71	2		T78	8
values[40]	416	1			T303	1		T71	2		T78	6
values[41]	470	1			T303	1		T71	1		T78	3
values[42]	431	1			T303	1		T78	1		T81	1
values[43]	420	1			T303	1		T78	1		T81	1
values[44]	413	1			T303	1		T78	1		T81	6
values[45]	414	1			T303	1		T78	1		T81	8
values[46]	425	1			T303	1		T78	1		T81	5
values[47]	424	1			T303	1		T78	2		T81	2
values[48]	429	1			T303	1		T78	4		T81	1
values[49]	456	1			T303	1		T78	3		T81	1
values[50]	427	1			T303	1		T78	5		T81	1
values[51]	393	1			T303	1		T78	1		T81	3
values[52]	377	1			T303	1		T78	1		T81	1
values[53]	429	1			T303	1		T78	1		T81	4
values[54]	388	1			T303	1		T78	1		T81	2
values[55]	372	1			T303	1		T78	1		T81	1
values[56]	335	1			T303	1		T78	3		T81	1
values[57]	366	1			T303	1		T78	1		T81	2
values[58]	391	1			T303	1		T78	2		T81	1
values[59]	328	1			T303	1		T78	1		T81	1
values[60]	348	1			T303	1		T78	2		T81	1
values[61]	391	1			T303	1		T78	3		T81	1
values[62]	589	1			T303	1		T78	4		T81	2
values[63]	2739	1			T303	12		T78	18		T81	11
values[64]	28308	1			T303	153		T78	71		T81	102

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	581879	1			T14	1968		T15	6		T16	1607
values[2]	2518269	1			T15	86		T16	11006		T29	592
values[3]	1119898	1			T15	581		T16	1763		T29	155
values[4]	137201	1			T15	151		T16	92		T53	133
values[5]	70582	1			T15	4		T16	62		T53	58
values[6]	46081	1			T16	28		T53	43		T207	386
values[7]	33596	1			T16	20		T53	11		T207	284
values[8]	26328	1			T16	47		T53	9		T207	169
values[9]	22404	1			T16	39		T53	2		T207	94
values[10]	19805	1			T16	36		T207	88		T303	6
values[11]	17910	1			T16	19		T207	48		T303	6
values[12]	16580	1			T16	40		T207	12		T303	6
values[13]	15442	1			T16	28		T207	7		T303	6
values[14]	14657	1			T16	18		T207	7		T303	6
values[15]	14228	1			T16	20		T207	13		T303	6
values[16]	13282	1			T16	31		T207	6		T303	6
values[17]	12508	1			T16	33		T207	4		T303	6
values[18]	12246	1			T16	28		T207	1		T303	6
values[19]	11836	1			T16	35		T207	5		T303	6
values[20]	11549	1			T16	28		T207	3		T303	6
values[21]	11249	1			T16	14		T207	2		T303	6
values[22]	10748	1			T16	24		T207	1		T303	6
values[23]	10233	1			T16	41		T207	4		T303	6
values[24]	9811	1			T16	13		T207	3		T303	6
values[25]	9806	1			T16	14		T207	1		T303	6
values[26]	9118	1			T16	11		T207	2		T303	6
values[27]	8700	1			T16	22		T207	4		T303	6
values[28]	8247	1			T16	32		T207	1		T303	6
values[29]	7561	1			T16	33		T207	3		T303	6
values[30]	7114	1			T16	22		T207	2		T303	6
values[31]	6885	1			T16	16		T207	1		T303	6
values[32]	6445	1			T16	18		T207	2		T303	6
values[33]	5678	1			T16	18		T207	4		T303	6
values[34]	5192	1			T16	10		T207	1		T303	6
values[35]	4951	1			T16	9		T207	1		T303	6
values[36]	4600	1			T16	4		T207	8		T303	6
values[37]	4334	1			T16	8		T207	3		T303	6
values[38]	4062	1			T16	3		T207	2		T303	6
values[39]	3872	1			T16	2		T207	1		T303	6
values[40]	3833	1			T16	3		T207	3		T303	6
values[41]	3802	1			T16	4		T207	4		T303	6
values[42]	3581	1			T16	5		T207	3		T303	6
values[43]	3526	1			T16	5		T207	5		T303	6
values[44]	3441	1			T16	4		T207	4		T303	6
values[45]	3386	1			T16	4		T207	4		T303	6
values[46]	3244	1			T16	4		T207	4		T303	7
values[47]	3157	1			T16	1		T207	1		T303	6
values[48]	3164	1			T16	1		T207	2		T303	6
values[49]	3111	1			T16	1		T207	2		T303	6
values[50]	3047	1			T207	6		T303	6		T71	6
values[51]	2927	1			T207	4		T303	7		T71	3
values[52]	2943	1			T207	5		T303	6		T71	7
values[53]	2898	1			T207	10		T303	6		T71	1
values[54]	2833	1			T207	4		T303	6		T71	4
values[55]	2852	1			T207	2		T303	6		T71	3
values[56]	2824	1			T207	2		T303	6		T71	4
values[57]	2710	1			T207	2		T303	6		T71	4
values[58]	2752	1			T207	1		T303	6		T71	8
values[59]	2613	1			T207	5		T303	7		T71	3
values[60]	2505	1			T207	2		T303	6		T71	3
values[61]	2727	1			T207	5		T303	6		T71	1
values[62]	4092	1			T207	16		T303	6		T71	3
values[63]	21468	1			T207	37		T303	8		T308	2
values[64]	220053	1			T207	56		T303	1128		T308	454