Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1052022	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1747892

1

T11

1338

T12

4004

T13

2534

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2161251	1			T11	2351		T12	6017		T13	4677
values[0x0]	303516	1			T11	49		T12	2239		T13	61
values[0x1]	335147	1			T11	60		T12	2342		T13	70

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	780889	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2019025

1

T11

1713

T12

5789

T13

3277

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	43901	1			T11	31		T12	180		T13	95
valid_sources[0x01]	44537	1			T11	35		T12	227		T13	92
valid_sources[0x02]	43031	1			T11	51		T12	141		T13	90
valid_sources[0x03]	43486	1			T11	46		T12	174		T13	102
valid_sources[0x04]	44454	1			T11	26		T12	165		T13	57
valid_sources[0x05]	43980	1			T11	44		T12	114		T13	92
valid_sources[0x06]	44393	1			T11	50		T12	125		T13	68
valid_sources[0x07]	43697	1			T11	40		T12	181		T13	54
valid_sources[0x08]	43930	1			T11	44		T12	192		T13	104
valid_sources[0x09]	42768	1			T11	47		T12	142		T13	70
valid_sources[0x0a]	43586	1			T11	35		T12	149		T13	61
valid_sources[0x0b]	43110	1			T11	37		T12	160		T13	64
valid_sources[0x0c]	43071	1			T11	51		T12	191		T13	40
valid_sources[0x0d]	44462	1			T11	43		T12	149		T13	90
valid_sources[0x0e]	44116	1			T11	40		T12	130		T13	75
valid_sources[0x0f]	44022	1			T11	32		T12	158		T13	71
valid_sources[0x10]	44129	1			T11	38		T12	130		T13	130
valid_sources[0x11]	43711	1			T11	45		T12	144		T13	91
valid_sources[0x12]	43596	1			T11	37		T12	130		T13	122
valid_sources[0x13]	44363	1			T11	27		T12	135		T13	71
valid_sources[0x14]	42993	1			T11	42		T12	95		T13	45
valid_sources[0x15]	44603	1			T11	41		T12	107		T13	56
valid_sources[0x16]	43739	1			T11	36		T12	164		T13	72
valid_sources[0x17]	43235	1			T11	30		T12	120		T13	54
valid_sources[0x18]	43650	1			T11	34		T12	188		T13	50
valid_sources[0x19]	43623	1			T11	32		T12	160		T13	61
valid_sources[0x1a]	44855	1			T11	32		T12	222		T13	107
valid_sources[0x1b]	43879	1			T11	51		T12	136		T13	64
valid_sources[0x1c]	43370	1			T11	49		T12	238		T13	72
valid_sources[0x1d]	43812	1			T11	29		T12	124		T13	130
valid_sources[0x1e]	43579	1			T11	34		T12	216		T13	76
valid_sources[0x1f]	43618	1			T11	39		T12	194		T13	52
valid_sources[0x20]	43752	1			T11	31		T12	170		T13	87

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1243490

1

T11

1229

T12

1512

T13

2403

values[0x0]

all_enables

biggest_size

260309

1

T11

49

T12

1341

T13

61

values[0x1]

all_enables

biggest_size

244093

1

T11

60

T12

1151

T13

70

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2805006	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

442630

1

T14

260

T15

98

T16

2095

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1098376	1			T14	628		T15	266		T16	5048
values[0x0]	1049504	1			T14	660		T15	248		T16	5133
values[0x1]	1099756	1			T14	667		T15	236		T16	5101

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2172652	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1074984

1

T14

651

T15

232

T16

4923

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	50646	1			T14	16		T15	10		T16	300
valid_sources[0x01]	50456	1			T15	11		T16	265		T29	7
valid_sources[0x02]	50602	1			T14	33		T15	9		T16	185
valid_sources[0x03]	51697	1			T14	20		T15	10		T16	200
valid_sources[0x04]	51172	1			T14	15		T15	9		T16	243
valid_sources[0x05]	51116	1			T14	14		T15	12		T16	241
valid_sources[0x06]	50754	1			T14	14		T15	15		T16	191
valid_sources[0x07]	50044	1			T14	43		T15	16		T16	252
valid_sources[0x08]	50822	1			T14	57		T15	9		T16	313
valid_sources[0x09]	51321	1			T15	13		T16	225		T29	9
valid_sources[0x0a]	50875	1			T14	9		T15	10		T16	333
valid_sources[0x0b]	50374	1			T15	17		T16	211		T29	14
valid_sources[0x0c]	50516	1			T14	13		T15	8		T16	195
valid_sources[0x0d]	51106	1			T14	15		T15	13		T16	226
valid_sources[0x0e]	51519	1			T15	8		T16	290		T29	35
valid_sources[0x0f]	50871	1			T15	9		T16	201		T29	27
valid_sources[0x10]	49881	1			T14	44		T15	16		T16	183
valid_sources[0x11]	50135	1			T14	35		T15	12		T16	188
valid_sources[0x12]	51510	1			T14	57		T15	13		T16	285
valid_sources[0x13]	50526	1			T14	26		T15	10		T16	301
valid_sources[0x14]	51372	1			T14	20		T15	11		T16	321
valid_sources[0x15]	49970	1			T14	28		T15	7		T16	272
valid_sources[0x16]	50548	1			T14	21		T15	11		T16	217
valid_sources[0x17]	50663	1			T14	6		T15	14		T16	200
valid_sources[0x18]	49111	1			T14	59		T15	9		T16	223
valid_sources[0x19]	50731	1			T14	53		T15	13		T16	281
valid_sources[0x1a]	51074	1			T14	9		T15	11		T16	282
valid_sources[0x1b]	49706	1			T14	16		T15	11		T16	247
valid_sources[0x1c]	51023	1			T14	30		T15	14		T16	225
valid_sources[0x1d]	49317	1			T14	62		T15	14		T16	282
valid_sources[0x1e]	51057	1			T14	34		T15	21		T16	249
valid_sources[0x1f]	51500	1			T14	5		T15	13		T16	274
valid_sources[0x20]	50904	1			T14	40		T15	11		T16	195

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46746

1

T14

18

T15

10

T16

227

values[0x0]

all_enables

biggest_size

349769

1

T14

215

T15

79

T16

1681

values[0x1]

all_enables

biggest_size

46115

1

T14

27

T15

9

T16

187

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2973010	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

484470

1

T14

293

T15

147

T16

2496

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1182307	1			T14	687		T15	346		T16	6058
values[0x0]	1091341	1			T14	661		T15	332		T16	5891
values[0x1]	1183832	1			T14	659		T15	307		T16	5916

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2282684	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1174796

1

T14

679

T15

334

T16

5949

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54684	1			T14	16		T15	14		T16	338
valid_sources[0x01]	54763	1			T15	15		T16	282		T29	11
valid_sources[0x02]	54292	1			T14	27		T15	13		T16	357
valid_sources[0x03]	54122	1			T14	16		T15	21		T16	208
valid_sources[0x04]	53493	1			T14	14		T15	15		T16	226
valid_sources[0x05]	53863	1			T14	20		T15	16		T16	312
valid_sources[0x06]	54134	1			T14	15		T15	15		T16	217
valid_sources[0x07]	54116	1			T14	33		T15	18		T16	250
valid_sources[0x08]	53806	1			T14	67		T15	13		T16	320
valid_sources[0x09]	54151	1			T15	16		T16	299		T29	19
valid_sources[0x0a]	53009	1			T14	16		T15	10		T16	349
valid_sources[0x0b]	54254	1			T15	14		T16	350		T29	10
valid_sources[0x0c]	52925	1			T14	14		T15	18		T16	350
valid_sources[0x0d]	54042	1			T14	5		T15	17		T16	192
valid_sources[0x0e]	54209	1			T15	16		T16	418		T29	10
valid_sources[0x0f]	54344	1			T15	13		T16	176		T29	22
valid_sources[0x10]	54377	1			T14	42		T15	19		T16	214
valid_sources[0x11]	54417	1			T14	36		T15	10		T16	149
valid_sources[0x12]	55332	1			T14	66		T15	27		T16	332
valid_sources[0x13]	53284	1			T14	28		T15	8		T16	435
valid_sources[0x14]	53998	1			T14	11		T15	17		T16	373
valid_sources[0x15]	54100	1			T14	20		T15	12		T16	229
valid_sources[0x16]	53491	1			T14	34		T15	17		T16	263
valid_sources[0x17]	53677	1			T14	7		T15	9		T16	249
valid_sources[0x18]	53689	1			T14	57		T15	22		T16	390
valid_sources[0x19]	54552	1			T14	49		T15	17		T16	337
valid_sources[0x1a]	54239	1			T14	18		T15	18		T16	298
valid_sources[0x1b]	53272	1			T14	19		T15	14		T16	241
valid_sources[0x1c]	53630	1			T14	43		T15	16		T16	103
valid_sources[0x1d]	53462	1			T14	59		T15	15		T16	229
valid_sources[0x1e]	53487	1			T14	25		T15	22		T16	242
valid_sources[0x1f]	53474	1			T14	13		T15	26		T16	281
valid_sources[0x20]	54603	1			T14	39		T15	16		T16	295

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

50632

1

T14

34

T15

13

T16

235

values[0x0]

all_enables

biggest_size

382667

1

T14

228

T15

120

T16

2008

values[0x1]

all_enables

biggest_size

51171

1

T14

31

T15

14

T16

253

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2823100	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

446737

1

T14

272

T15

112

T16

2099

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1107035	1			T14	638		T15	280		T16	5133
values[0x0]	1057512	1			T14	667		T15	255		T16	4995
values[0x1]	1105290	1			T14	663		T15	293		T16	5178

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2186106	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1083731

1

T14

627

T15

287

T16

5108

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51003	1			T14	6		T15	32		T16	299
valid_sources[0x01]	51713	1			T15	2		T16	247		T29	21
valid_sources[0x02]	51215	1			T14	15		T15	12		T16	188
valid_sources[0x03]	51601	1			T14	17		T15	11		T16	270
valid_sources[0x04]	50528	1			T14	5		T15	12		T16	234
valid_sources[0x05]	50691	1			T14	12		T15	9		T16	246
valid_sources[0x06]	51628	1			T14	8		T15	37		T16	220
valid_sources[0x07]	51977	1			T14	42		T15	8		T16	237
valid_sources[0x08]	51007	1			T14	64		T15	7		T16	253
valid_sources[0x09]	52040	1			T15	8		T16	320		T29	13
valid_sources[0x0a]	51192	1			T14	15		T15	19		T16	323
valid_sources[0x0b]	51729	1			T15	1		T16	225		T29	16
valid_sources[0x0c]	51075	1			T14	19		T15	7		T16	210
valid_sources[0x0d]	51773	1			T14	8		T15	13		T16	205
valid_sources[0x0e]	50934	1			T15	13		T16	286		T29	5
valid_sources[0x0f]	52014	1			T15	8		T16	230		T29	2
valid_sources[0x10]	50408	1			T14	56		T15	15		T16	186
valid_sources[0x11]	49421	1			T14	52		T15	5		T16	241
valid_sources[0x12]	51929	1			T14	55		T15	12		T16	280
valid_sources[0x13]	49618	1			T14	29		T15	34		T16	260
valid_sources[0x14]	51085	1			T14	32		T15	7		T16	323
valid_sources[0x15]	50901	1			T14	29		T15	6		T16	244
valid_sources[0x16]	51395	1			T14	30		T15	17		T16	201
valid_sources[0x17]	50992	1			T14	19		T15	6		T16	206
valid_sources[0x18]	49813	1			T14	49		T15	9		T16	210
valid_sources[0x19]	50932	1			T14	51		T15	35		T16	265
valid_sources[0x1a]	51062	1			T14	16		T15	3		T16	280
valid_sources[0x1b]	49604	1			T14	19		T15	12		T16	223
valid_sources[0x1c]	49763	1			T14	32		T15	18		T16	205
valid_sources[0x1d]	50157	1			T14	56		T15	19		T16	229
valid_sources[0x1e]	51459	1			T14	23		T15	8		T16	251
valid_sources[0x1f]	50810	1			T14	9		T15	20		T16	268
valid_sources[0x20]	51664	1			T14	23		T15	8		T16	240

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46570

1

T14

27

T15

14

T16

214

values[0x0]

all_enables

biggest_size

353592

1

T14

211

T15

90

T16

1705

values[0x1]

all_enables

biggest_size

46575

1

T14

34

T15

8

T16

180