Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : otbn
SCORELINECONDTOGGLEFSMBRANCHASSERT
76.26 76.26

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_otbn_0.1/rtl/otbn.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_otbn 76.89 76.89


Module Instance : tb.dut.top_earlgrey.u_otbn

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
76.89 76.89


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
76.89 76.89


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
84.02 68.10 83.95 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : otbn
TotalCoveredPercent
Totals 63 39 61.90
Total Bits 2452 1870 76.26
Total Bits 0->1 1226 935 76.26
Total Bits 1->0 1226 935 76.26

Ports 63 39 61.90
Port Bits 2452 1870 76.26
Port Bits 0->1 1226 935 76.26
Port Bits 1->0 1226 935 76.26

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
rst_ni Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
tl_i.d_ready Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_mask[3:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_address[17:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_address[19:18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20] Yes Yes *T14,*T15,*T16 Yes T14,T15,T16 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T14,*T15,*T16 Yes T14,T15,T16 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T14,*T15,*T16 Yes T14,T15,T16 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_valid Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_o.a_ready Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_error Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_data[31:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_sink Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_source[5:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T14,*T15,*T16 Yes T14,T15,T16 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
idle_o[3:0] Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
intr_done_o Yes Yes T20 Yes T20 OUTPUT
alert_rx_i[0].ack_n Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
alert_rx_i[0].ack_p Yes Yes T12,T17,T18 Yes T12,T17,T18 INPUT
alert_rx_i[0].ping_n No No No INPUT
alert_rx_i[0].ping_p No No No INPUT
alert_rx_i[1].ack_n Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
alert_rx_i[1].ack_p Yes Yes T12,T19,T17 Yes T12,T19,T17 INPUT
alert_rx_i[1].ping_n No No No INPUT
alert_rx_i[1].ping_p No No No INPUT
alert_tx_o[0].alert_n Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
alert_tx_o[0].alert_p Yes Yes T12,T17,T18 Yes T12,T17,T18 OUTPUT
alert_tx_o[1].alert_n Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
alert_tx_o[1].alert_p Yes Yes T12,T19,T17 Yes T12,T19,T17 OUTPUT
lc_escalate_en_i[3:0] No No No INPUT
lc_rma_req_i[3:0] No No No INPUT
lc_rma_ack_o[3:0] No No No OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
clk_edn_i Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
rst_edn_ni Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
edn_rnd_o.edn_req No No No OUTPUT
edn_rnd_i.edn_bus[31:0] No No No INPUT
edn_rnd_i.edn_fips No No No INPUT
edn_rnd_i.edn_ack No No No INPUT
edn_urnd_o.edn_req Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
edn_urnd_i.edn_bus[31:0] No No No INPUT
edn_urnd_i.edn_fips No No No INPUT
edn_urnd_i.edn_ack No No No INPUT
clk_otp_i Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
rst_otp_ni Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
otbn_otp_key_o.req No No No OUTPUT
otbn_otp_key_i.seed_valid No No No INPUT
otbn_otp_key_i.nonce[63:0] No No No INPUT
otbn_otp_key_i.key[127:0] No No No INPUT
otbn_otp_key_i.ack No No No INPUT
keymgr_key_i.key[1:0][383:0] Yes Yes T12,T17,T18 Yes T12,T17,T18 INPUT
keymgr_key_i.valid No No No INPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_otbn
TotalCoveredPercent
Totals 59 39 66.10
Total Bits 2432 1870 76.89
Total Bits 0->1 1216 935 76.89
Total Bits 1->0 1216 935 76.89

Ports 59 39 66.10
Port Bits 2432 1870 76.89
Port Bits 0->1 1216 935 76.89
Port Bits 1->0 1216 935 76.89

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
rst_ni Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
tl_i.d_ready Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_mask[3:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_address[17:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_address[19:18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20] Yes Yes *T14,*T15,*T16 Yes T14,T15,T16 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T14,*T15,*T16 Yes T14,T15,T16 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T14,*T15,*T16 Yes T14,T15,T16 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_i.a_valid Yes Yes T14,T15,T16 Yes T14,T15,T16 INPUT
tl_o.a_ready Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_error Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_data[31:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_sink Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_source[5:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T14,*T15,*T16 Yes T14,T15,T16 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT
idle_o[3:0] Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
intr_done_o Yes Yes T20 Yes T20 OUTPUT
alert_rx_i[0].ack_n Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
alert_rx_i[0].ack_p Yes Yes T12,T17,T18 Yes T12,T17,T18 INPUT
alert_rx_i[0].ping_n No No No INPUT
alert_rx_i[0].ping_p No No No INPUT
alert_rx_i[1].ack_n Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
alert_rx_i[1].ack_p Yes Yes T12,T19,T17 Yes T12,T19,T17 INPUT
alert_rx_i[1].ping_n No No No INPUT
alert_rx_i[1].ping_p No No No INPUT
alert_tx_o[0].alert_n Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
alert_tx_o[0].alert_p Yes Yes T12,T17,T18 Yes T12,T17,T18 OUTPUT
alert_tx_o[1].alert_n Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
alert_tx_o[1].alert_p Yes Yes T12,T19,T17 Yes T12,T19,T17 OUTPUT
lc_escalate_en_i[3:0] No No No INPUT
lc_rma_req_i[3:0] No No No INPUT
lc_rma_ack_o[3:0] No No No OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg[3:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg_en[0:0] Excluded Excluded Excluded INPUT [LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
clk_edn_i Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
rst_edn_ni Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
edn_rnd_o.edn_req No No No OUTPUT
edn_rnd_i.edn_bus[31:0] No No No INPUT
edn_rnd_i.edn_fips No No No INPUT
edn_rnd_i.edn_ack No No No INPUT
edn_urnd_o.edn_req Yes Yes T11,T12,T13 Yes T11,T12,T13 OUTPUT
edn_urnd_i.edn_bus[31:0] No No No INPUT
edn_urnd_i.edn_fips No No No INPUT
edn_urnd_i.edn_ack No No No INPUT
clk_otp_i Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
rst_otp_ni Yes Yes T11,T12,T13 Yes T11,T12,T13 INPUT
otbn_otp_key_o.req No No No OUTPUT
otbn_otp_key_i.seed_valid No No No INPUT
otbn_otp_key_i.nonce[63:0] No No No INPUT
otbn_otp_key_i.key[127:0] No No No INPUT
otbn_otp_key_i.ack No No No INPUT
keymgr_key_i.key[1:0][383:0] Yes Yes T12,T17,T18 Yes T12,T17,T18 INPUT
keymgr_key_i.valid No No No INPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%