Unified Coverage Report :: Module :: adc_ctrl

Module : adc_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.74			90.74

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_adc_ctrl_aon	90.74			90.74

---

Module Instance : tb.dut.top_earlgrey.u_adc_ctrl_aon

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.74			90.74

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.74			90.74

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.02	68.10		83.95			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : adc_ctrl

	Total	Covered	Percent
Totals	37	31	83.78
Total Bits	324	294	90.74
Total Bits 0->1	162	147	90.74
Total Bits 1->0	162	147	90.74

Ports	37	31	83.78
Port Bits	324	294	90.74
Port Bits 0->1	162	147	90.74
Port Bits 1->0	162	147	90.74

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
clk_aon_i	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
rst_ni	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
rst_aon_ni	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
tl_i.d_ready	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[6:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[17:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18]	Yes	Yes	*T14,*T15,*T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[21:19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[22]	Yes	Yes	*T14,*T15,*T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T14,*T15,*T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_valid	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_o.a_ready	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_error	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_sink	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T14,*T15,*T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T12,T17,T18	Yes	T12,T17,T18	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T12,T17,T18	Yes	T12,T17,T18	OUTPUT
adc_o.pd	Yes	Yes	T21,T20	Yes	T21,T20	OUTPUT
adc_o.channel_sel[0]	Yes	Yes	*T21,*T20	Yes	T21,T20	OUTPUT
adc_o.channel_sel[1]	No	No		No		OUTPUT
adc_i.data_valid	No	No		No		INPUT
adc_i.data[9:0]	No	No		No		INPUT
intr_match_done_o	Yes	Yes	T21,T22	Yes	T21,T22	OUTPUT
wkup_req_o	No	No		No		OUTPUT

*Tests covering at least one bit in the range