Unified Coverage Report :: Module :: usbdev

Module : usbdev

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
86.19			86.19

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_usbdev	95.26			95.26

---

Module Instance : tb.dut.top_earlgrey.u_usbdev

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.26			95.26

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.26			95.26

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.02	68.10		83.95			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : usbdev

	Total	Covered	Percent
Totals	77	60	77.92
Total Bits	420	362	86.19
Total Bits 0->1	210	181	86.19
Total Bits 1->0	210	181	86.19

Ports	77	60	77.92
Port Bits	420	362	86.19
Port Bits 0->1	210	181	86.19
Port Bits 1->0	210	181	86.19

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
rst_ni	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
clk_aon_i	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
rst_aon_ni	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
tl_i.d_ready	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[11:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[16:12]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T14,*T15,*T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[19:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[21:20]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[29:22]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T14,*T15,*T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_valid	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_o.a_ready	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_error	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_sink	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T14,*T15,*T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T12,T19,T17	Yes	T12,T19,T17	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T12,T19,T17	Yes	T12,T19,T17	OUTPUT
cio_usb_dp_i	Yes	Yes	T12,T17,T18	Yes	T12,T17,T18	INPUT
cio_usb_dn_i	Yes	Yes	T12,T17,T18	Yes	T12,T17,T18	INPUT
usb_rx_d_i	Yes	Yes	T12,T17,T18	Yes	T12,T17,T18	INPUT
cio_usb_dp_o	Yes	Yes	T12,T17,T18	Yes	T12,T17,T18	OUTPUT
cio_usb_dp_en_o	Yes	Yes	T12,T17,T18	Yes	T12,T17,T18	OUTPUT
cio_usb_dn_o	Yes	Yes	T12,T17,T18	Yes	T12,T17,T18	OUTPUT
cio_usb_dn_en_o	Yes	Yes	T12,T17,T18	Yes	T12,T17,T18	OUTPUT
usb_tx_se0_o	Yes	Yes	T19,T21	Yes	T19,T21	OUTPUT
usb_tx_d_o	Yes	Yes	T12,T19,T17	Yes	T12,T19,T17	OUTPUT
cio_sense_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
usb_dp_pullup_o	Yes	Yes	T19,T22	Yes	T19,T22	OUTPUT
usb_dn_pullup_o	Yes	Yes	T21,T20	Yes	T21,T20	OUTPUT
usb_rx_enable_o	Yes	Yes	T12,T17,T18	Yes	T12,T17,T18	OUTPUT
usb_tx_use_d_se0_o	Yes	Yes	T12,T18,T33	Yes	T12,T18,T33	OUTPUT
usb_aon_suspend_req_o	Yes	Yes	T21,T20	Yes	T21,T20	OUTPUT
usb_aon_wake_ack_o	Yes	Yes	T19,T17,T21	Yes	T19,T17,T21	OUTPUT
usb_aon_bus_reset_i	No	No		No		INPUT
usb_aon_sense_lost_i	Yes	Yes	T21,T20	Yes	T21,T20	INPUT
usb_aon_wake_detect_active_i	Yes	Yes	T21,T20	Yes	T21,T20	INPUT
usb_ref_val_o	No	No		No		OUTPUT
usb_ref_pulse_o	No	No		No		OUTPUT
ram_cfg_i.b_ram_lcfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.b_ram_lcfg.cfg_en	No	No		No		INPUT
ram_cfg_i.a_ram_lcfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.a_ram_lcfg.cfg_en	No	No		No		INPUT
ram_cfg_i.b_ram_fcfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.b_ram_fcfg.cfg_en	No	No		No		INPUT
ram_cfg_i.a_ram_fcfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.a_ram_fcfg.cfg_en	No	No		No		INPUT
intr_pkt_received_o	Yes	Yes	T21,T20	Yes	T21,T20	OUTPUT
intr_pkt_sent_o	Yes	Yes	T19	Yes	T19	OUTPUT
intr_powered_o	Yes	Yes	T28,T22,T51	Yes	T28,T22,T51	OUTPUT
intr_disconnected_o	Yes	Yes	T12,T18,T33	Yes	T12,T18,T33	OUTPUT
intr_host_lost_o	Yes	Yes	T19,T28	Yes	T19,T28	OUTPUT
intr_link_reset_o	Yes	Yes	T28,T20	Yes	T28,T20	OUTPUT
intr_link_suspend_o	Yes	Yes	T28	Yes	T28	OUTPUT
intr_link_resume_o	Yes	Yes	T19,T22,T20	Yes	T19,T22,T20	OUTPUT
intr_av_empty_o	No	No		No		OUTPUT
intr_rx_full_o	Yes	Yes	T20	Yes	T20	OUTPUT
intr_av_overflow_o	Yes	Yes	T20	Yes	T20	OUTPUT
intr_link_in_err_o	Yes	Yes	T28,T20	Yes	T28,T20	OUTPUT
intr_link_out_err_o	Yes	Yes	T20	Yes	T20	OUTPUT
intr_rx_crc_err_o	No	No		No		OUTPUT
intr_rx_pid_err_o	No	No		No		OUTPUT
intr_rx_bitstuff_err_o	No	No		No		OUTPUT
intr_frame_o	Yes	Yes	T21,T22	Yes	T21,T22	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_usbdev

	Total	Covered	Percent
Totals	69	60	86.96
Total Bits	380	362	95.26
Total Bits 0->1	190	181	95.26
Total Bits 1->0	190	181	95.26

Ports	69	60	86.96
Port Bits	380	362	95.26
Port Bits 0->1	190	181	95.26
Port Bits 1->0	190	181	95.26

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
rst_ni	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
clk_aon_i	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
rst_aon_ni	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
tl_i.d_ready	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[11:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[16:12]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T14,*T15,*T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[19:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[21:20]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[29:22]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T14,*T15,*T16	Yes	T14,T15,T16	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_i.a_valid	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	INPUT
tl_o.a_ready	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_error	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_sink	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T14,*T15,*T16	Yes	T14,T15,T16	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T14,T15,T16	Yes	T14,T15,T16	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T12,T19,T17	Yes	T12,T19,T17	INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T12,T19,T17	Yes	T12,T19,T17	OUTPUT
cio_usb_dp_i	Yes	Yes	T12,T17,T18	Yes	T12,T17,T18	INPUT
cio_usb_dn_i	Yes	Yes	T12,T17,T18	Yes	T12,T17,T18	INPUT
usb_rx_d_i	Yes	Yes	T12,T17,T18	Yes	T12,T17,T18	INPUT
cio_usb_dp_o	Yes	Yes	T12,T17,T18	Yes	T12,T17,T18	OUTPUT
cio_usb_dp_en_o	Yes	Yes	T12,T17,T18	Yes	T12,T17,T18	OUTPUT
cio_usb_dn_o	Yes	Yes	T12,T17,T18	Yes	T12,T17,T18	OUTPUT
cio_usb_dn_en_o	Yes	Yes	T12,T17,T18	Yes	T12,T17,T18	OUTPUT
usb_tx_se0_o	Yes	Yes	T19,T21	Yes	T19,T21	OUTPUT
usb_tx_d_o	Yes	Yes	T12,T19,T17	Yes	T12,T19,T17	OUTPUT
cio_sense_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
usb_dp_pullup_o	Yes	Yes	T19,T22	Yes	T19,T22	OUTPUT
usb_dn_pullup_o	Yes	Yes	T21,T20	Yes	T21,T20	OUTPUT
usb_rx_enable_o	Yes	Yes	T12,T17,T18	Yes	T12,T17,T18	OUTPUT
usb_tx_use_d_se0_o	Yes	Yes	T12,T18,T33	Yes	T12,T18,T33	OUTPUT
usb_aon_suspend_req_o	Yes	Yes	T21,T20	Yes	T21,T20	OUTPUT
usb_aon_wake_ack_o	Yes	Yes	T19,T17,T21	Yes	T19,T17,T21	OUTPUT
usb_aon_bus_reset_i	No	No		No		INPUT
usb_aon_sense_lost_i	Yes	Yes	T21,T20	Yes	T21,T20	INPUT
usb_aon_wake_detect_active_i	Yes	Yes	T21,T20	Yes	T21,T20	INPUT
usb_ref_val_o	No	No		No		OUTPUT
usb_ref_pulse_o	No	No		No		OUTPUT
ram_cfg_i.b_ram_lcfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.b_ram_lcfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_lcfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_lcfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.b_ram_fcfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.b_ram_fcfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_fcfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.a_ram_fcfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
intr_pkt_received_o	Yes	Yes	T21,T20	Yes	T21,T20	OUTPUT
intr_pkt_sent_o	Yes	Yes	T19	Yes	T19	OUTPUT
intr_powered_o	Yes	Yes	T28,T22,T51	Yes	T28,T22,T51	OUTPUT
intr_disconnected_o	Yes	Yes	T12,T18,T33	Yes	T12,T18,T33	OUTPUT
intr_host_lost_o	Yes	Yes	T19,T28	Yes	T19,T28	OUTPUT
intr_link_reset_o	Yes	Yes	T28,T20	Yes	T28,T20	OUTPUT
intr_link_suspend_o	Yes	Yes	T28	Yes	T28	OUTPUT
intr_link_resume_o	Yes	Yes	T19,T22,T20	Yes	T19,T22,T20	OUTPUT
intr_av_empty_o	No	No		No		OUTPUT
intr_rx_full_o	Yes	Yes	T20	Yes	T20	OUTPUT
intr_av_overflow_o	Yes	Yes	T20	Yes	T20	OUTPUT
intr_link_in_err_o	Yes	Yes	T28,T20	Yes	T28,T20	OUTPUT
intr_link_out_err_o	Yes	Yes	T20	Yes	T20	OUTPUT
intr_rx_crc_err_o	No	No		No		OUTPUT
intr_rx_pid_err_o	No	No		No		OUTPUT
intr_rx_bitstuff_err_o	No	No		No		OUTPUT
intr_frame_o	Yes	Yes	T21,T22	Yes	T21,T22	OUTPUT

*Tests covering at least one bit in the range