Unified Coverage Report :: Module :: prim_esc_receiver

Module : prim_esc_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71			85.71

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_esc_0/rtl/prim_esc_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_esc_receiver	85.71			85.71

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_esc_receiver

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71			85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.71			85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
42.58	30.59	14.29	62.34		58.33	47.37	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_esc_receiver

	Total	Covered	Percent
Totals	7	6	85.71
Total Bits	14	12	85.71
Total Bits 0->1	7	6	85.71
Total Bits 1->0	7	6	85.71

Ports	7	6	85.71
Port Bits	14	12	85.71
Port Bits 0->1	7	6	85.71
Port Bits 1->0	7	6	85.71

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
esc_req_o	No	No		No		OUTPUT
esc_rx_o.resp_n	Yes	Yes	T26	Yes	T26	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T26	Yes	T26	OUTPUT
esc_tx_i.esc_n	Yes	Yes	T26	Yes	T26	INPUT
esc_tx_i.esc_p	Yes	Yes	T26	Yes	T26	INPUT

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_esc_receiver

	Total	Covered	Percent
Totals	7	6	85.71
Total Bits	14	12	85.71
Total Bits 0->1	7	6	85.71
Total Bits 1->0	7	6	85.71

Ports	7	6	85.71
Port Bits	14	12	85.71
Port Bits 0->1	7	6	85.71
Port Bits 1->0	7	6	85.71

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
esc_req_o	No	No		No		OUTPUT
esc_rx_o.resp_n	Yes	Yes	T26	Yes	T26	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T26	Yes	T26	OUTPUT
esc_tx_i.esc_n	Yes	Yes	T26	Yes	T26	INPUT
esc_tx_i.esc_p	Yes	Yes	T26	Yes	T26	INPUT