Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.03	99.16	97.14			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.03	99.16	97.14			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.03	99.16	97.14			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.03	99.16	97.14			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.03	99.16	97.14			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.03	99.16	97.14			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.03	99.16	97.14			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.03	99.16	97.14			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	71.43			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.40	94.74	69.01			89.83	80.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.03	99.16	97.14			99.83	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	73.04	92.86	63.27			86.05	50.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T12,T57,T19

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T12,T19,T17
1	1	Covered	T12,T19,T17

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T12,T19,T17

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T12,T19,T17
1	1	Covered	T12,T19,T17

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T12,T19,T17
0	0	1	Covered	T12,T19,T17
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T12,T19,T17
0	0	1	Covered	T12,T19,T17
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	24770002	111015	0	0
DstReqKnown_A	255884	222028	0	0
SrcAckBusyChk_A	24770002	277	0	0
SrcBusyKnown_A	24770002	24630603	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24770002	111015	0	0
T12	84515	683	0	0
T17	301875	2116	0	0
T18	318218	728	0	0
T30	90703	848	0	0
T32	223526	26176	0	0
T33	327078	825	0	0
T35	36694	0	0	0
T39	75475	550	0	0
T45	339008	4265	0	0
T47	0	650	0	0
T56	78988	796	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	255884	222028	0	0
T11	858	534	0	0
T12	948	722	0	0
T13	1803	1260	0	0
T17	2779	2556	0	0
T18	3022	2800	0	0
T19	348	126	0	0
T32	18876	18650	0	0
T35	646	421	0	0
T44	1479	958	0	0
T59	305	80	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24770002	277	0	0
T12	84515	2	0	0
T17	301875	5	0	0
T18	318218	2	0	0
T30	90703	2	0	0
T32	223526	64	0	0
T33	327078	2	0	0
T35	36694	0	0	0
T39	75475	2	0	0
T45	339008	10	0	0
T47	0	2	0	0
T56	78988	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24770002	24630603	0	0
T11	27791	26539	0	0
T12	84515	83413	0	0
T13	49204	48013	0	0
T17	301875	301030	0	0
T18	318218	317704	0	0
T19	17951	16515	0	0
T32	223526	223419	0	0
T35	36694	36069	0	0
T44	69894	66258	0	0
T59	11255	9829	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T31,T12,T19

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T12,T19,T17
1	1	Covered	T12,T19,T17

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T12,T19,T17

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T12,T19,T17
1	1	Covered	T12,T19,T17

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T12,T19,T17
0	0	1	Covered	T12,T19,T17
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T12,T19,T17
0	0	1	Covered	T12,T19,T17
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	24770002	107401	0	0
DstReqKnown_A	255884	222028	0	0
SrcAckBusyChk_A	24770002	268	0	0
SrcBusyKnown_A	24770002	24630603	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24770002	107401	0	0
T12	84515	685	0	0
T17	301875	1109	0	0
T18	318218	271	0	0
T30	90703	893	0	0
T32	223526	26142	0	0
T33	327078	3225	0	0
T35	36694	0	0	0
T39	75475	689	0	0
T45	339008	2175	0	0
T47	0	721	0	0
T56	78988	719	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	255884	222028	0	0
T11	858	534	0	0
T12	948	722	0	0
T13	1803	1260	0	0
T17	2779	2556	0	0
T18	3022	2800	0	0
T19	348	126	0	0
T32	18876	18650	0	0
T35	646	421	0	0
T44	1479	958	0	0
T59	305	80	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24770002	268	0	0
T12	84515	2	0	0
T17	301875	3	0	0
T18	318218	1	0	0
T30	90703	2	0	0
T32	223526	64	0	0
T33	327078	8	0	0
T35	36694	0	0	0
T39	75475	2	0	0
T45	339008	5	0	0
T47	0	2	0	0
T56	78988	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24770002	24630603	0	0
T11	27791	26539	0	0
T12	84515	83413	0	0
T13	49204	48013	0	0
T17	301875	301030	0	0
T18	318218	317704	0	0
T19	17951	16515	0	0
T32	223526	223419	0	0
T35	36694	36069	0	0
T44	69894	66258	0	0
T59	11255	9829	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T12,T69,T65

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T12,T19,T17
1	1	Covered	T12,T19,T17

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T12,T19,T17

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T12,T19,T17
1	1	Covered	T12,T19,T17

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T12,T19,T17
0	0	1	Covered	T12,T19,T17
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T12,T19,T17
0	0	1	Covered	T12,T19,T17
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	24770002	107233	0	0
DstReqKnown_A	255884	222028	0	0
SrcAckBusyChk_A	24770002	271	0	0
SrcBusyKnown_A	24770002	24630603	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24770002	107233	0	0
T12	84515	689	0	0
T17	301875	3329	0	0
T18	318218	3798	0	0
T30	90703	773	0	0
T32	223526	26186	0	0
T33	327078	1491	0	0
T35	36694	0	0	0
T39	75475	580	0	0
T45	339008	720	0	0
T47	0	727	0	0
T56	78988	676	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	255884	222028	0	0
T11	858	534	0	0
T12	948	722	0	0
T13	1803	1260	0	0
T17	2779	2556	0	0
T18	3022	2800	0	0
T19	348	126	0	0
T32	18876	18650	0	0
T35	646	421	0	0
T44	1479	958	0	0
T59	305	80	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24770002	271	0	0
T12	84515	2	0	0
T17	301875	8	0	0
T18	318218	10	0	0
T30	90703	2	0	0
T32	223526	64	0	0
T33	327078	4	0	0
T35	36694	0	0	0
T39	75475	2	0	0
T45	339008	2	0	0
T47	0	2	0	0
T56	78988	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24770002	24630603	0	0
T11	27791	26539	0	0
T12	84515	83413	0	0
T13	49204	48013	0	0
T17	301875	301030	0	0
T18	318218	317704	0	0
T19	17951	16515	0	0
T32	223526	223419	0	0
T35	36694	36069	0	0
T44	69894	66258	0	0
T59	11255	9829	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T12,T70,T19

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T12,T19,T17
1	1	Covered	T12,T19,T17

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T12,T19,T17

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T12,T19,T17
1	1	Covered	T12,T19,T17

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T12,T19,T17
0	0	1	Covered	T12,T19,T17
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T12,T19,T17
0	0	1	Covered	T12,T19,T17
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	24770002	104140	0	0
DstReqKnown_A	255884	222028	0	0
SrcAckBusyChk_A	24770002	262	0	0
SrcBusyKnown_A	24770002	24630603	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24770002	104140	0	0
T12	84515	677	0	0
T17	301875	3255	0	0
T18	318218	2682	0	0
T30	90703	839	0	0
T32	223526	26110	0	0
T33	327078	827	0	0
T35	36694	0	0	0
T39	75475	658	0	0
T45	339008	435	0	0
T47	0	745	0	0
T56	78988	692	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	255884	222028	0	0
T11	858	534	0	0
T12	948	722	0	0
T13	1803	1260	0	0
T17	2779	2556	0	0
T18	3022	2800	0	0
T19	348	126	0	0
T32	18876	18650	0	0
T35	646	421	0	0
T44	1479	958	0	0
T59	305	80	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24770002	262	0	0
T12	84515	2	0	0
T17	301875	8	0	0
T18	318218	7	0	0
T30	90703	2	0	0
T32	223526	64	0	0
T33	327078	2	0	0
T35	36694	0	0	0
T39	75475	2	0	0
T45	339008	1	0	0
T47	0	2	0	0
T56	78988	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24770002	24630603	0	0
T11	27791	26539	0	0
T12	84515	83413	0	0
T13	49204	48013	0	0
T17	301875	301030	0	0
T18	318218	317704	0	0
T19	17951	16515	0	0
T32	223526	223419	0	0
T35	36694	36069	0	0
T44	69894	66258	0	0
T59	11255	9829	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T12,T57,T19

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T12,T19,T17
1	1	Covered	T12,T19,T17

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T12,T19,T17

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T12,T19,T17
1	1	Covered	T12,T19,T17

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T12,T19,T17
0	0	1	Covered	T12,T19,T17
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T12,T19,T17
0	0	1	Covered	T12,T19,T17
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	24770002	94174	0	0
DstReqKnown_A	255884	222028	0	0
SrcAckBusyChk_A	24770002	239	0	0
SrcBusyKnown_A	24770002	24630603	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24770002	94174	0	0
T12	84515	671	0	0
T17	301875	1170	0	0
T18	318218	2682	0	0
T30	90703	815	0	0
T32	223526	26187	0	0
T33	327078	3244	0	0
T35	36694	0	0	0
T39	75475	676	0	0
T45	339008	2681	0	0
T47	0	712	0	0
T56	78988	680	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	255884	222028	0	0
T11	858	534	0	0
T12	948	722	0	0
T13	1803	1260	0	0
T17	2779	2556	0	0
T18	3022	2800	0	0
T19	348	126	0	0
T32	18876	18650	0	0
T35	646	421	0	0
T44	1479	958	0	0
T59	305	80	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24770002	239	0	0
T12	84515	2	0	0
T17	301875	3	0	0
T18	318218	7	0	0
T30	90703	2	0	0
T32	223526	64	0	0
T33	327078	8	0	0
T35	36694	0	0	0
T39	75475	2	0	0
T45	339008	6	0	0
T47	0	2	0	0
T56	78988	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24770002	24630603	0	0
T11	27791	26539	0	0
T12	84515	83413	0	0
T13	49204	48013	0	0
T17	301875	301030	0	0
T18	318218	317704	0	0
T19	17951	16515	0	0
T32	223526	223419	0	0
T35	36694	36069	0	0
T44	69894	66258	0	0
T59	11255	9829	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T12,T19,T64

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T12,T19,T17
1	1	Covered	T12,T19,T17

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T12,T19,T17

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T12,T19,T17
1	1	Covered	T12,T19,T17

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T12,T19,T17
0	0	1	Covered	T12,T19,T17
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T12,T19,T17
0	0	1	Covered	T12,T19,T17
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	24770002	111964	0	0
DstReqKnown_A	255884	222028	0	0
SrcAckBusyChk_A	24770002	281	0	0
SrcBusyKnown_A	24770002	24630603	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24770002	111964	0	0
T12	84515	766	0	0
T17	301875	3700	0	0
T18	318218	3542	0	0
T30	90703	875	0	0
T32	223526	26115	0	0
T33	327078	1457	0	0
T35	36694	0	0	0
T39	75475	554	0	0
T45	339008	5573	0	0
T47	0	686	0	0
T56	78988	780	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	255884	222028	0	0
T11	858	534	0	0
T12	948	722	0	0
T13	1803	1260	0	0
T17	2779	2556	0	0
T18	3022	2800	0	0
T19	348	126	0	0
T32	18876	18650	0	0
T35	646	421	0	0
T44	1479	958	0	0
T59	305	80	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24770002	281	0	0
T12	84515	2	0	0
T17	301875	9	0	0
T18	318218	9	0	0
T30	90703	2	0	0
T32	223526	64	0	0
T33	327078	4	0	0
T35	36694	0	0	0
T39	75475	2	0	0
T45	339008	13	0	0
T47	0	2	0	0
T56	78988	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24770002	24630603	0	0
T11	27791	26539	0	0
T12	84515	83413	0	0
T13	49204	48013	0	0
T17	301875	301030	0	0
T18	318218	317704	0	0
T19	17951	16515	0	0
T32	223526	223419	0	0
T35	36694	36069	0	0
T44	69894	66258	0	0
T59	11255	9829	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T71,T12,T69

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T12,T19,T17
1	1	Covered	T12,T19,T17

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T12,T19,T17

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T12,T19,T17
1	1	Covered	T12,T19,T17

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T12,T19,T17
0	0	1	Covered	T12,T19,T17
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T12,T19,T17
0	0	1	Covered	T12,T19,T17
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	24770002	95850	0	0
DstReqKnown_A	255884	222028	0	0
SrcAckBusyChk_A	24770002	241	0	0
SrcBusyKnown_A	24770002	24630603	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24770002	95850	0	0
T12	84515	647	0	0
T17	301875	5056	0	0
T30	90703	771	0	0
T32	223526	26139	0	0
T33	327078	1944	0	0
T35	36694	0	0	0
T39	75475	601	0	0
T45	339008	2617	0	0
T47	86723	715	0	0
T56	78988	729	0	0
T58	0	2997	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	255884	222028	0	0
T11	858	534	0	0
T12	948	722	0	0
T13	1803	1260	0	0
T17	2779	2556	0	0
T18	3022	2800	0	0
T19	348	126	0	0
T32	18876	18650	0	0
T35	646	421	0	0
T44	1479	958	0	0
T59	305	80	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24770002	241	0	0
T12	84515	2	0	0
T17	301875	12	0	0
T30	90703	2	0	0
T32	223526	64	0	0
T33	327078	5	0	0
T35	36694	0	0	0
T39	75475	2	0	0
T45	339008	6	0	0
T47	86723	2	0	0
T56	78988	2	0	0
T58	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24770002	24630603	0	0
T11	27791	26539	0	0
T12	84515	83413	0	0
T13	49204	48013	0	0
T17	301875	301030	0	0
T18	318218	317704	0	0
T19	17951	16515	0	0
T32	223526	223419	0	0
T35	36694	36069	0	0
T44	69894	66258	0	0
T59	11255	9829	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T12,T19,T64

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T12,T19,T17
1	1	Covered	T12,T19,T17

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Unreachable
1	0	Covered	T12,T19,T17

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T12,T19,T17
1	1	Covered	T12,T19,T17

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T12,T19,T17
0	0	1	Covered	T12,T19,T17
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T12,T19,T17
0	0	1	Covered	T12,T19,T17
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	24770002	119970	0	0
DstReqKnown_A	255884	222028	0	0
SrcAckBusyChk_A	24770002	300	0	0
SrcBusyKnown_A	24770002	24630603	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24770002	119970	0	0
T12	84515	639	0	0
T17	301875	1139	0	0
T18	318218	4627	0	0
T30	90703	811	0	0
T32	223526	26211	0	0
T33	327078	2320	0	0
T35	36694	0	0	0
T39	75475	564	0	0
T45	339008	2979	0	0
T47	0	724	0	0
T56	78988	773	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	255884	222028	0	0
T11	858	534	0	0
T12	948	722	0	0
T13	1803	1260	0	0
T17	2779	2556	0	0
T18	3022	2800	0	0
T19	348	126	0	0
T32	18876	18650	0	0
T35	646	421	0	0
T44	1479	958	0	0
T59	305	80	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24770002	300	0	0
T12	84515	2	0	0
T17	301875	3	0	0
T18	318218	12	0	0
T30	90703	2	0	0
T32	223526	64	0	0
T33	327078	6	0	0
T35	36694	0	0	0
T39	75475	2	0	0
T45	339008	7	0	0
T47	0	2	0	0
T56	78988	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24770002	24630603	0	0
T11	27791	26539	0	0
T12	84515	83413	0	0
T13	49204	48013	0	0
T17	301875	301030	0	0
T18	318218	317704	0	0
T19	17951	16515	0	0
T32	223526	223419	0	0
T35	36694	36069	0	0
T44	69894	66258	0	0
T59	11255	9829	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Total	Covered	Percent
Conditions	14	10	71.43
Logical	14	10	71.43
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T15,T16
0	1	Unreachable
1	0	Covered	T72,T12,T57

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T15,T16
1	0	Covered	T12,T19,T17
1	1	Covered	T12,T19,T17

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T13
0	1	Not Covered
1	0	Covered	T12,T19,T17

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T12,T19,T17
1	1	Covered	T12,T19,T17

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T12,T19,T17
0	0	1	Covered	T12,T19,T17
0	0	0	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T11,T12,T13
0	1	-	Covered	T12,T19,T17
0	0	1	Covered	T12,T19,T17
0	0	0	Covered	T11,T12,T13

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	24770002	116990	0	0
DstReqKnown_A	255884	222028	0	0
SrcAckBusyChk_A	24770002	242	0	0
SrcBusyKnown_A	24770002	24630603	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24770002	116990	0	0
T12	84515	696	0	0
T17	301875	314	0	0
T18	318218	342	0	0
T30	90703	817	0	0
T32	223526	33817	0	0
T33	327078	5746	0	0
T35	36694	0	0	0
T39	75475	587	0	0
T45	339008	4830	0	0
T47	0	645	0	0
T56	78988	677	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	255884	222028	0	0
T11	858	534	0	0
T12	948	722	0	0
T13	1803	1260	0	0
T17	2779	2556	0	0
T18	3022	2800	0	0
T19	348	126	0	0
T32	18876	18650	0	0
T35	646	421	0	0
T44	1479	958	0	0
T59	305	80	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24770002	242	0	0
T12	84515	2	0	0
T17	301875	1	0	0
T18	318218	1	0	0
T30	90703	2	0	0
T32	223526	64	0	0
T33	327078	11	0	0
T35	36694	0	0	0
T39	75475	2	0	0
T45	339008	9	0	0
T47	0	2	0	0
T56	78988	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24770002	24630603	0	0
T11	27791	26539	0	0
T12	84515	83413	0	0
T13	49204	48013	0	0
T17	301875	301030	0	0
T18	318218	317704	0	0
T19	17951	16515	0	0
T32	223526	223419	0	0
T35	36694	36069	0	0
T44	69894	66258	0	0
T59	11255	9829	0	0