Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo	75.00	50.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	145272435	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	21086	21086	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	145272435	0	0
T1	289574	12569	0	0
T2	225800	5221	0	0
T3	322416	15141	0	0
T19	1100613	250864	0	0
T20	2092125	904087	0	0
T21	594546	25739	0	0
T22	635046	298221	0	0
T29	106680	25	0	0
T38	499656	55490	0	0
T63	282026	11734	0	0
T64	272946	6652	0	0
T65	308368	13952	0	0
T66	265342	5749	0	0
T67	362464	17955	0	0
T68	311936	15185	0	0
T69	230214	7707	0	0
T90	909344	109816	0	0
T104	501548	50477	0	0
T106	467724	59650	0	0
T136	426478	302353	0	0
T137	150442	14459	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1447870	1446160	0	0
T2	1129000	1127250	0	0
T3	1612080	1610400	0	0
T29	640080	639072	0	0
T30	1083000	1081686	0	0
T31	666768	665766	0	0
T56	1577712	1577640	0	0
T57	1627428	1627332	0	0
T59	2201946	2201268	0	0
T63	1410130	1408380	0	0
T64	545892	545208	0	0
T65	616736	616080	0	0
T66	530684	529940	0	0
T67	724928	724228	0	0
T68	623872	623188	0	0
T69	460428	459744	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1447870	1446160	0	0
T2	1129000	1127250	0	0
T3	1612080	1610400	0	0
T29	640080	639072	0	0
T30	1083000	1081686	0	0
T31	666768	665766	0	0
T56	1577712	1577640	0	0
T57	1627428	1627332	0	0
T59	2201946	2201268	0	0
T63	1410130	1408380	0	0
T64	545892	545208	0	0
T65	616736	616080	0	0
T66	530684	529940	0	0
T67	724928	724228	0	0
T68	623872	623188	0	0
T69	460428	459744	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1447870	1446160	0	0
T2	1129000	1127250	0	0
T3	1612080	1610400	0	0
T29	640080	639072	0	0
T30	1083000	1081686	0	0
T31	666768	665766	0	0
T56	1577712	1577640	0	0
T57	1627428	1627332	0	0
T59	2201946	2201268	0	0
T63	1410130	1408380	0	0
T64	545892	545208	0	0
T65	616736	616080	0	0
T66	530684	529940	0	0
T67	724928	724228	0	0
T68	623872	623188	0	0
T69	460428	459744	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	21086	21086	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T32	6	6	0	0
T33	6	6	0	0
T34	6	6	0	0
T58	6	6	0	0
T63	4	4	0	0
T64	4	4	0	0
T65	4	4	0	0
T66	4	4	0	0
T67	4	4	0	0
T68	4	4	0	0
T69	4	4	0	0
T100	6	6	0	0
T101	6	6	0	0
T123	6	6	0	0
T230	6	6	0	0
T231	6	6	0	0
T232	6	6	0	0