Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	401901841	46679506	0	0
DepthKnown_A	401901841	401799061	0	0
RvalidKnown_A	401901841	401799061	0	0
WreadyKnown_A	401901841	401799061	0	0
gen_passthru_fifo.paramCheckPass	962	962	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401901841	46679506	0	0
T19	366871	167028	0	0
T20	697375	454764	0	0
T21	198182	14410	0	0
T22	211682	150941	0	0
T38	249828	32637	0	0
T90	454672	57174	0	0
T104	250774	28854	0	0
T106	233862	32138	0	0
T136	213239	153038	0	0
T137	75221	8404	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401901841	401799061	0	0
T1	144787	144616	0	0
T2	112900	112725	0	0
T3	161208	161040	0	0
T63	141013	140838	0	0
T64	136473	136302	0	0
T65	154184	154020	0	0
T66	132671	132485	0	0
T67	181232	181057	0	0
T68	155968	155797	0	0
T69	115107	114936	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401901841	401799061	0	0
T1	144787	144616	0	0
T2	112900	112725	0	0
T3	161208	161040	0	0
T63	141013	140838	0	0
T64	136473	136302	0	0
T65	154184	154020	0	0
T66	132671	132485	0	0
T67	181232	181057	0	0
T68	155968	155797	0	0
T69	115107	114936	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401901841	401799061	0	0
T1	144787	144616	0	0
T2	112900	112725	0	0
T3	161208	161040	0	0
T63	141013	140838	0	0
T64	136473	136302	0	0
T65	154184	154020	0	0
T66	132671	132485	0	0
T67	181232	181057	0	0
T68	155968	155797	0	0
T69	115107	114936	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	962	962	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	401901841	35656753	0	0
DepthKnown_A	401901841	401799061	0	0
RvalidKnown_A	401901841	401799061	0	0
WreadyKnown_A	401901841	401799061	0	0
gen_passthru_fifo.paramCheckPass	962	962	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401901841	35656753	0	0
T19	366871	83763	0	0
T20	697375	449263	0	0
T21	198182	11312	0	0
T22	211682	147227	0	0
T38	249828	22853	0	0
T90	454672	52642	0	0
T104	250774	21623	0	0
T106	233862	27512	0	0
T136	213239	149315	0	0
T137	75221	6055	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401901841	401799061	0	0
T1	144787	144616	0	0
T2	112900	112725	0	0
T3	161208	161040	0	0
T63	141013	140838	0	0
T64	136473	136302	0	0
T65	154184	154020	0	0
T66	132671	132485	0	0
T67	181232	181057	0	0
T68	155968	155797	0	0
T69	115107	114936	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401901841	401799061	0	0
T1	144787	144616	0	0
T2	112900	112725	0	0
T3	161208	161040	0	0
T63	141013	140838	0	0
T64	136473	136302	0	0
T65	154184	154020	0	0
T66	132671	132485	0	0
T67	181232	181057	0	0
T68	155968	155797	0	0
T69	115107	114936	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401901841	401799061	0	0
T1	144787	144616	0	0
T2	112900	112725	0	0
T3	161208	161040	0	0
T63	141013	140838	0	0
T64	136473	136302	0	0
T65	154184	154020	0	0
T66	132671	132485	0	0
T67	181232	181057	0	0
T68	155968	155797	0	0
T69	115107	114936	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	962	962	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	401901841	34031739	0	0
DepthKnown_A	401901841	401799061	0	0
RvalidKnown_A	401901841	401799061	0	0
WreadyKnown_A	401901841	401799061	0	0
gen_passthru_fifo.paramCheckPass	962	962	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401901841	34031739	0	0
T1	144787	2714	0	0
T2	112900	3507	0	0
T3	161208	3204	0	0
T63	141013	2624	0	0
T64	136473	4150	0	0
T65	154184	3052	0	0
T66	132671	3401	0	0
T67	181232	3650	0	0
T68	155968	3240	0	0
T69	115107	1666	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401901841	401799061	0	0
T1	144787	144616	0	0
T2	112900	112725	0	0
T3	161208	161040	0	0
T63	141013	140838	0	0
T64	136473	136302	0	0
T65	154184	154020	0	0
T66	132671	132485	0	0
T67	181232	181057	0	0
T68	155968	155797	0	0
T69	115107	114936	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401901841	401799061	0	0
T1	144787	144616	0	0
T2	112900	112725	0	0
T3	161208	161040	0	0
T63	141013	140838	0	0
T64	136473	136302	0	0
T65	154184	154020	0	0
T66	132671	132485	0	0
T67	181232	181057	0	0
T68	155968	155797	0	0
T69	115107	114936	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401901841	401799061	0	0
T1	144787	144616	0	0
T2	112900	112725	0	0
T3	161208	161040	0	0
T63	141013	140838	0	0
T64	136473	136302	0	0
T65	154184	154020	0	0
T66	132671	132485	0	0
T67	181232	181057	0	0
T68	155968	155797	0	0
T69	115107	114936	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	962	962	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	401901841	28476919	0	0
DepthKnown_A	401901841	401799061	0	0
RvalidKnown_A	401901841	401799061	0	0
WreadyKnown_A	401901841	401799061	0	0
gen_passthru_fifo.paramCheckPass	962	962	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401901841	28476919	0	0
T1	144787	9855	0	0
T2	112900	1714	0	0
T3	161208	11937	0	0
T63	141013	9110	0	0
T64	136473	2502	0	0
T65	154184	10900	0	0
T66	132671	2348	0	0
T67	181232	14305	0	0
T68	155968	11945	0	0
T69	115107	6041	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401901841	401799061	0	0
T1	144787	144616	0	0
T2	112900	112725	0	0
T3	161208	161040	0	0
T63	141013	140838	0	0
T64	136473	136302	0	0
T65	154184	154020	0	0
T66	132671	132485	0	0
T67	181232	181057	0	0
T68	155968	155797	0	0
T69	115107	114936	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401901841	401799061	0	0
T1	144787	144616	0	0
T2	112900	112725	0	0
T3	161208	161040	0	0
T63	141013	140838	0	0
T64	136473	136302	0	0
T65	154184	154020	0	0
T66	132671	132485	0	0
T67	181232	181057	0	0
T68	155968	155797	0	0
T69	115107	114936	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	401901841	401799061	0	0
T1	144787	144616	0	0
T2	112900	112725	0	0
T3	161208	161040	0	0
T63	141013	140838	0	0
T64	136473	136302	0	0
T65	154184	154020	0	0
T66	132671	132485	0	0
T67	181232	181057	0	0
T68	155968	155797	0	0
T69	115107	114936	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	962	962	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	473364705	105920	0	0
DepthKnown_A	473364705	473246150	0	0
RvalidKnown_A	473364705	473246150	0	0
WreadyKnown_A	473364705	473246150	0	0
gen_passthru_fifo.paramCheckPass	2873	2873	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473364705	105920	0	0
T19	366871	73	0	0
T20	697375	60	0	0
T21	198182	17	0	0
T22	211682	53	0	0
T29	106680	25	0	0
T30	180500	50	0	0
T31	111128	25	0	0
T56	262952	685	0	0
T57	271238	741	0	0
T59	366991	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473364705	473246150	0	0
T1	144787	144616	0	0
T2	112900	112725	0	0
T3	161208	161040	0	0
T29	106680	106512	0	0
T30	180500	180281	0	0
T31	111128	110961	0	0
T56	262952	262940	0	0
T57	271238	271222	0	0
T59	366991	366878	0	0
T63	141013	140838	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473364705	473246150	0	0
T1	144787	144616	0	0
T2	112900	112725	0	0
T3	161208	161040	0	0
T29	106680	106512	0	0
T30	180500	180281	0	0
T31	111128	110961	0	0
T56	262952	262940	0	0
T57	271238	271222	0	0
T59	366991	366878	0	0
T63	141013	140838	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473364705	473246150	0	0
T1	144787	144616	0	0
T2	112900	112725	0	0
T3	161208	161040	0	0
T29	106680	106512	0	0
T30	180500	180281	0	0
T31	111128	110961	0	0
T56	262952	262940	0	0
T57	271238	271222	0	0
T59	366991	366878	0	0
T63	141013	140838	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2873	2873	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T58	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0
T123	1	1	0	0
T230	1	1	0	0
T231	1	1	0	0
T232	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	473364705	107839	0	0
DepthKnown_A	473364705	473246150	0	0
RvalidKnown_A	473364705	473246150	0	0
WreadyKnown_A	473364705	473246150	0	0
gen_passthru_fifo.paramCheckPass	2873	2873	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473364705	107839	0	0
T19	366871	73	0	0
T20	697375	60	0	0
T21	198182	17	0	0
T22	211682	53	0	0
T29	106680	25	0	0
T30	180500	50	0	0
T31	111128	25	0	0
T56	262952	1011	0	0
T57	271238	1278	0	0
T59	366991	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473364705	473246150	0	0
T1	144787	144616	0	0
T2	112900	112725	0	0
T3	161208	161040	0	0
T29	106680	106512	0	0
T30	180500	180281	0	0
T31	111128	110961	0	0
T56	262952	262940	0	0
T57	271238	271222	0	0
T59	366991	366878	0	0
T63	141013	140838	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473364705	473246150	0	0
T1	144787	144616	0	0
T2	112900	112725	0	0
T3	161208	161040	0	0
T29	106680	106512	0	0
T30	180500	180281	0	0
T31	111128	110961	0	0
T56	262952	262940	0	0
T57	271238	271222	0	0
T59	366991	366878	0	0
T63	141013	140838	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473364705	473246150	0	0
T1	144787	144616	0	0
T2	112900	112725	0	0
T3	161208	161040	0	0
T29	106680	106512	0	0
T30	180500	180281	0	0
T31	111128	110961	0	0
T56	262952	262940	0	0
T57	271238	271222	0	0
T59	366991	366878	0	0
T63	141013	140838	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2873	2873	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T58	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0
T123	1	1	0	0
T230	1	1	0	0
T231	1	1	0	0
T232	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	473364705	49672	0	0
DepthKnown_A	473364705	473246150	0	0
RvalidKnown_A	473364705	473246150	0	0
WreadyKnown_A	473364705	473246150	0	0
gen_passthru_fifo.paramCheckPass	2873	2873	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473364705	49672	0	0
T19	366871	69	0	0
T20	697375	58	0	0
T21	198182	14	0	0
T22	211682	52	0	0
T38	249828	97	0	0
T90	454672	28	0	0
T104	250774	39	0	0
T106	233862	29	0	0
T136	213239	52	0	0
T137	75221	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473364705	473246150	0	0
T1	144787	144616	0	0
T2	112900	112725	0	0
T3	161208	161040	0	0
T29	106680	106512	0	0
T30	180500	180281	0	0
T31	111128	110961	0	0
T56	262952	262940	0	0
T57	271238	271222	0	0
T59	366991	366878	0	0
T63	141013	140838	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473364705	473246150	0	0
T1	144787	144616	0	0
T2	112900	112725	0	0
T3	161208	161040	0	0
T29	106680	106512	0	0
T30	180500	180281	0	0
T31	111128	110961	0	0
T56	262952	262940	0	0
T57	271238	271222	0	0
T59	366991	366878	0	0
T63	141013	140838	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473364705	473246150	0	0
T1	144787	144616	0	0
T2	112900	112725	0	0
T3	161208	161040	0	0
T29	106680	106512	0	0
T30	180500	180281	0	0
T31	111128	110961	0	0
T56	262952	262940	0	0
T57	271238	271222	0	0
T59	366991	366878	0	0
T63	141013	140838	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2873	2873	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T58	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0
T123	1	1	0	0
T230	1	1	0	0
T231	1	1	0	0
T232	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	473364705	49671	0	0
DepthKnown_A	473364705	473246150	0	0
RvalidKnown_A	473364705	473246150	0	0
WreadyKnown_A	473364705	473246150	0	0
gen_passthru_fifo.paramCheckPass	2873	2873	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473364705	49671	0	0
T19	366871	69	0	0
T20	697375	58	0	0
T21	198182	14	0	0
T22	211682	52	0	0
T38	249828	97	0	0
T90	454672	28	0	0
T104	250774	39	0	0
T106	233862	29	0	0
T136	213239	52	0	0
T137	75221	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473364705	473246150	0	0
T1	144787	144616	0	0
T2	112900	112725	0	0
T3	161208	161040	0	0
T29	106680	106512	0	0
T30	180500	180281	0	0
T31	111128	110961	0	0
T56	262952	262940	0	0
T57	271238	271222	0	0
T59	366991	366878	0	0
T63	141013	140838	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473364705	473246150	0	0
T1	144787	144616	0	0
T2	112900	112725	0	0
T3	161208	161040	0	0
T29	106680	106512	0	0
T30	180500	180281	0	0
T31	111128	110961	0	0
T56	262952	262940	0	0
T57	271238	271222	0	0
T59	366991	366878	0	0
T63	141013	140838	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473364705	473246150	0	0
T1	144787	144616	0	0
T2	112900	112725	0	0
T3	161208	161040	0	0
T29	106680	106512	0	0
T30	180500	180281	0	0
T31	111128	110961	0	0
T56	262952	262940	0	0
T57	271238	271222	0	0
T59	366991	366878	0	0
T63	141013	140838	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2873	2873	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T58	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0
T123	1	1	0	0
T230	1	1	0	0
T231	1	1	0	0
T232	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	473364705	56248	0	0
DepthKnown_A	473364705	473246150	0	0
RvalidKnown_A	473364705	473246150	0	0
WreadyKnown_A	473364705	473246150	0	0
gen_passthru_fifo.paramCheckPass	2873	2873	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473364705	56248	0	0
T19	366871	4	0	0
T20	697375	2	0	0
T21	198182	3	0	0
T22	211682	1	0	0
T29	106680	25	0	0
T30	180500	50	0	0
T31	111128	25	0	0
T56	262952	685	0	0
T57	271238	741	0	0
T59	366991	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473364705	473246150	0	0
T1	144787	144616	0	0
T2	112900	112725	0	0
T3	161208	161040	0	0
T29	106680	106512	0	0
T30	180500	180281	0	0
T31	111128	110961	0	0
T56	262952	262940	0	0
T57	271238	271222	0	0
T59	366991	366878	0	0
T63	141013	140838	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473364705	473246150	0	0
T1	144787	144616	0	0
T2	112900	112725	0	0
T3	161208	161040	0	0
T29	106680	106512	0	0
T30	180500	180281	0	0
T31	111128	110961	0	0
T56	262952	262940	0	0
T57	271238	271222	0	0
T59	366991	366878	0	0
T63	141013	140838	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473364705	473246150	0	0
T1	144787	144616	0	0
T2	112900	112725	0	0
T3	161208	161040	0	0
T29	106680	106512	0	0
T30	180500	180281	0	0
T31	111128	110961	0	0
T56	262952	262940	0	0
T57	271238	271222	0	0
T59	366991	366878	0	0
T63	141013	140838	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2873	2873	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T58	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0
T123	1	1	0	0
T230	1	1	0	0
T231	1	1	0	0
T232	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	473364705	58168	0	0
DepthKnown_A	473364705	473246150	0	0
RvalidKnown_A	473364705	473246150	0	0
WreadyKnown_A	473364705	473246150	0	0
gen_passthru_fifo.paramCheckPass	2873	2873	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473364705	58168	0	0
T19	366871	4	0	0
T20	697375	2	0	0
T21	198182	3	0	0
T22	211682	1	0	0
T29	106680	25	0	0
T30	180500	50	0	0
T31	111128	25	0	0
T56	262952	1011	0	0
T57	271238	1278	0	0
T59	366991	100	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473364705	473246150	0	0
T1	144787	144616	0	0
T2	112900	112725	0	0
T3	161208	161040	0	0
T29	106680	106512	0	0
T30	180500	180281	0	0
T31	111128	110961	0	0
T56	262952	262940	0	0
T57	271238	271222	0	0
T59	366991	366878	0	0
T63	141013	140838	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473364705	473246150	0	0
T1	144787	144616	0	0
T2	112900	112725	0	0
T3	161208	161040	0	0
T29	106680	106512	0	0
T30	180500	180281	0	0
T31	111128	110961	0	0
T56	262952	262940	0	0
T57	271238	271222	0	0
T59	366991	366878	0	0
T63	141013	140838	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473364705	473246150	0	0
T1	144787	144616	0	0
T2	112900	112725	0	0
T3	161208	161040	0	0
T29	106680	106512	0	0
T30	180500	180281	0	0
T31	111128	110961	0	0
T56	262952	262940	0	0
T57	271238	271222	0	0
T59	366991	366878	0	0
T63	141013	140838	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2873	2873	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T58	1	1	0	0
T100	1	1	0	0
T101	1	1	0	0
T123	1	1	0	0
T230	1	1	0	0
T231	1	1	0	0
T232	1	1	0	0