Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_pwm_aon.u_reg.u_cfg_cdc

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T59,T337,T56

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T59,T56,T57
1	-	Covered	T8,T16,T17

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119298667	95265	0	0
DstReqKnown_A	1546130	1337541	0	0
SrcAckBusyChk_A	119298667	235	0	0
SrcBusyKnown_A	119298667	118518051	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	95265	0	0
T8	41329	764	0	0
T13	0	463	0	0
T16	43477	811	0	0
T17	0	791	0	0
T56	678620	2460	0	0
T57	684685	5085	0	0
T59	88935	794	0	0
T85	54565	0	0	0
T86	43809	0	0	0
T110	88057	0	0	0
T201	28522	0	0	0
T294	0	2580	0	0
T295	0	745	0	0
T296	0	1694	0	0
T331	42134	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1546130	1337541	0	0
T1	361	135	0	0
T2	367	140	0	0
T3	433	208	0	0
T29	783	496	0	0
T30	1407	943	0	0
T31	1040	556	0	0
T56	5882	5656	0	0
T57	6032	5747	0	0
T59	1131	906	0	0
T63	360	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	235	0	0
T8	41329	2	0	0
T13	0	1	0	0
T16	43477	2	0	0
T17	0	2	0	0
T56	678620	6	0	0
T57	684685	13	0	0
T59	88935	2	0	0
T85	54565	0	0	0
T86	43809	0	0	0
T110	88057	0	0	0
T201	28522	0	0	0
T294	0	6	0	0
T295	0	2	0	0
T296	0	5	0	0
T331	42134	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	118518051	0	0
T1	10008	9220	0	0
T2	10066	9233	0	0
T3	9804	9168	0	0
T29	27898	26616	0	0
T30	46569	45067	0	0
T31	29019	27738	0	0
T56	678620	677417	0	0
T57	684685	682666	0	0
T59	88935	88417	0	0
T63	10051	9228	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	0	1
145	0	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T59,T56,T338

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T59,T56,T57
1	-	Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119298667	66728	0	0
DstReqKnown_A	1546130	1337541	0	0
SrcAckBusyChk_A	119298667	167	0	0
SrcBusyKnown_A	119298667	118518051	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	66728	0	0
T13	469436	466	0	0
T56	678620	5805	0	0
T57	684685	4721	0	0
T59	88935	799	0	0
T174	51735	0	0	0
T293	0	983	0	0
T294	0	471	0	0
T295	0	820	0	0
T296	0	1398	0	0
T297	0	392	0	0
T330	0	1118	0	0
T332	23429	0	0	0
T333	49193	0	0	0
T334	58663	0	0	0
T335	125937	0	0	0
T336	40146	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1546130	1337541	0	0
T1	361	135	0	0
T2	367	140	0	0
T3	433	208	0	0
T29	783	496	0	0
T30	1407	943	0	0
T31	1040	556	0	0
T56	5882	5656	0	0
T57	6032	5747	0	0
T59	1131	906	0	0
T63	360	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	167	0	0
T13	469436	1	0	0
T56	678620	14	0	0
T57	684685	12	0	0
T59	88935	2	0	0
T174	51735	0	0	0
T293	0	3	0	0
T294	0	1	0	0
T295	0	2	0	0
T296	0	4	0	0
T297	0	1	0	0
T330	0	3	0	0
T332	23429	0	0	0
T333	49193	0	0	0
T334	58663	0	0	0
T335	125937	0	0	0
T336	40146	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	118518051	0	0
T1	10008	9220	0	0
T2	10066	9233	0	0
T3	9804	9168	0	0
T29	27898	26616	0	0
T30	46569	45067	0	0
T31	29019	27738	0	0
T56	678620	677417	0	0
T57	684685	682666	0	0
T59	88935	88417	0	0
T63	10051	9228	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T328,T59,T56

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T59,T56,T57
1	-	Covered	T18

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119298667	70377	0	0
DstReqKnown_A	1546130	1337541	0	0
SrcAckBusyChk_A	119298667	176	0	0
SrcBusyKnown_A	119298667	118518051	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	70377	0	0
T13	0	446	0	0
T18	42894	1019	0	0
T28	152543	0	0	0
T56	678620	4093	0	0
T57	684685	4229	0	0
T59	88935	862	0	0
T294	0	5388	0	0
T295	0	709	0	0
T296	0	289	0	0
T297	0	448	0	0
T330	0	4423	0	0
T339	160629	0	0	0
T340	67496	0	0	0
T341	24872	0	0	0
T342	43685	0	0	0
T343	39070	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1546130	1337541	0	0
T1	361	135	0	0
T2	367	140	0	0
T3	433	208	0	0
T29	783	496	0	0
T30	1407	943	0	0
T31	1040	556	0	0
T56	5882	5656	0	0
T57	6032	5747	0	0
T59	1131	906	0	0
T63	360	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	176	0	0
T13	0	1	0	0
T18	42894	2	0	0
T28	152543	0	0	0
T56	678620	10	0	0
T57	684685	11	0	0
T59	88935	2	0	0
T294	0	13	0	0
T295	0	2	0	0
T296	0	1	0	0
T297	0	1	0	0
T330	0	11	0	0
T339	160629	0	0	0
T340	67496	0	0	0
T341	24872	0	0	0
T342	43685	0	0	0
T343	39070	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	118518051	0	0
T1	10008	9220	0	0
T2	10066	9233	0	0
T3	9804	9168	0	0
T29	27898	26616	0	0
T30	46569	45067	0	0
T31	29019	27738	0	0
T56	678620	677417	0	0
T57	684685	682666	0	0
T59	88935	88417	0	0
T63	10051	9228	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	0	1
145	0	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T123,T59,T56

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T59,T56,T57
1	-	Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119298667	66376	0	0
DstReqKnown_A	1546130	1337541	0	0
SrcAckBusyChk_A	119298667	167	0	0
SrcBusyKnown_A	119298667	118518051	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	66376	0	0
T13	469436	370	0	0
T56	678620	5738	0	0
T57	684685	3429	0	0
T59	88935	860	0	0
T174	51735	0	0	0
T293	0	5545	0	0
T295	0	730	0	0
T296	0	1378	0	0
T297	0	456	0	0
T330	0	1120	0	0
T332	23429	0	0	0
T333	49193	0	0	0
T334	58663	0	0	0
T335	125937	0	0	0
T336	40146	0	0	0
T344	0	693	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1546130	1337541	0	0
T1	361	135	0	0
T2	367	140	0	0
T3	433	208	0	0
T29	783	496	0	0
T30	1407	943	0	0
T31	1040	556	0	0
T56	5882	5656	0	0
T57	6032	5747	0	0
T59	1131	906	0	0
T63	360	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	167	0	0
T13	469436	1	0	0
T56	678620	14	0	0
T57	684685	9	0	0
T59	88935	2	0	0
T174	51735	0	0	0
T293	0	14	0	0
T295	0	2	0	0
T296	0	4	0	0
T297	0	1	0	0
T330	0	3	0	0
T332	23429	0	0	0
T333	49193	0	0	0
T334	58663	0	0	0
T335	125937	0	0	0
T336	40146	0	0	0
T344	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	118518051	0	0
T1	10008	9220	0	0
T2	10066	9233	0	0
T3	9804	9168	0	0
T29	27898	26616	0	0
T30	46569	45067	0	0
T31	29019	27738	0	0
T56	678620	677417	0	0
T57	684685	682666	0	0
T59	88935	88417	0	0
T63	10051	9228	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T59,T56,T57

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T59,T56,T57
1	-	Covered	T9

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119298667	77860	0	0
DstReqKnown_A	1546130	1337541	0	0
SrcAckBusyChk_A	119298667	193	0	0
SrcBusyKnown_A	119298667	118518051	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	77860	0	0
T9	27403	1001	0	0
T13	0	395	0	0
T56	678620	4549	0	0
T57	684685	4676	0	0
T59	88935	798	0	0
T72	36875	0	0	0
T73	154332	0	0	0
T74	83738	0	0	0
T75	39487	0	0	0
T76	62920	0	0	0
T77	9790	0	0	0
T294	0	2938	0	0
T295	0	774	0	0
T296	0	4702	0	0
T297	0	458	0	0
T330	0	298	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1546130	1337541	0	0
T1	361	135	0	0
T2	367	140	0	0
T3	433	208	0	0
T29	783	496	0	0
T30	1407	943	0	0
T31	1040	556	0	0
T56	5882	5656	0	0
T57	6032	5747	0	0
T59	1131	906	0	0
T63	360	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	193	0	0
T9	27403	2	0	0
T13	0	1	0	0
T56	678620	11	0	0
T57	684685	12	0	0
T59	88935	2	0	0
T72	36875	0	0	0
T73	154332	0	0	0
T74	83738	0	0	0
T75	39487	0	0	0
T76	62920	0	0	0
T77	9790	0	0	0
T294	0	7	0	0
T295	0	2	0	0
T296	0	12	0	0
T297	0	1	0	0
T330	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	118518051	0	0
T1	10008	9220	0	0
T2	10066	9233	0	0
T3	9804	9168	0	0
T29	27898	26616	0	0
T30	46569	45067	0	0
T31	29019	27738	0	0
T56	678620	677417	0	0
T57	684685	682666	0	0
T59	88935	88417	0	0
T63	10051	9228	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T101,T59,T56

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T59,T56,T57
1	-	Covered	T10,T14,T15

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119298667	70789	0	0
DstReqKnown_A	1546130	1337541	0	0
SrcAckBusyChk_A	119298667	182	0	0
SrcBusyKnown_A	119298667	118518051	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	70789	0	0
T10	155807	1533	0	0
T14	0	1422	0	0
T15	0	1443	0	0
T56	678620	6835	0	0
T57	684685	1387	0	0
T59	88935	907	0	0
T79	0	774	0	0
T80	0	624	0	0
T88	62077	0	0	0
T94	400763	0	0	0
T105	50258	0	0	0
T199	44151	0	0	0
T211	66089	0	0	0
T214	23015	0	0	0
T329	0	612	0	0
T345	0	611	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1546130	1337541	0	0
T1	361	135	0	0
T2	367	140	0	0
T3	433	208	0	0
T29	783	496	0	0
T30	1407	943	0	0
T31	1040	556	0	0
T56	5882	5656	0	0
T57	6032	5747	0	0
T59	1131	906	0	0
T63	360	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	182	0	0
T10	155807	4	0	0
T14	0	4	0	0
T15	0	4	0	0
T56	678620	17	0	0
T57	684685	4	0	0
T59	88935	2	0	0
T79	0	2	0	0
T80	0	2	0	0
T88	62077	0	0	0
T94	400763	0	0	0
T105	50258	0	0	0
T199	44151	0	0	0
T211	66089	0	0	0
T214	23015	0	0	0
T329	0	2	0	0
T345	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	118518051	0	0
T1	10008	9220	0	0
T2	10066	9233	0	0
T3	9804	9168	0	0
T29	27898	26616	0	0
T30	46569	45067	0	0
T31	29019	27738	0	0
T56	678620	677417	0	0
T57	684685	682666	0	0
T59	88935	88417	0	0
T63	10051	9228	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	0	1
145	0	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T59,T56,T57

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T59,T56,T57
1	-	Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119298667	72891	0	0
DstReqKnown_A	1546130	1337541	0	0
SrcAckBusyChk_A	119298667	183	0	0
SrcBusyKnown_A	119298667	118518051	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	72891	0	0
T13	469436	455	0	0
T56	678620	4474	0	0
T57	684685	5419	0	0
T59	88935	812	0	0
T174	51735	0	0	0
T293	0	2782	0	0
T294	0	1847	0	0
T295	0	748	0	0
T296	0	1740	0	0
T297	0	429	0	0
T330	0	2736	0	0
T332	23429	0	0	0
T333	49193	0	0	0
T334	58663	0	0	0
T335	125937	0	0	0
T336	40146	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1546130	1337541	0	0
T1	361	135	0	0
T2	367	140	0	0
T3	433	208	0	0
T29	783	496	0	0
T30	1407	943	0	0
T31	1040	556	0	0
T56	5882	5656	0	0
T57	6032	5747	0	0
T59	1131	906	0	0
T63	360	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	183	0	0
T13	469436	1	0	0
T56	678620	11	0	0
T57	684685	14	0	0
T59	88935	2	0	0
T174	51735	0	0	0
T293	0	7	0	0
T294	0	4	0	0
T295	0	2	0	0
T296	0	5	0	0
T297	0	1	0	0
T330	0	7	0	0
T332	23429	0	0	0
T333	49193	0	0	0
T334	58663	0	0	0
T335	125937	0	0	0
T336	40146	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	118518051	0	0
T1	10008	9220	0	0
T2	10066	9233	0	0
T3	9804	9168	0	0
T29	27898	26616	0	0
T30	46569	45067	0	0
T31	29019	27738	0	0
T56	678620	677417	0	0
T57	684685	682666	0	0
T59	88935	88417	0	0
T63	10051	9228	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T59,T346,T56

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T59,T56,T57
1	-	Covered	T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119298667	78851	0	0
DstReqKnown_A	1546130	1337541	0	0
SrcAckBusyChk_A	119298667	195	0	0
SrcBusyKnown_A	119298667	118518051	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	78851	0	0
T7	23807	900	0	0
T13	0	394	0	0
T39	67441	0	0	0
T40	65481	0	0	0
T56	678620	3272	0	0
T57	684685	1403	0	0
T59	88935	909	0	0
T81	19425	0	0	0
T82	160541	0	0	0
T83	68539	0	0	0
T84	42006	0	0	0
T294	0	2566	0	0
T295	0	693	0	0
T296	0	4251	0	0
T297	0	465	0	0
T330	0	3656	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1546130	1337541	0	0
T1	361	135	0	0
T2	367	140	0	0
T3	433	208	0	0
T29	783	496	0	0
T30	1407	943	0	0
T31	1040	556	0	0
T56	5882	5656	0	0
T57	6032	5747	0	0
T59	1131	906	0	0
T63	360	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	195	0	0
T7	23807	2	0	0
T13	0	1	0	0
T39	67441	0	0	0
T40	65481	0	0	0
T56	678620	8	0	0
T57	684685	4	0	0
T59	88935	2	0	0
T81	19425	0	0	0
T82	160541	0	0	0
T83	68539	0	0	0
T84	42006	0	0	0
T294	0	6	0	0
T295	0	2	0	0
T296	0	11	0	0
T297	0	1	0	0
T330	0	9	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	118518051	0	0
T1	10008	9220	0	0
T2	10066	9233	0	0
T3	9804	9168	0	0
T29	27898	26616	0	0
T30	46569	45067	0	0
T31	29019	27738	0	0
T56	678620	677417	0	0
T57	684685	682666	0	0
T59	88935	88417	0	0
T63	10051	9228	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T347,T59,T348

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119298667	74344	0	0
DstReqKnown_A	1546130	1337541	0	0
SrcAckBusyChk_A	119298667	186	0	0
SrcBusyKnown_A	119298667	118518051	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	74344	0	0
T8	41329	269	0	0
T13	0	407	0	0
T16	43477	438	0	0
T17	0	418	0	0
T56	678620	6243	0	0
T57	684685	2173	0	0
T59	88935	755	0	0
T85	54565	0	0	0
T86	43809	0	0	0
T110	88057	0	0	0
T201	28522	0	0	0
T294	0	4088	0	0
T295	0	657	0	0
T296	0	1065	0	0
T331	42134	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1546130	1337541	0	0
T1	361	135	0	0
T2	367	140	0	0
T3	433	208	0	0
T29	783	496	0	0
T30	1407	943	0	0
T31	1040	556	0	0
T56	5882	5656	0	0
T57	6032	5747	0	0
T59	1131	906	0	0
T63	360	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	186	0	0
T8	41329	1	0	0
T13	0	1	0	0
T16	43477	1	0	0
T17	0	1	0	0
T56	678620	15	0	0
T57	684685	6	0	0
T59	88935	2	0	0
T85	54565	0	0	0
T86	43809	0	0	0
T110	88057	0	0	0
T201	28522	0	0	0
T294	0	10	0	0
T295	0	2	0	0
T296	0	3	0	0
T331	42134	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	118518051	0	0
T1	10008	9220	0	0
T2	10066	9233	0	0
T3	9804	9168	0	0
T29	27898	26616	0	0
T30	46569	45067	0	0
T31	29019	27738	0	0
T56	678620	677417	0	0
T57	684685	682666	0	0
T59	88935	88417	0	0
T63	10051	9228	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T59,T56,T57

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119298667	73252	0	0
DstReqKnown_A	1546130	1337541	0	0
SrcAckBusyChk_A	119298667	182	0	0
SrcBusyKnown_A	119298667	118518051	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	73252	0	0
T13	469436	439	0	0
T56	678620	3923	0	0
T57	684685	4625	0	0
T59	88935	924	0	0
T174	51735	0	0	0
T293	0	3656	0	0
T294	0	3699	0	0
T295	0	644	0	0
T296	0	2073	0	0
T297	0	420	0	0
T330	0	3285	0	0
T332	23429	0	0	0
T333	49193	0	0	0
T334	58663	0	0	0
T335	125937	0	0	0
T336	40146	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1546130	1337541	0	0
T1	361	135	0	0
T2	367	140	0	0
T3	433	208	0	0
T29	783	496	0	0
T30	1407	943	0	0
T31	1040	556	0	0
T56	5882	5656	0	0
T57	6032	5747	0	0
T59	1131	906	0	0
T63	360	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	182	0	0
T13	469436	1	0	0
T56	678620	9	0	0
T57	684685	12	0	0
T59	88935	2	0	0
T174	51735	0	0	0
T293	0	9	0	0
T294	0	9	0	0
T295	0	2	0	0
T296	0	6	0	0
T297	0	1	0	0
T330	0	8	0	0
T332	23429	0	0	0
T333	49193	0	0	0
T334	58663	0	0	0
T335	125937	0	0	0
T336	40146	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	118518051	0	0
T1	10008	9220	0	0
T2	10066	9233	0	0
T3	9804	9168	0	0
T29	27898	26616	0	0
T30	46569	45067	0	0
T31	29019	27738	0	0
T56	678620	677417	0	0
T57	684685	682666	0	0
T59	88935	88417	0	0
T63	10051	9228	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T59,T56,T57

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119298667	74285	0	0
DstReqKnown_A	1546130	1337541	0	0
SrcAckBusyChk_A	119298667	184	0	0
SrcBusyKnown_A	119298667	118518051	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	74285	0	0
T13	0	451	0	0
T18	42894	363	0	0
T28	152543	0	0	0
T56	678620	5782	0	0
T57	684685	969	0	0
T59	88935	921	0	0
T294	0	2227	0	0
T295	0	787	0	0
T296	0	264	0	0
T297	0	442	0	0
T330	0	3668	0	0
T339	160629	0	0	0
T340	67496	0	0	0
T341	24872	0	0	0
T342	43685	0	0	0
T343	39070	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1546130	1337541	0	0
T1	361	135	0	0
T2	367	140	0	0
T3	433	208	0	0
T29	783	496	0	0
T30	1407	943	0	0
T31	1040	556	0	0
T56	5882	5656	0	0
T57	6032	5747	0	0
T59	1131	906	0	0
T63	360	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	184	0	0
T13	0	1	0	0
T18	42894	1	0	0
T28	152543	0	0	0
T56	678620	14	0	0
T57	684685	3	0	0
T59	88935	2	0	0
T294	0	5	0	0
T295	0	2	0	0
T296	0	1	0	0
T297	0	1	0	0
T330	0	9	0	0
T339	160629	0	0	0
T340	67496	0	0	0
T341	24872	0	0	0
T342	43685	0	0	0
T343	39070	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	118518051	0	0
T1	10008	9220	0	0
T2	10066	9233	0	0
T3	9804	9168	0	0
T29	27898	26616	0	0
T30	46569	45067	0	0
T31	29019	27738	0	0
T56	678620	677417	0	0
T57	684685	682666	0	0
T59	88935	88417	0	0
T63	10051	9228	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T59,T56,T57

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119298667	78757	0	0
DstReqKnown_A	1546130	1337541	0	0
SrcAckBusyChk_A	119298667	198	0	0
SrcBusyKnown_A	119298667	118518051	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	78757	0	0
T13	469436	376	0	0
T56	678620	3289	0	0
T57	684685	6990	0	0
T59	88935	857	0	0
T174	51735	0	0	0
T293	0	3895	0	0
T294	0	2190	0	0
T295	0	786	0	0
T296	0	5044	0	0
T297	0	367	0	0
T330	0	3997	0	0
T332	23429	0	0	0
T333	49193	0	0	0
T334	58663	0	0	0
T335	125937	0	0	0
T336	40146	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1546130	1337541	0	0
T1	361	135	0	0
T2	367	140	0	0
T3	433	208	0	0
T29	783	496	0	0
T30	1407	943	0	0
T31	1040	556	0	0
T56	5882	5656	0	0
T57	6032	5747	0	0
T59	1131	906	0	0
T63	360	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	198	0	0
T13	469436	1	0	0
T56	678620	8	0	0
T57	684685	18	0	0
T59	88935	2	0	0
T174	51735	0	0	0
T293	0	10	0	0
T294	0	5	0	0
T295	0	2	0	0
T296	0	13	0	0
T297	0	1	0	0
T330	0	10	0	0
T332	23429	0	0	0
T333	49193	0	0	0
T334	58663	0	0	0
T335	125937	0	0	0
T336	40146	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	118518051	0	0
T1	10008	9220	0	0
T2	10066	9233	0	0
T3	9804	9168	0	0
T29	27898	26616	0	0
T30	46569	45067	0	0
T31	29019	27738	0	0
T56	678620	677417	0	0
T57	684685	682666	0	0
T59	88935	88417	0	0
T63	10051	9228	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T59,T349,T56

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119298667	77222	0	0
DstReqKnown_A	1546130	1337541	0	0
SrcAckBusyChk_A	119298667	191	0	0
SrcBusyKnown_A	119298667	118518051	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	77222	0	0
T9	27403	461	0	0
T13	0	418	0	0
T56	678620	3313	0	0
T57	684685	6796	0	0
T59	88935	756	0	0
T72	36875	0	0	0
T73	154332	0	0	0
T74	83738	0	0	0
T75	39487	0	0	0
T76	62920	0	0	0
T77	9790	0	0	0
T294	0	2885	0	0
T295	0	609	0	0
T296	0	2970	0	0
T297	0	382	0	0
T330	0	316	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1546130	1337541	0	0
T1	361	135	0	0
T2	367	140	0	0
T3	433	208	0	0
T29	783	496	0	0
T30	1407	943	0	0
T31	1040	556	0	0
T56	5882	5656	0	0
T57	6032	5747	0	0
T59	1131	906	0	0
T63	360	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	191	0	0
T9	27403	1	0	0
T13	0	1	0	0
T56	678620	8	0	0
T57	684685	17	0	0
T59	88935	2	0	0
T72	36875	0	0	0
T73	154332	0	0	0
T74	83738	0	0	0
T75	39487	0	0	0
T76	62920	0	0	0
T77	9790	0	0	0
T294	0	7	0	0
T295	0	2	0	0
T296	0	8	0	0
T297	0	1	0	0
T330	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	118518051	0	0
T1	10008	9220	0	0
T2	10066	9233	0	0
T3	9804	9168	0	0
T29	27898	26616	0	0
T30	46569	45067	0	0
T31	29019	27738	0	0
T56	678620	677417	0	0
T57	684685	682666	0	0
T59	88935	88417	0	0
T63	10051	9228	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T59,T348,T56

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119298667	73546	0	0
DstReqKnown_A	1546130	1337541	0	0
SrcAckBusyChk_A	119298667	185	0	0
SrcBusyKnown_A	119298667	118518051	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	73546	0	0
T10	155807	909	0	0
T14	0	677	0	0
T15	0	698	0	0
T56	678620	2047	0	0
T57	684685	5029	0	0
T59	88935	860	0	0
T79	0	401	0	0
T80	0	248	0	0
T88	62077	0	0	0
T94	400763	0	0	0
T105	50258	0	0	0
T199	44151	0	0	0
T211	66089	0	0	0
T214	23015	0	0	0
T329	0	357	0	0
T345	0	355	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1546130	1337541	0	0
T1	361	135	0	0
T2	367	140	0	0
T3	433	208	0	0
T29	783	496	0	0
T30	1407	943	0	0
T31	1040	556	0	0
T56	5882	5656	0	0
T57	6032	5747	0	0
T59	1131	906	0	0
T63	360	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	185	0	0
T10	155807	2	0	0
T14	0	2	0	0
T15	0	2	0	0
T56	678620	5	0	0
T57	684685	13	0	0
T59	88935	2	0	0
T79	0	1	0	0
T80	0	1	0	0
T88	62077	0	0	0
T94	400763	0	0	0
T105	50258	0	0	0
T199	44151	0	0	0
T211	66089	0	0	0
T214	23015	0	0	0
T329	0	1	0	0
T345	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	118518051	0	0
T1	10008	9220	0	0
T2	10066	9233	0	0
T3	9804	9168	0	0
T29	27898	26616	0	0
T30	46569	45067	0	0
T31	29019	27738	0	0
T56	678620	677417	0	0
T57	684685	682666	0	0
T59	88935	88417	0	0
T63	10051	9228	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T59,T56,T338

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119298667	71164	0	0
DstReqKnown_A	1546130	1337541	0	0
SrcAckBusyChk_A	119298667	179	0	0
SrcBusyKnown_A	119298667	118518051	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	71164	0	0
T13	469436	384	0	0
T56	678620	2249	0	0
T57	684685	3971	0	0
T59	88935	772	0	0
T174	51735	0	0	0
T293	0	4562	0	0
T294	0	2161	0	0
T295	0	723	0	0
T296	0	619	0	0
T297	0	421	0	0
T330	0	3955	0	0
T332	23429	0	0	0
T333	49193	0	0	0
T334	58663	0	0	0
T335	125937	0	0	0
T336	40146	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1546130	1337541	0	0
T1	361	135	0	0
T2	367	140	0	0
T3	433	208	0	0
T29	783	496	0	0
T30	1407	943	0	0
T31	1040	556	0	0
T56	5882	5656	0	0
T57	6032	5747	0	0
T59	1131	906	0	0
T63	360	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	179	0	0
T13	469436	1	0	0
T56	678620	5	0	0
T57	684685	10	0	0
T59	88935	2	0	0
T174	51735	0	0	0
T293	0	12	0	0
T294	0	5	0	0
T295	0	2	0	0
T296	0	2	0	0
T297	0	1	0	0
T330	0	10	0	0
T332	23429	0	0	0
T333	49193	0	0	0
T334	58663	0	0	0
T335	125937	0	0	0
T336	40146	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	118518051	0	0
T1	10008	9220	0	0
T2	10066	9233	0	0
T3	9804	9168	0	0
T29	27898	26616	0	0
T30	46569	45067	0	0
T31	29019	27738	0	0
T56	678620	677417	0	0
T57	684685	682666	0	0
T59	88935	88417	0	0
T63	10051	9228	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T59,T349,T56

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119298667	58854	0	0
DstReqKnown_A	1546130	1337541	0	0
SrcAckBusyChk_A	119298667	147	0	0
SrcBusyKnown_A	119298667	118518051	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	58854	0	0
T7	23807	480	0	0
T13	0	459	0	0
T39	67441	0	0	0
T40	65481	0	0	0
T56	678620	1267	0	0
T57	684685	4731	0	0
T59	88935	896	0	0
T81	19425	0	0	0
T82	160541	0	0	0
T83	68539	0	0	0
T84	42006	0	0	0
T294	0	896	0	0
T295	0	841	0	0
T296	0	1019	0	0
T297	0	411	0	0
T330	0	2009	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1546130	1337541	0	0
T1	361	135	0	0
T2	367	140	0	0
T3	433	208	0	0
T29	783	496	0	0
T30	1407	943	0	0
T31	1040	556	0	0
T56	5882	5656	0	0
T57	6032	5747	0	0
T59	1131	906	0	0
T63	360	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	147	0	0
T7	23807	1	0	0
T13	0	1	0	0
T39	67441	0	0	0
T40	65481	0	0	0
T56	678620	3	0	0
T57	684685	12	0	0
T59	88935	2	0	0
T81	19425	0	0	0
T82	160541	0	0	0
T83	68539	0	0	0
T84	42006	0	0	0
T294	0	2	0	0
T295	0	2	0	0
T296	0	3	0	0
T297	0	1	0	0
T330	0	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	118518051	0	0
T1	10008	9220	0	0
T2	10066	9233	0	0
T3	9804	9168	0	0
T29	27898	26616	0	0
T30	46569	45067	0	0
T31	29019	27738	0	0
T56	678620	677417	0	0
T57	684685	682666	0	0
T59	88935	88417	0	0
T63	10051	9228	0	0