Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.68	96.99	84.51			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.26			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T59,T56,T57

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119298667	58091	0	0
DstReqKnown_A	1546130	1337541	0	0
SrcAckBusyChk_A	119298667	147	0	0
SrcBusyKnown_A	119298667	118518051	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	58091	0	0
T13	469436	470	0	0
T56	678620	2944	0	0
T57	684685	4309	0	0
T59	88935	860	0	0
T174	51735	0	0	0
T293	0	5816	0	0
T294	0	3209	0	0
T295	0	742	0	0
T296	0	250	0	0
T297	0	449	0	0
T330	0	768	0	0
T332	23429	0	0	0
T333	49193	0	0	0
T334	58663	0	0	0
T335	125937	0	0	0
T336	40146	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1546130	1337541	0	0
T1	361	135	0	0
T2	367	140	0	0
T3	433	208	0	0
T29	783	496	0	0
T30	1407	943	0	0
T31	1040	556	0	0
T56	5882	5656	0	0
T57	6032	5747	0	0
T59	1131	906	0	0
T63	360	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	147	0	0
T13	469436	1	0	0
T56	678620	7	0	0
T57	684685	11	0	0
T59	88935	2	0	0
T174	51735	0	0	0
T293	0	15	0	0
T294	0	8	0	0
T295	0	2	0	0
T296	0	1	0	0
T297	0	1	0	0
T330	0	2	0	0
T332	23429	0	0	0
T333	49193	0	0	0
T334	58663	0	0	0
T335	125937	0	0	0
T336	40146	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	118518051	0	0
T1	10008	9220	0	0
T2	10066	9233	0	0
T3	9804	9168	0	0
T29	27898	26616	0	0
T30	46569	45067	0	0
T31	29019	27738	0	0
T56	678620	677417	0	0
T57	684685	682666	0	0
T59	88935	88417	0	0
T63	10051	9228	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T101,T59,T56

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119298667	89924	0	0
DstReqKnown_A	1546130	1337541	0	0
SrcAckBusyChk_A	119298667	224	0	0
SrcBusyKnown_A	119298667	118518051	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	89924	0	0
T11	40079	340	0	0
T12	0	296	0	0
T13	0	438	0	0
T36	93086	0	0	0
T56	678620	7561	0	0
T57	684685	5092	0	0
T59	88935	764	0	0
T154	204610	0	0	0
T181	35314	0	0	0
T233	20085	0	0	0
T239	19605	0	0	0
T247	169874	0	0	0
T294	0	2546	0	0
T295	0	725	0	0
T296	0	3859	0	0
T350	0	332	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1546130	1337541	0	0
T1	361	135	0	0
T2	367	140	0	0
T3	433	208	0	0
T29	783	496	0	0
T30	1407	943	0	0
T31	1040	556	0	0
T56	5882	5656	0	0
T57	6032	5747	0	0
T59	1131	906	0	0
T63	360	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	224	0	0
T11	40079	1	0	0
T12	0	1	0	0
T13	0	1	0	0
T36	93086	0	0	0
T56	678620	19	0	0
T57	684685	13	0	0
T59	88935	2	0	0
T154	204610	0	0	0
T181	35314	0	0	0
T233	20085	0	0	0
T239	19605	0	0	0
T247	169874	0	0	0
T294	0	6	0	0
T295	0	2	0	0
T296	0	10	0	0
T297	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	118518051	0	0
T1	10008	9220	0	0
T2	10066	9233	0	0
T3	9804	9168	0	0
T29	27898	26616	0	0
T30	46569	45067	0	0
T31	29019	27738	0	0
T56	678620	677417	0	0
T57	684685	682666	0	0
T59	88935	88417	0	0
T63	10051	9228	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T59,T56,T57

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119298667	73856	0	0
DstReqKnown_A	1546130	1337541	0	0
SrcAckBusyChk_A	119298667	185	0	0
SrcBusyKnown_A	119298667	118518051	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	73856	0	0
T13	469436	437	0	0
T56	678620	6150	0	0
T57	684685	5709	0	0
T59	88935	807	0	0
T174	51735	0	0	0
T293	0	1963	0	0
T294	0	845	0	0
T295	0	768	0	0
T296	0	2997	0	0
T297	0	445	0	0
T330	0	3290	0	0
T332	23429	0	0	0
T333	49193	0	0	0
T334	58663	0	0	0
T335	125937	0	0	0
T336	40146	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1546130	1337541	0	0
T1	361	135	0	0
T2	367	140	0	0
T3	433	208	0	0
T29	783	496	0	0
T30	1407	943	0	0
T31	1040	556	0	0
T56	5882	5656	0	0
T57	6032	5747	0	0
T59	1131	906	0	0
T63	360	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	185	0	0
T13	469436	1	0	0
T56	678620	15	0	0
T57	684685	15	0	0
T59	88935	2	0	0
T174	51735	0	0	0
T293	0	5	0	0
T294	0	2	0	0
T295	0	2	0	0
T296	0	8	0	0
T297	0	1	0	0
T330	0	8	0	0
T332	23429	0	0	0
T333	49193	0	0	0
T334	58663	0	0	0
T335	125937	0	0	0
T336	40146	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	118518051	0	0
T1	10008	9220	0	0
T2	10066	9233	0	0
T3	9804	9168	0	0
T29	27898	26616	0	0
T30	46569	45067	0	0
T31	29019	27738	0	0
T56	678620	677417	0	0
T57	684685	682666	0	0
T59	88935	88417	0	0
T63	10051	9228	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T33,T59,T56

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119298667	67834	0	0
DstReqKnown_A	1546130	1337541	0	0
SrcAckBusyChk_A	119298667	170	0	0
SrcBusyKnown_A	119298667	118518051	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	67834	0	0
T13	469436	426	0	0
T56	678620	8561	0	0
T57	684685	4615	0	0
T59	88935	727	0	0
T174	51735	0	0	0
T293	0	2371	0	0
T294	0	2188	0	0
T295	0	646	0	0
T296	0	320	0	0
T297	0	423	0	0
T330	0	1478	0	0
T332	23429	0	0	0
T333	49193	0	0	0
T334	58663	0	0	0
T335	125937	0	0	0
T336	40146	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1546130	1337541	0	0
T1	361	135	0	0
T2	367	140	0	0
T3	433	208	0	0
T29	783	496	0	0
T30	1407	943	0	0
T31	1040	556	0	0
T56	5882	5656	0	0
T57	6032	5747	0	0
T59	1131	906	0	0
T63	360	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	170	0	0
T13	469436	1	0	0
T56	678620	21	0	0
T57	684685	12	0	0
T59	88935	2	0	0
T174	51735	0	0	0
T293	0	6	0	0
T294	0	5	0	0
T295	0	2	0	0
T296	0	1	0	0
T297	0	1	0	0
T330	0	4	0	0
T332	23429	0	0	0
T333	49193	0	0	0
T334	58663	0	0	0
T335	125937	0	0	0
T336	40146	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	118518051	0	0
T1	10008	9220	0	0
T2	10066	9233	0	0
T3	9804	9168	0	0
T29	27898	26616	0	0
T30	46569	45067	0	0
T31	29019	27738	0	0
T56	678620	677417	0	0
T57	684685	682666	0	0
T59	88935	88417	0	0
T63	10051	9228	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T123,T59,T56

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119298667	68267	0	0
DstReqKnown_A	1546130	1337541	0	0
SrcAckBusyChk_A	119298667	174	0	0
SrcBusyKnown_A	119298667	118518051	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	68267	0	0
T13	469436	416	0	0
T56	678620	7265	0	0
T57	684685	5807	0	0
T59	88935	798	0	0
T174	51735	0	0	0
T293	0	5593	0	0
T294	0	2934	0	0
T295	0	755	0	0
T296	0	2121	0	0
T297	0	379	0	0
T330	0	1456	0	0
T332	23429	0	0	0
T333	49193	0	0	0
T334	58663	0	0	0
T335	125937	0	0	0
T336	40146	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1546130	1337541	0	0
T1	361	135	0	0
T2	367	140	0	0
T3	433	208	0	0
T29	783	496	0	0
T30	1407	943	0	0
T31	1040	556	0	0
T56	5882	5656	0	0
T57	6032	5747	0	0
T59	1131	906	0	0
T63	360	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	174	0	0
T13	469436	1	0	0
T56	678620	18	0	0
T57	684685	15	0	0
T59	88935	2	0	0
T174	51735	0	0	0
T293	0	14	0	0
T294	0	7	0	0
T295	0	2	0	0
T296	0	6	0	0
T297	0	1	0	0
T330	0	4	0	0
T332	23429	0	0	0
T333	49193	0	0	0
T334	58663	0	0	0
T335	125937	0	0	0
T336	40146	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	118518051	0	0
T1	10008	9220	0	0
T2	10066	9233	0	0
T3	9804	9168	0	0
T29	27898	26616	0	0
T30	46569	45067	0	0
T31	29019	27738	0	0
T56	678620	677417	0	0
T57	684685	682666	0	0
T59	88935	88417	0	0
T63	10051	9228	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T59,T56,T57

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119298667	64952	0	0
DstReqKnown_A	1546130	1337541	0	0
SrcAckBusyChk_A	119298667	163	0	0
SrcBusyKnown_A	119298667	118518051	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	64952	0	0
T13	469436	407	0	0
T56	678620	1311	0	0
T57	684685	3270	0	0
T59	88935	763	0	0
T174	51735	0	0	0
T293	0	7147	0	0
T294	0	1873	0	0
T295	0	733	0	0
T296	0	619	0	0
T297	0	413	0	0
T330	0	249	0	0
T332	23429	0	0	0
T333	49193	0	0	0
T334	58663	0	0	0
T335	125937	0	0	0
T336	40146	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1546130	1337541	0	0
T1	361	135	0	0
T2	367	140	0	0
T3	433	208	0	0
T29	783	496	0	0
T30	1407	943	0	0
T31	1040	556	0	0
T56	5882	5656	0	0
T57	6032	5747	0	0
T59	1131	906	0	0
T63	360	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	163	0	0
T13	469436	1	0	0
T56	678620	3	0	0
T57	684685	9	0	0
T59	88935	2	0	0
T174	51735	0	0	0
T293	0	18	0	0
T294	0	4	0	0
T295	0	2	0	0
T296	0	2	0	0
T297	0	1	0	0
T330	0	1	0	0
T332	23429	0	0	0
T333	49193	0	0	0
T334	58663	0	0	0
T335	125937	0	0	0
T336	40146	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	118518051	0	0
T1	10008	9220	0	0
T2	10066	9233	0	0
T3	9804	9168	0	0
T29	27898	26616	0	0
T30	46569	45067	0	0
T31	29019	27738	0	0
T56	678620	677417	0	0
T57	684685	682666	0	0
T59	88935	88417	0	0
T63	10051	9228	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T351,T59,T56

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119298667	87938	0	0
DstReqKnown_A	1546130	1337541	0	0
SrcAckBusyChk_A	119298667	218	0	0
SrcBusyKnown_A	119298667	118518051	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	87938	0	0
T13	469436	422	0	0
T56	678620	4252	0	0
T57	684685	5519	0	0
T59	88935	866	0	0
T174	51735	0	0	0
T293	0	2267	0	0
T294	0	1883	0	0
T295	0	816	0	0
T296	0	2544	0	0
T297	0	446	0	0
T330	0	2775	0	0
T332	23429	0	0	0
T333	49193	0	0	0
T334	58663	0	0	0
T335	125937	0	0	0
T336	40146	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1546130	1337541	0	0
T1	361	135	0	0
T2	367	140	0	0
T3	433	208	0	0
T29	783	496	0	0
T30	1407	943	0	0
T31	1040	556	0	0
T56	5882	5656	0	0
T57	6032	5747	0	0
T59	1131	906	0	0
T63	360	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	218	0	0
T13	469436	1	0	0
T56	678620	10	0	0
T57	684685	14	0	0
T59	88935	2	0	0
T174	51735	0	0	0
T293	0	6	0	0
T294	0	4	0	0
T295	0	2	0	0
T296	0	7	0	0
T297	0	1	0	0
T330	0	7	0	0
T332	23429	0	0	0
T333	49193	0	0	0
T334	58663	0	0	0
T335	125937	0	0	0
T336	40146	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	118518051	0	0
T1	10008	9220	0	0
T2	10066	9233	0	0
T3	9804	9168	0	0
T29	27898	26616	0	0
T30	46569	45067	0	0
T31	29019	27738	0	0
T56	678620	677417	0	0
T57	684685	682666	0	0
T59	88935	88417	0	0
T63	10051	9228	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T59,T56,T57

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Unreachable
1	0	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119298667	73687	0	0
DstReqKnown_A	1546130	1337541	0	0
SrcAckBusyChk_A	119298667	183	0	0
SrcBusyKnown_A	119298667	118518051	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	73687	0	0
T13	469436	393	0	0
T56	678620	4508	0	0
T57	684685	5047	0	0
T59	88935	896	0	0
T174	51735	0	0	0
T293	0	4687	0	0
T294	0	900	0	0
T295	0	698	0	0
T296	0	3820	0	0
T297	0	448	0	0
T330	0	1977	0	0
T332	23429	0	0	0
T333	49193	0	0	0
T334	58663	0	0	0
T335	125937	0	0	0
T336	40146	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1546130	1337541	0	0
T1	361	135	0	0
T2	367	140	0	0
T3	433	208	0	0
T29	783	496	0	0
T30	1407	943	0	0
T31	1040	556	0	0
T56	5882	5656	0	0
T57	6032	5747	0	0
T59	1131	906	0	0
T63	360	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	183	0	0
T13	469436	1	0	0
T56	678620	11	0	0
T57	684685	13	0	0
T59	88935	2	0	0
T174	51735	0	0	0
T293	0	12	0	0
T294	0	2	0	0
T295	0	2	0	0
T296	0	10	0	0
T297	0	1	0	0
T330	0	5	0	0
T332	23429	0	0	0
T333	49193	0	0	0
T334	58663	0	0	0
T335	125937	0	0	0
T336	40146	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	118518051	0	0
T1	10008	9220	0	0
T2	10066	9233	0	0
T3	9804	9168	0	0
T29	27898	26616	0	0
T30	46569	45067	0	0
T31	29019	27738	0	0
T56	678620	677417	0	0
T57	684685	682666	0	0
T59	88935	88417	0	0
T63	10051	9228	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Unreachable
1	0	Covered	T59,T349,T346

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Covered	T7,T8,T9
1	0	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T59,T56,T57
1	1	Covered	T59,T56,T57

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Not Covered
1	1	Covered	T7,T8,T9

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T29,T30,T31
0	1	-	Covered	T59,T56,T57
0	0	1	Covered	T59,T56,T57
0	0	0	Covered	T29,T30,T31

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119298667	111036	0	0
DstReqKnown_A	1546130	1337541	0	0
SrcAckBusyChk_A	119298667	238	0	0
SrcBusyKnown_A	119298667	118518051	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	111036	0	0
T8	41329	2418	0	0
T10	155807	1564	0	0
T14	0	1384	0	0
T15	0	1493	0	0
T16	0	2787	0	0
T56	678620	8720	0	0
T57	684685	7962	0	0
T59	88935	853	0	0
T79	0	758	0	0
T80	0	705	0	0
T85	54565	0	0	0
T86	43809	0	0	0
T105	50258	0	0	0
T211	66089	0	0	0
T214	23015	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1546130	1337541	0	0
T1	361	135	0	0
T2	367	140	0	0
T3	433	208	0	0
T29	783	496	0	0
T30	1407	943	0	0
T31	1040	556	0	0
T56	5882	5656	0	0
T57	6032	5747	0	0
T59	1131	906	0	0
T63	360	134	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	238	0	0
T8	41329	5	0	0
T10	155807	4	0	0
T14	0	4	0	0
T15	0	4	0	0
T16	0	6	0	0
T56	678620	17	0	0
T57	684685	16	0	0
T59	88935	2	0	0
T79	0	2	0	0
T80	0	2	0	0
T85	54565	0	0	0
T86	43809	0	0	0
T105	50258	0	0	0
T211	66089	0	0	0
T214	23015	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119298667	118518051	0	0
T1	10008	9220	0	0
T2	10066	9233	0	0
T3	9804	9168	0	0
T29	27898	26616	0	0
T30	46569	45067	0	0
T31	29019	27738	0	0
T56	678620	677417	0	0
T57	684685	682666	0	0
T59	88935	88417	0	0
T63	10051	9228	0	0