Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_io_intr
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| CONT_ASSIGN | 47 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 52 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
| ALWAYS | 80 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 47 |
1 |
1 |
| 49 |
1 |
1 |
| 52 |
1 |
1 |
| 54 |
1 |
1 |
| 80 |
1 |
1 |
| 81 |
1 |
1 |
| 83 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_io_intr
| Total | Covered | Percent |
|---|
| Conditions | 12 | 12 | 100.00 |
| Logical | 12 | 12 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 47
EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
-----------------------------1---------------------------- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T143,T166,T167 |
LINE 47
SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
----------------1---------------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T143,T166,T167 |
| 1 | 1 | Covered | T143,T166,T167 |
LINE 52
EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
-----------1---------- ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 83
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T143,T98,T322 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T143,T88,T98 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_io_intr
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
80 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 80 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_io_intr
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
IntrTKind_A |
958 |
958 |
0 |
0 |
IntrTKind_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
958 |
958 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T23 |
1 |
1 |
0 |
0 |
| T49 |
1 |
1 |
0 |
0 |
| T65 |
1 |
1 |
0 |
0 |
| T66 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_init_intr
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 7 | 7 | 100.00 |
| CONT_ASSIGN | 47 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 52 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 54 | 1 | 1 | 100.00 |
| ALWAYS | 80 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 47 |
1 |
1 |
| 49 |
1 |
1 |
| 52 |
1 |
1 |
| 54 |
1 |
1 |
| 80 |
1 |
1 |
| 81 |
1 |
1 |
| 83 |
1 |
1 |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_init_intr
| Total | Covered | Percent |
|---|
| Conditions | 12 | 12 | 100.00 |
| Logical | 12 | 12 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 47
EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
-----------------------------1---------------------------- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T143,T166,T167 |
LINE 47
SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
----------------1---------------- ----------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T143,T166,T167 |
| 1 | 1 | Covered | T143,T166,T167 |
LINE 52
EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
-----------1---------- ----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 83
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T143,T166,T167 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T143,T88,T166 |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_init_intr
| Line No. | Total | Covered | Percent |
| Branches |
|
2 |
2 |
100.00 |
| IF |
80 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 80 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_init_intr
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
IntrTKind_A |
958 |
958 |
0 |
0 |
IntrTKind_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
958 |
958 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T16 |
1 |
1 |
0 |
0 |
| T17 |
1 |
1 |
0 |
0 |
| T18 |
1 |
1 |
0 |
0 |
| T23 |
1 |
1 |
0 |
0 |
| T49 |
1 |
1 |
0 |
0 |
| T65 |
1 |
1 |
0 |
0 |
| T66 |
1 |
1 |
0 |
0 |