Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	400757241	46022109	0	0
DepthKnown_A	400757241	400657751	0	0
RvalidKnown_A	400757241	400657751	0	0
WreadyKnown_A	400757241	400657751	0	0
gen_passthru_fifo.paramCheckPass	958	958	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	46022109	0	0
T1	110565	14036	0	0
T2	150727	21437	0	0
T3	247509	30583	0	0
T16	445248	55535	0	0
T17	249743	25412	0	0
T18	190191	25149	0	0
T23	879715	101432	0	0
T49	175099	3464	0	0
T65	280776	34021	0	0
T66	74306	7435	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	400657751	0	0
T1	110565	110507	0	0
T2	150727	150676	0	0
T3	247509	247451	0	0
T16	445248	445087	0	0
T17	249743	249633	0	0
T18	190191	190071	0	0
T23	879715	879664	0	0
T49	175099	175044	0	0
T65	280776	280714	0	0
T66	74306	74244	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	400657751	0	0
T1	110565	110507	0	0
T2	150727	150676	0	0
T3	247509	247451	0	0
T16	445248	445087	0	0
T17	249743	249633	0	0
T18	190191	190071	0	0
T23	879715	879664	0	0
T49	175099	175044	0	0
T65	280776	280714	0	0
T66	74306	74244	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	400657751	0	0
T1	110565	110507	0	0
T2	150727	150676	0	0
T3	247509	247451	0	0
T16	445248	445087	0	0
T17	249743	249633	0	0
T18	190191	190071	0	0
T23	879715	879664	0	0
T49	175099	175044	0	0
T65	280776	280714	0	0
T66	74306	74244	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	958	958	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T23	1	1	0	0
T49	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	400757241	35302586	0	0
DepthKnown_A	400757241	400657751	0	0
RvalidKnown_A	400757241	400657751	0	0
WreadyKnown_A	400757241	400657751	0	0
gen_passthru_fifo.paramCheckPass	958	958	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	35302586	0	0
T1	110565	10818	0	0
T2	150727	15670	0	0
T3	247509	25030	0	0
T16	445248	43726	0	0
T17	249743	18289	0	0
T18	190191	18616	0	0
T23	879715	84075	0	0
T49	175099	1868	0	0
T65	280776	30040	0	0
T66	74306	5759	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	400657751	0	0
T1	110565	110507	0	0
T2	150727	150676	0	0
T3	247509	247451	0	0
T16	445248	445087	0	0
T17	249743	249633	0	0
T18	190191	190071	0	0
T23	879715	879664	0	0
T49	175099	175044	0	0
T65	280776	280714	0	0
T66	74306	74244	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	400657751	0	0
T1	110565	110507	0	0
T2	150727	150676	0	0
T3	247509	247451	0	0
T16	445248	445087	0	0
T17	249743	249633	0	0
T18	190191	190071	0	0
T23	879715	879664	0	0
T49	175099	175044	0	0
T65	280776	280714	0	0
T66	74306	74244	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	400657751	0	0
T1	110565	110507	0	0
T2	150727	150676	0	0
T3	247509	247451	0	0
T16	445248	445087	0	0
T17	249743	249633	0	0
T18	190191	190071	0	0
T23	879715	879664	0	0
T49	175099	175044	0	0
T65	280776	280714	0	0
T66	74306	74244	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	958	958	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T23	1	1	0	0
T49	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	400757241	34124452	0	0
DepthKnown_A	400757241	400657751	0	0
RvalidKnown_A	400757241	400657751	0	0
WreadyKnown_A	400757241	400657751	0	0
gen_passthru_fifo.paramCheckPass	958	958	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	34124452	0	0
T1	110565	10260	0	0
T2	150727	8899	0	0
T3	247509	17739	0	0
T16	445248	23333	0	0
T17	249743	12648	0	0
T18	190191	13891	0	0
T23	879715	149983	0	0
T49	175099	465	0	0
T65	280776	25443	0	0
T66	74306	4604	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	400657751	0	0
T1	110565	110507	0	0
T2	150727	150676	0	0
T3	247509	247451	0	0
T16	445248	445087	0	0
T17	249743	249633	0	0
T18	190191	190071	0	0
T23	879715	879664	0	0
T49	175099	175044	0	0
T65	280776	280714	0	0
T66	74306	74244	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	400657751	0	0
T1	110565	110507	0	0
T2	150727	150676	0	0
T3	247509	247451	0	0
T16	445248	445087	0	0
T17	249743	249633	0	0
T18	190191	190071	0	0
T23	879715	879664	0	0
T49	175099	175044	0	0
T65	280776	280714	0	0
T66	74306	74244	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	400657751	0	0
T1	110565	110507	0	0
T2	150727	150676	0	0
T3	247509	247451	0	0
T16	445248	445087	0	0
T17	249743	249633	0	0
T18	190191	190071	0	0
T23	879715	879664	0	0
T49	175099	175044	0	0
T65	280776	280714	0	0
T66	74306	74244	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	958	958	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T23	1	1	0	0
T49	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	400757241	28509733	0	0
DepthKnown_A	400757241	400657751	0	0
RvalidKnown_A	400757241	400657751	0	0
WreadyKnown_A	400757241	400657751	0	0
gen_passthru_fifo.paramCheckPass	958	958	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	28509733	0	0
T1	110565	10114	0	0
T2	150727	8640	0	0
T3	247509	17322	0	0
T16	445248	22623	0	0
T17	249743	12317	0	0
T18	190191	13488	0	0
T23	879715	91932	0	0
T49	175099	354	0	0
T65	280776	25263	0	0
T66	74306	4494	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	400657751	0	0
T1	110565	110507	0	0
T2	150727	150676	0	0
T3	247509	247451	0	0
T16	445248	445087	0	0
T17	249743	249633	0	0
T18	190191	190071	0	0
T23	879715	879664	0	0
T49	175099	175044	0	0
T65	280776	280714	0	0
T66	74306	74244	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	400657751	0	0
T1	110565	110507	0	0
T2	150727	150676	0	0
T3	247509	247451	0	0
T16	445248	445087	0	0
T17	249743	249633	0	0
T18	190191	190071	0	0
T23	879715	879664	0	0
T49	175099	175044	0	0
T65	280776	280714	0	0
T66	74306	74244	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	400657751	0	0
T1	110565	110507	0	0
T2	150727	150676	0	0
T3	247509	247451	0	0
T16	445248	445087	0	0
T17	249743	249633	0	0
T18	190191	190071	0	0
T23	879715	879664	0	0
T49	175099	175044	0	0
T65	280776	280714	0	0
T66	74306	74244	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	958	958	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T23	1	1	0	0
T49	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	400757241	82174	0	0
DepthKnown_A	400757241	400657751	0	0
RvalidKnown_A	400757241	400657751	0	0
WreadyKnown_A	400757241	400657751	0	0
gen_passthru_fifo.paramCheckPass	958	958	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	82174	0	0
T1	110565	16	0	0
T2	150727	26	0	0
T3	247509	215	0	0
T16	445248	77	0	0
T17	249743	102	0	0
T18	190191	37	0	0
T23	879715	33	0	0
T49	175099	8	0	0
T65	280776	23	0	0
T66	74306	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	400657751	0	0
T1	110565	110507	0	0
T2	150727	150676	0	0
T3	247509	247451	0	0
T16	445248	445087	0	0
T17	249743	249633	0	0
T18	190191	190071	0	0
T23	879715	879664	0	0
T49	175099	175044	0	0
T65	280776	280714	0	0
T66	74306	74244	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	400657751	0	0
T1	110565	110507	0	0
T2	150727	150676	0	0
T3	247509	247451	0	0
T16	445248	445087	0	0
T17	249743	249633	0	0
T18	190191	190071	0	0
T23	879715	879664	0	0
T49	175099	175044	0	0
T65	280776	280714	0	0
T66	74306	74244	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	400657751	0	0
T1	110565	110507	0	0
T2	150727	150676	0	0
T3	247509	247451	0	0
T16	445248	445087	0	0
T17	249743	249633	0	0
T18	190191	190071	0	0
T23	879715	879664	0	0
T49	175099	175044	0	0
T65	280776	280714	0	0
T66	74306	74244	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	958	958	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T23	1	1	0	0
T49	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	400757241	82174	0	0
DepthKnown_A	400757241	400657751	0	0
RvalidKnown_A	400757241	400657751	0	0
WreadyKnown_A	400757241	400657751	0	0
gen_passthru_fifo.paramCheckPass	958	958	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	82174	0	0
T1	110565	16	0	0
T2	150727	26	0	0
T3	247509	215	0	0
T16	445248	77	0	0
T17	249743	102	0	0
T18	190191	37	0	0
T23	879715	33	0	0
T49	175099	8	0	0
T65	280776	23	0	0
T66	74306	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	400657751	0	0
T1	110565	110507	0	0
T2	150727	150676	0	0
T3	247509	247451	0	0
T16	445248	445087	0	0
T17	249743	249633	0	0
T18	190191	190071	0	0
T23	879715	879664	0	0
T49	175099	175044	0	0
T65	280776	280714	0	0
T66	74306	74244	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	400657751	0	0
T1	110565	110507	0	0
T2	150727	150676	0	0
T3	247509	247451	0	0
T16	445248	445087	0	0
T17	249743	249633	0	0
T18	190191	190071	0	0
T23	879715	879664	0	0
T49	175099	175044	0	0
T65	280776	280714	0	0
T66	74306	74244	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	400657751	0	0
T1	110565	110507	0	0
T2	150727	150676	0	0
T3	247509	247451	0	0
T16	445248	445087	0	0
T17	249743	249633	0	0
T18	190191	190071	0	0
T23	879715	879664	0	0
T49	175099	175044	0	0
T65	280776	280714	0	0
T66	74306	74244	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	958	958	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T23	1	1	0	0
T49	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	400757241	49138	0	0
DepthKnown_A	400757241	400657751	0	0
RvalidKnown_A	400757241	400657751	0	0
WreadyKnown_A	400757241	400657751	0	0
gen_passthru_fifo.paramCheckPass	958	958	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	49138	0	0
T1	110565	13	0	0
T2	150727	23	0	0
T3	247509	212	0	0
T16	445248	74	0	0
T17	249743	94	0	0
T18	190191	35	0	0
T23	879715	12	0	0
T49	175099	8	0	0
T65	280776	20	0	0
T66	74306	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	400657751	0	0
T1	110565	110507	0	0
T2	150727	150676	0	0
T3	247509	247451	0	0
T16	445248	445087	0	0
T17	249743	249633	0	0
T18	190191	190071	0	0
T23	879715	879664	0	0
T49	175099	175044	0	0
T65	280776	280714	0	0
T66	74306	74244	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	400657751	0	0
T1	110565	110507	0	0
T2	150727	150676	0	0
T3	247509	247451	0	0
T16	445248	445087	0	0
T17	249743	249633	0	0
T18	190191	190071	0	0
T23	879715	879664	0	0
T49	175099	175044	0	0
T65	280776	280714	0	0
T66	74306	74244	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	400657751	0	0
T1	110565	110507	0	0
T2	150727	150676	0	0
T3	247509	247451	0	0
T16	445248	445087	0	0
T17	249743	249633	0	0
T18	190191	190071	0	0
T23	879715	879664	0	0
T49	175099	175044	0	0
T65	280776	280714	0	0
T66	74306	74244	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	958	958	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T23	1	1	0	0
T49	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	400757241	49138	0	0
DepthKnown_A	400757241	400657751	0	0
RvalidKnown_A	400757241	400657751	0	0
WreadyKnown_A	400757241	400657751	0	0
gen_passthru_fifo.paramCheckPass	958	958	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	49138	0	0
T1	110565	13	0	0
T2	150727	23	0	0
T3	247509	212	0	0
T16	445248	74	0	0
T17	249743	94	0	0
T18	190191	35	0	0
T23	879715	12	0	0
T49	175099	8	0	0
T65	280776	20	0	0
T66	74306	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	400657751	0	0
T1	110565	110507	0	0
T2	150727	150676	0	0
T3	247509	247451	0	0
T16	445248	445087	0	0
T17	249743	249633	0	0
T18	190191	190071	0	0
T23	879715	879664	0	0
T49	175099	175044	0	0
T65	280776	280714	0	0
T66	74306	74244	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	400657751	0	0
T1	110565	110507	0	0
T2	150727	150676	0	0
T3	247509	247451	0	0
T16	445248	445087	0	0
T17	249743	249633	0	0
T18	190191	190071	0	0
T23	879715	879664	0	0
T49	175099	175044	0	0
T65	280776	280714	0	0
T66	74306	74244	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	400657751	0	0
T1	110565	110507	0	0
T2	150727	150676	0	0
T3	247509	247451	0	0
T16	445248	445087	0	0
T17	249743	249633	0	0
T18	190191	190071	0	0
T23	879715	879664	0	0
T49	175099	175044	0	0
T65	280776	280714	0	0
T66	74306	74244	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	958	958	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T23	1	1	0	0
T49	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	400757241	33036	0	0
DepthKnown_A	400757241	400657751	0	0
RvalidKnown_A	400757241	400657751	0	0
WreadyKnown_A	400757241	400657751	0	0
gen_passthru_fifo.paramCheckPass	958	958	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	33036	0	0
T1	110565	3	0	0
T2	150727	3	0	0
T3	247509	3	0	0
T16	445248	3	0	0
T17	249743	8	0	0
T18	190191	2	0	0
T23	879715	21	0	0
T44	0	2	0	0
T49	175099	0	0	0
T65	280776	3	0	0
T66	74306	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	400657751	0	0
T1	110565	110507	0	0
T2	150727	150676	0	0
T3	247509	247451	0	0
T16	445248	445087	0	0
T17	249743	249633	0	0
T18	190191	190071	0	0
T23	879715	879664	0	0
T49	175099	175044	0	0
T65	280776	280714	0	0
T66	74306	74244	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	400657751	0	0
T1	110565	110507	0	0
T2	150727	150676	0	0
T3	247509	247451	0	0
T16	445248	445087	0	0
T17	249743	249633	0	0
T18	190191	190071	0	0
T23	879715	879664	0	0
T49	175099	175044	0	0
T65	280776	280714	0	0
T66	74306	74244	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	400657751	0	0
T1	110565	110507	0	0
T2	150727	150676	0	0
T3	247509	247451	0	0
T16	445248	445087	0	0
T17	249743	249633	0	0
T18	190191	190071	0	0
T23	879715	879664	0	0
T49	175099	175044	0	0
T65	280776	280714	0	0
T66	74306	74244	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	958	958	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T23	1	1	0	0
T49	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	400757241	33036	0	0
DepthKnown_A	400757241	400657751	0	0
RvalidKnown_A	400757241	400657751	0	0
WreadyKnown_A	400757241	400657751	0	0
gen_passthru_fifo.paramCheckPass	958	958	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	33036	0	0
T1	110565	3	0	0
T2	150727	3	0	0
T3	247509	3	0	0
T16	445248	3	0	0
T17	249743	8	0	0
T18	190191	2	0	0
T23	879715	21	0	0
T44	0	2	0	0
T49	175099	0	0	0
T65	280776	3	0	0
T66	74306	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	400657751	0	0
T1	110565	110507	0	0
T2	150727	150676	0	0
T3	247509	247451	0	0
T16	445248	445087	0	0
T17	249743	249633	0	0
T18	190191	190071	0	0
T23	879715	879664	0	0
T49	175099	175044	0	0
T65	280776	280714	0	0
T66	74306	74244	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	400657751	0	0
T1	110565	110507	0	0
T2	150727	150676	0	0
T3	247509	247451	0	0
T16	445248	445087	0	0
T17	249743	249633	0	0
T18	190191	190071	0	0
T23	879715	879664	0	0
T49	175099	175044	0	0
T65	280776	280714	0	0
T66	74306	74244	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400757241	400657751	0	0
T1	110565	110507	0	0
T2	150727	150676	0	0
T3	247509	247451	0	0
T16	445248	445087	0	0
T17	249743	249633	0	0
T18	190191	190071	0	0
T23	879715	879664	0	0
T49	175099	175044	0	0
T65	280776	280714	0	0
T66	74306	74244	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	958	958	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T23	1	1	0	0
T49	1	1	0	0
T65	1	1	0	0
T66	1	1	0	0