Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo	75.00	50.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	140684642	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	21020	21020	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	140684642	0	0
T1	373060	18653	0	0
T2	301502	13350	0	0
T3	299204	12939	0	0
T7	494619	34444	0	0
T17	423312	48354	0	0
T18	656436	54631	0	0
T19	664086	53117	0	0
T20	1509957	99783	0	0
T28	72288	25	0	0
T35	1806189	640737	0	0
T45	373890	45920	0	0
T59	328346	14787	0	0
T60	300748	12912	0	0
T61	341690	10186	0	0
T62	346098	9609	0	0
T63	401998	21251	0	0
T64	344634	10518	0	0
T65	283484	8398	0	0
T77	1011592	75824	0	0
T78	297888	35947	0	0
T86	1436124	108880	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1865300	1863590	0	0
T2	1507510	1505870	0	0
T3	1496020	1494280	0	0
T28	433728	433074	0	0
T29	763464	762786	0	0
T30	666822	665466	0	0
T59	1641730	1640130	0	0
T60	1503740	1502170	0	0
T61	1708450	1706700	0	0
T62	692196	691524	0	0
T63	803996	803324	0	0
T64	689268	688568	0	0
T65	566968	566268	0	0
T122	1151292	1149894	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1865300	1863590	0	0
T2	1507510	1505870	0	0
T3	1496020	1494280	0	0
T28	433728	433074	0	0
T29	763464	762786	0	0
T30	666822	665466	0	0
T59	1641730	1640130	0	0
T60	1503740	1502170	0	0
T61	1708450	1706700	0	0
T62	692196	691524	0	0
T63	803996	803324	0	0
T64	689268	688568	0	0
T65	566968	566268	0	0
T122	1151292	1149894	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1865300	1863590	0	0
T2	1507510	1505870	0	0
T3	1496020	1494280	0	0
T28	433728	433074	0	0
T29	763464	762786	0	0
T30	666822	665466	0	0
T59	1641730	1640130	0	0
T60	1503740	1502170	0	0
T61	1708450	1706700	0	0
T62	692196	691524	0	0
T63	803996	803324	0	0
T64	689268	688568	0	0
T65	566968	566268	0	0
T122	1151292	1149894	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	21020	21020	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T28	6	6	0	0
T31	6	6	0	0
T32	6	6	0	0
T53	6	6	0	0
T54	6	6	0	0
T59	4	4	0	0
T60	4	4	0	0
T61	4	4	0	0
T62	4	4	0	0
T63	4	4	0	0
T64	4	4	0	0
T65	4	4	0	0
T102	6	6	0	0
T221	6	6	0	0
T222	6	6	0	0
T223	6	6	0	0
T224	6	6	0	0