Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	398552666	45459575	0	0
DepthKnown_A	398552666	398453010	0	0
RvalidKnown_A	398552666	398453010	0	0
WreadyKnown_A	398552666	398453010	0	0
gen_passthru_fifo.paramCheckPass	956	956	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	45459575	0	0
T7	164873	19764	0	0
T17	141104	26168	0	0
T18	218812	31698	0	0
T19	221362	30344	0	0
T20	503319	58734	0	0
T35	602063	425113	0	0
T45	186945	24329	0	0
T77	505796	44817	0	0
T78	148944	22370	0	0
T86	478708	60422	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	398453010	0	0
T1	186530	186359	0	0
T2	150751	150587	0	0
T3	149602	149428	0	0
T59	164173	164013	0	0
T60	150374	150217	0	0
T61	170845	170670	0	0
T62	173049	172881	0	0
T63	200999	200831	0	0
T64	172317	172142	0	0
T65	141742	141567	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	398453010	0	0
T1	186530	186359	0	0
T2	150751	150587	0	0
T3	149602	149428	0	0
T59	164173	164013	0	0
T60	150374	150217	0	0
T61	170845	170670	0	0
T62	173049	172881	0	0
T63	200999	200831	0	0
T64	172317	172142	0	0
T65	141742	141567	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	398453010	0	0
T1	186530	186359	0	0
T2	150751	150587	0	0
T3	149602	149428	0	0
T59	164173	164013	0	0
T60	150374	150217	0	0
T61	170845	170670	0	0
T62	173049	172881	0	0
T63	200999	200831	0	0
T64	172317	172142	0	0
T65	141742	141567	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	398552666	34811026	0	0
DepthKnown_A	398552666	398453010	0	0
RvalidKnown_A	398552666	398453010	0	0
WreadyKnown_A	398552666	398453010	0	0
gen_passthru_fifo.paramCheckPass	956	956	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	34811026	0	0
T7	164873	14645	0	0
T17	141104	22157	0	0
T18	218812	22905	0	0
T19	221362	22702	0	0
T20	503319	40937	0	0
T35	602063	215608	0	0
T45	186945	21591	0	0
T77	505796	31007	0	0
T78	148944	13577	0	0
T86	478708	48381	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	398453010	0	0
T1	186530	186359	0	0
T2	150751	150587	0	0
T3	149602	149428	0	0
T59	164173	164013	0	0
T60	150374	150217	0	0
T61	170845	170670	0	0
T62	173049	172881	0	0
T63	200999	200831	0	0
T64	172317	172142	0	0
T65	141742	141567	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	398453010	0	0
T1	186530	186359	0	0
T2	150751	150587	0	0
T3	149602	149428	0	0
T59	164173	164013	0	0
T60	150374	150217	0	0
T61	170845	170670	0	0
T62	173049	172881	0	0
T63	200999	200831	0	0
T64	172317	172142	0	0
T65	141742	141567	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	398453010	0	0
T1	186530	186359	0	0
T2	150751	150587	0	0
T3	149602	149428	0	0
T59	164173	164013	0	0
T60	150374	150217	0	0
T61	170845	170670	0	0
T62	173049	172881	0	0
T63	200999	200831	0	0
T64	172317	172142	0	0
T65	141742	141567	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	398552666	32580025	0	0
DepthKnown_A	398552666	398453010	0	0
RvalidKnown_A	398552666	398453010	0	0
WreadyKnown_A	398552666	398453010	0	0
gen_passthru_fifo.paramCheckPass	956	956	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	32580025	0	0
T1	186530	3794	0	0
T2	150751	2769	0	0
T3	149602	2698	0	0
T59	164173	2991	0	0
T60	150374	2685	0	0
T61	170845	6214	0	0
T62	173049	5593	0	0
T63	200999	4409	0	0
T64	172317	6458	0	0
T65	141742	5516	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	398453010	0	0
T1	186530	186359	0	0
T2	150751	150587	0	0
T3	149602	149428	0	0
T59	164173	164013	0	0
T60	150374	150217	0	0
T61	170845	170670	0	0
T62	173049	172881	0	0
T63	200999	200831	0	0
T64	172317	172142	0	0
T65	141742	141567	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	398453010	0	0
T1	186530	186359	0	0
T2	150751	150587	0	0
T3	149602	149428	0	0
T59	164173	164013	0	0
T60	150374	150217	0	0
T61	170845	170670	0	0
T62	173049	172881	0	0
T63	200999	200831	0	0
T64	172317	172142	0	0
T65	141742	141567	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	398453010	0	0
T1	186530	186359	0	0
T2	150751	150587	0	0
T3	149602	149428	0	0
T59	164173	164013	0	0
T60	150374	150217	0	0
T61	170845	170670	0	0
T62	173049	172881	0	0
T63	200999	200831	0	0
T64	172317	172142	0	0
T65	141742	141567	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	398552666	27397112	0	0
DepthKnown_A	398552666	398453010	0	0
RvalidKnown_A	398552666	398453010	0	0
WreadyKnown_A	398552666	398453010	0	0
gen_passthru_fifo.paramCheckPass	956	956	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	27397112	0	0
T1	186530	14859	0	0
T2	150751	10581	0	0
T3	149602	10241	0	0
T59	164173	11796	0	0
T60	150374	10227	0	0
T61	170845	3972	0	0
T62	173049	4016	0	0
T63	200999	16842	0	0
T64	172317	4060	0	0
T65	141742	2882	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	398453010	0	0
T1	186530	186359	0	0
T2	150751	150587	0	0
T3	149602	149428	0	0
T59	164173	164013	0	0
T60	150374	150217	0	0
T61	170845	170670	0	0
T62	173049	172881	0	0
T63	200999	200831	0	0
T64	172317	172142	0	0
T65	141742	141567	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	398453010	0	0
T1	186530	186359	0	0
T2	150751	150587	0	0
T3	149602	149428	0	0
T59	164173	164013	0	0
T60	150374	150217	0	0
T61	170845	170670	0	0
T62	173049	172881	0	0
T63	200999	200831	0	0
T64	172317	172142	0	0
T65	141742	141567	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	398453010	0	0
T1	186530	186359	0	0
T2	150751	150587	0	0
T3	149602	149428	0	0
T59	164173	164013	0	0
T60	150374	150217	0	0
T61	170845	170670	0	0
T62	173049	172881	0	0
T63	200999	200831	0	0
T64	172317	172142	0	0
T65	141742	141567	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	478357528	107771	0	0
DepthKnown_A	478357528	478242073	0	0
RvalidKnown_A	478357528	478242073	0	0
WreadyKnown_A	478357528	478242073	0	0
gen_passthru_fifo.paramCheckPass	2866	2866	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478357528	107771	0	0
T7	164873	35	0	0
T17	141104	29	0	0
T18	218812	28	0	0
T19	221362	71	0	0
T20	503319	112	0	0
T28	72288	25	0	0
T29	127244	50	0	0
T35	602063	16	0	0
T86	478708	77	0	0
T122	191882	50	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478357528	478242073	0	0
T1	186530	186359	0	0
T2	150751	150587	0	0
T3	149602	149428	0	0
T28	72288	72179	0	0
T29	127244	127131	0	0
T30	111137	110911	0	0
T59	164173	164013	0	0
T60	150374	150217	0	0
T61	170845	170670	0	0
T122	191882	191649	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478357528	478242073	0	0
T1	186530	186359	0	0
T2	150751	150587	0	0
T3	149602	149428	0	0
T28	72288	72179	0	0
T29	127244	127131	0	0
T30	111137	110911	0	0
T59	164173	164013	0	0
T60	150374	150217	0	0
T61	170845	170670	0	0
T122	191882	191649	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478357528	478242073	0	0
T1	186530	186359	0	0
T2	150751	150587	0	0
T3	149602	149428	0	0
T28	72288	72179	0	0
T29	127244	127131	0	0
T30	111137	110911	0	0
T59	164173	164013	0	0
T60	150374	150217	0	0
T61	170845	170670	0	0
T122	191882	191649	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2866	2866	0	0
T28	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T102	1	1	0	0
T221	1	1	0	0
T222	1	1	0	0
T223	1	1	0	0
T224	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	478357528	110681	0	0
DepthKnown_A	478357528	478242073	0	0
RvalidKnown_A	478357528	478242073	0	0
WreadyKnown_A	478357528	478242073	0	0
gen_passthru_fifo.paramCheckPass	2866	2866	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478357528	110681	0	0
T7	164873	35	0	0
T17	141104	29	0	0
T18	218812	28	0	0
T19	221362	71	0	0
T20	503319	112	0	0
T28	72288	25	0	0
T29	127244	50	0	0
T35	602063	16	0	0
T86	478708	77	0	0
T122	191882	50	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478357528	478242073	0	0
T1	186530	186359	0	0
T2	150751	150587	0	0
T3	149602	149428	0	0
T28	72288	72179	0	0
T29	127244	127131	0	0
T30	111137	110911	0	0
T59	164173	164013	0	0
T60	150374	150217	0	0
T61	170845	170670	0	0
T122	191882	191649	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478357528	478242073	0	0
T1	186530	186359	0	0
T2	150751	150587	0	0
T3	149602	149428	0	0
T28	72288	72179	0	0
T29	127244	127131	0	0
T30	111137	110911	0	0
T59	164173	164013	0	0
T60	150374	150217	0	0
T61	170845	170670	0	0
T122	191882	191649	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478357528	478242073	0	0
T1	186530	186359	0	0
T2	150751	150587	0	0
T3	149602	149428	0	0
T28	72288	72179	0	0
T29	127244	127131	0	0
T30	111137	110911	0	0
T59	164173	164013	0	0
T60	150374	150217	0	0
T61	170845	170670	0	0
T122	191882	191649	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2866	2866	0	0
T28	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T102	1	1	0	0
T221	1	1	0	0
T222	1	1	0	0
T223	1	1	0	0
T224	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	478357528	50911	0	0
DepthKnown_A	478357528	478242073	0	0
RvalidKnown_A	478357528	478242073	0	0
WreadyKnown_A	478357528	478242073	0	0
gen_passthru_fifo.paramCheckPass	2866	2866	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478357528	50911	0	0
T7	164873	31	0	0
T17	141104	28	0	0
T18	218812	26	0	0
T19	221362	69	0	0
T20	503319	97	0	0
T35	602063	5	0	0
T45	186945	77	0	0
T77	505796	176	0	0
T78	148944	26	0	0
T86	478708	74	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478357528	478242073	0	0
T1	186530	186359	0	0
T2	150751	150587	0	0
T3	149602	149428	0	0
T28	72288	72179	0	0
T29	127244	127131	0	0
T30	111137	110911	0	0
T59	164173	164013	0	0
T60	150374	150217	0	0
T61	170845	170670	0	0
T122	191882	191649	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478357528	478242073	0	0
T1	186530	186359	0	0
T2	150751	150587	0	0
T3	149602	149428	0	0
T28	72288	72179	0	0
T29	127244	127131	0	0
T30	111137	110911	0	0
T59	164173	164013	0	0
T60	150374	150217	0	0
T61	170845	170670	0	0
T122	191882	191649	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478357528	478242073	0	0
T1	186530	186359	0	0
T2	150751	150587	0	0
T3	149602	149428	0	0
T28	72288	72179	0	0
T29	127244	127131	0	0
T30	111137	110911	0	0
T59	164173	164013	0	0
T60	150374	150217	0	0
T61	170845	170670	0	0
T122	191882	191649	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2866	2866	0	0
T28	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T102	1	1	0	0
T221	1	1	0	0
T222	1	1	0	0
T223	1	1	0	0
T224	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	478357528	50911	0	0
DepthKnown_A	478357528	478242073	0	0
RvalidKnown_A	478357528	478242073	0	0
WreadyKnown_A	478357528	478242073	0	0
gen_passthru_fifo.paramCheckPass	2866	2866	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478357528	50911	0	0
T7	164873	31	0	0
T17	141104	28	0	0
T18	218812	26	0	0
T19	221362	69	0	0
T20	503319	97	0	0
T35	602063	5	0	0
T45	186945	77	0	0
T77	505796	176	0	0
T78	148944	26	0	0
T86	478708	74	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478357528	478242073	0	0
T1	186530	186359	0	0
T2	150751	150587	0	0
T3	149602	149428	0	0
T28	72288	72179	0	0
T29	127244	127131	0	0
T30	111137	110911	0	0
T59	164173	164013	0	0
T60	150374	150217	0	0
T61	170845	170670	0	0
T122	191882	191649	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478357528	478242073	0	0
T1	186530	186359	0	0
T2	150751	150587	0	0
T3	149602	149428	0	0
T28	72288	72179	0	0
T29	127244	127131	0	0
T30	111137	110911	0	0
T59	164173	164013	0	0
T60	150374	150217	0	0
T61	170845	170670	0	0
T122	191882	191649	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478357528	478242073	0	0
T1	186530	186359	0	0
T2	150751	150587	0	0
T3	149602	149428	0	0
T28	72288	72179	0	0
T29	127244	127131	0	0
T30	111137	110911	0	0
T59	164173	164013	0	0
T60	150374	150217	0	0
T61	170845	170670	0	0
T122	191882	191649	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2866	2866	0	0
T28	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T102	1	1	0	0
T221	1	1	0	0
T222	1	1	0	0
T223	1	1	0	0
T224	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	478357528	56860	0	0
DepthKnown_A	478357528	478242073	0	0
RvalidKnown_A	478357528	478242073	0	0
WreadyKnown_A	478357528	478242073	0	0
gen_passthru_fifo.paramCheckPass	2866	2866	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478357528	56860	0	0
T7	164873	4	0	0
T17	141104	1	0	0
T18	218812	2	0	0
T19	221362	2	0	0
T20	503319	15	0	0
T28	72288	25	0	0
T29	127244	50	0	0
T35	602063	11	0	0
T86	478708	3	0	0
T122	191882	50	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478357528	478242073	0	0
T1	186530	186359	0	0
T2	150751	150587	0	0
T3	149602	149428	0	0
T28	72288	72179	0	0
T29	127244	127131	0	0
T30	111137	110911	0	0
T59	164173	164013	0	0
T60	150374	150217	0	0
T61	170845	170670	0	0
T122	191882	191649	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478357528	478242073	0	0
T1	186530	186359	0	0
T2	150751	150587	0	0
T3	149602	149428	0	0
T28	72288	72179	0	0
T29	127244	127131	0	0
T30	111137	110911	0	0
T59	164173	164013	0	0
T60	150374	150217	0	0
T61	170845	170670	0	0
T122	191882	191649	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478357528	478242073	0	0
T1	186530	186359	0	0
T2	150751	150587	0	0
T3	149602	149428	0	0
T28	72288	72179	0	0
T29	127244	127131	0	0
T30	111137	110911	0	0
T59	164173	164013	0	0
T60	150374	150217	0	0
T61	170845	170670	0	0
T122	191882	191649	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2866	2866	0	0
T28	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T102	1	1	0	0
T221	1	1	0	0
T222	1	1	0	0
T223	1	1	0	0
T224	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	478357528	59770	0	0
DepthKnown_A	478357528	478242073	0	0
RvalidKnown_A	478357528	478242073	0	0
WreadyKnown_A	478357528	478242073	0	0
gen_passthru_fifo.paramCheckPass	2866	2866	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478357528	59770	0	0
T7	164873	4	0	0
T17	141104	1	0	0
T18	218812	2	0	0
T19	221362	2	0	0
T20	503319	15	0	0
T28	72288	25	0	0
T29	127244	50	0	0
T35	602063	11	0	0
T86	478708	3	0	0
T122	191882	50	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478357528	478242073	0	0
T1	186530	186359	0	0
T2	150751	150587	0	0
T3	149602	149428	0	0
T28	72288	72179	0	0
T29	127244	127131	0	0
T30	111137	110911	0	0
T59	164173	164013	0	0
T60	150374	150217	0	0
T61	170845	170670	0	0
T122	191882	191649	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478357528	478242073	0	0
T1	186530	186359	0	0
T2	150751	150587	0	0
T3	149602	149428	0	0
T28	72288	72179	0	0
T29	127244	127131	0	0
T30	111137	110911	0	0
T59	164173	164013	0	0
T60	150374	150217	0	0
T61	170845	170670	0	0
T122	191882	191649	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478357528	478242073	0	0
T1	186530	186359	0	0
T2	150751	150587	0	0
T3	149602	149428	0	0
T28	72288	72179	0	0
T29	127244	127131	0	0
T30	111137	110911	0	0
T59	164173	164013	0	0
T60	150374	150217	0	0
T61	170845	170670	0	0
T122	191882	191649	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2866	2866	0	0
T28	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T53	1	1	0	0
T54	1	1	0	0
T102	1	1	0	0
T221	1	1	0	0
T222	1	1	0	0
T223	1	1	0	0
T224	1	1	0	0