Unified Coverage Report :: Module :: rv_core_ibex

Module : rv_core_ibex

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.69	96.47	89.29	98.77		100.00	78.95

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex	92.94	96.47	89.29	100.00		100.00	78.95

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.94	96.47	89.29	100.00		100.00	78.95

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.84	97.60	95.59	98.69		98.13	94.16

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.41	90.68		92.56			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
fifo_d	100.00	100.00	100.00			100.00	100.00
fifo_i	93.75	75.00	100.00			100.00	100.00
gen_alert_senders[0].u_alert_sender	100.00			100.00
gen_alert_senders[1].u_alert_sender	100.00			100.00
gen_alert_senders[2].u_alert_sender	100.00			100.00
gen_alert_senders[3].u_alert_sender	75.00			75.00
tl_adapter_host_d_ibex	92.37	97.67	81.82			90.00	100.00
tl_adapter_host_i_ibex	87.90	90.48	72.22			88.89	100.00
u_alert_nmi_sync	100.00	100.00				100.00
u_core	96.63			96.63
u_core_sleeping_buf	100.00	100.00
u_dbus_trans	97.29	100.00	96.30			100.00	92.86
u_edn_if	89.08	100.00	86.44			94.87	75.00
u_ibus_trans	96.36	100.00	92.59			100.00	92.86
u_intr_timer_sync	100.00	100.00				100.00
u_lc_sync	100.00	100.00				100.00	100.00
u_prim_buf_irq	100.00	100.00
u_prim_esc_receiver	100.00			100.00
u_prim_lc_sender	100.00	100.00				100.00
u_prim_sync_reqack_data	91.67	100.00	66.67			100.00	100.00
u_pwrmgr_sync	100.00	100.00				100.00	100.00
u_reg_cfg	99.28	98.69	98.84			99.58	100.00
u_sim_win_rsp	80.88	77.55	68.18			77.78	100.00
u_tlul_req_buf	100.00	100.00
u_tlul_rsp_buf	100.00	100.00
u_wdog_nmi_sync	100.00	100.00				100.00

Line Coverage for Module : rv_core_ibex

	Line No.	Total	Covered	Percent
TOTAL		85	82	96.47
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
ALWAYS	488	3	3	100.00
CONT_ASSIGN	508	1	1	100.00
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
ALWAYS	514	8	8	100.00
CONT_ASSIGN	699	1	1	100.00
CONT_ASSIGN	699	1	1	100.00
CONT_ASSIGN	700	1	1	100.00
CONT_ASSIGN	700	1	1	100.00
CONT_ASSIGN	701	1	1	100.00
CONT_ASSIGN	701	1	1	100.00
CONT_ASSIGN	705	1	1	100.00
CONT_ASSIGN	705	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	707	1	1	100.00
CONT_ASSIGN	707	1	1	100.00
CONT_ASSIGN	714	1	1	100.00
CONT_ASSIGN	715	1	1	100.00
CONT_ASSIGN	716	1	1	100.00
CONT_ASSIGN	719	1	1	100.00
CONT_ASSIGN	721	1	1	100.00
CONT_ASSIGN	723	1	1	100.00
CONT_ASSIGN	725	1	1	100.00
CONT_ASSIGN	732	1	1	100.00
CONT_ASSIGN	734	1	1	100.00
CONT_ASSIGN	736	1	1	100.00
CONT_ASSIGN	738	1	1	100.00
CONT_ASSIGN	748	1	1	100.00
CONT_ASSIGN	749	1	1	100.00
CONT_ASSIGN	750	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	754	1	1	100.00
CONT_ASSIGN	757	1	1	100.00
ALWAYS	789	11	11	100.00
ALWAYS	805	7	7	100.00
CONT_ASSIGN	816	1	1	100.00
CONT_ASSIGN	835	1	1	100.00
CONT_ASSIGN	836	1	1	100.00
CONT_ASSIGN	837	1	1	100.00
CONT_ASSIGN	840	1	0	0.00
CONT_ASSIGN	844	0	0
CONT_ASSIGN	883	1	1	100.00
ALWAYS	936	0	0
CONT_ASSIGN	977	1	0	0.00
CONT_ASSIGN	979	1	0	0.00
CONT_ASSIGN	981	1	1	100.00
CONT_ASSIGN	983	1	1	100.00
CONT_ASSIGN	985	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
202	1	1
203	1	1
216	1	1
217	1	1
218	1	1
225	1	1
263	1	1
265	1	1
268	1	1
342	1	1
348	1	1
363	1	1
488	1	1
489	1	1
491	1	1
508	1	1
509	1	1
510	1	1
511	1	1
514	1	1
515	1	1
516	1	1
517	1	1
518	1	1
519	1	1
520	1	1
521	1	1
			MISSING_ELSE
699	2	2
700	2	2
701	2	2
705	2	2
706	2	2
707	2	2
714	1	1
715	1	1
716	1	1
719	1	1
721	1	1
723	1	1
725	1	1
732	1	1
734	1	1
736	1	1
738	1	1
748	1	1
749	1	1
750	1	1
751	1	1
754	1	1
757	1	1
789	1	1
790	1	1
791	1	1
793	1	1
794	1	1
795	1	1
796	1	1
797	1	1
798	1	1
799	1	1
800	1	1
			MISSING_ELSE
805	1	1
806	1	1
807	1	1
808	1	1
810	1	1
811	1	1
812	1	1
816	1	1
835	1	1
836	1	1
837	1	1
840	0	1
844		unreachable
883	1	1
936		unreachable
937		unreachable
938		unreachable
939		unreachable
			==> MISSING_ELSE
977	0	1
979	0	1
981	1	1
983	1	1
985	1	1

---

Cond Coverage for Module : rv_core_ibex

	Total	Covered	Percent
Conditions	28	25	89.29
Logical	28	25	89.29
Non-Logical	0	0
Event	0	0

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T91,T74,T247
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T248,T249,T250
1	0	Covered	T77,T145,T44

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T77,T145,T44

 LINE       732
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T44,T22,T175
1	0	Covered	T17,T18,T19
1	1	Covered	T22,T8,T23

 LINE       734
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T22,T8,T23
1	0	Covered	T17,T18,T19
1	1	Covered	T44,T22,T175

 LINE       736
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T44,T22,T8
1	0	Covered	T17,T18,T19
1	1	Covered	T22,T23,T24

 LINE       738
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T44,T22,T175
1	0	Covered	T17,T18,T19
1	1	Covered	T22,T8,T23

 LINE       750
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T77,T145,T44
0	1	0	Covered	T91,T74,T247
1	0	0	Covered	T75,T251,T252

 LINE       797
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T19,T20
1	1	Covered	T17,T18,T19

---

Toggle Coverage for Module : rv_core_ibex

	Total	Covered	Percent
Totals	121	117	96.69
Total Bits	1624	1604	98.77
Total Bits 0->1	812	802	98.77
Total Bits 1->0	812	802	98.77

Ports	121	117	96.69
Port Bits	1624	1604	98.77
Port Bits 0->1	812	802	98.77
Port Bits 1->0	812	802	98.77

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
rst_ni	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
clk_edn_i	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
rst_edn_ni	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
clk_esc_i	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
rst_esc_ni	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
rst_cpu_n_o	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_o.d_ready	Yes	Yes	T32,T54,T221	Yes	T31,T32,T53	OUTPUT
corei_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	OUTPUT
corei_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T53,T54,T223	Yes	T53,T54,T223	OUTPUT
corei_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_data[31:0]	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	OUTPUT
corei_tl_h_o.a_mask[3:0]	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	OUTPUT
corei_tl_h_o.a_address[31:0]	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	OUTPUT
corei_tl_h_o.a_source[5:0]	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	OUTPUT
corei_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_size[1:0]	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	OUTPUT
corei_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_opcode[2:0]	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	OUTPUT
corei_tl_h_o.a_valid	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	OUTPUT
corei_tl_h_i.a_ready	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	INPUT
corei_tl_h_i.d_error	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	INPUT
corei_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	INPUT
corei_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	INPUT
corei_tl_h_i.d_data[31:0]	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	INPUT
corei_tl_h_i.d_sink	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	INPUT
corei_tl_h_i.d_source[5:0]	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	INPUT
corei_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_size[1:0]	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	INPUT
corei_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_opcode[0]	Yes	Yes	*T31,*T32,*T53	Yes	T31,T32,T53	INPUT
corei_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_valid	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	INPUT
cored_tl_h_o.d_ready	Yes	Yes	T32,T28,T54	Yes	T31,T32,T28	OUTPUT
cored_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	OUTPUT
cored_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T32,T28,T53	Yes	T32,T28,T53	OUTPUT
cored_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_data[31:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	OUTPUT
cored_tl_h_o.a_mask[3:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	OUTPUT
cored_tl_h_o.a_address[31:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	OUTPUT
cored_tl_h_o.a_source[5:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	OUTPUT
cored_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_size[1:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	OUTPUT
cored_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_opcode[2:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	OUTPUT
cored_tl_h_o.a_valid	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	OUTPUT
cored_tl_h_i.a_ready	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	INPUT
cored_tl_h_i.d_error	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	INPUT
cored_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	INPUT
cored_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	INPUT
cored_tl_h_i.d_data[31:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	INPUT
cored_tl_h_i.d_sink	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	INPUT
cored_tl_h_i.d_source[5:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	INPUT
cored_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_size[1:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	INPUT
cored_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_opcode[0]	Yes	Yes	*T31,*T32,*T28	Yes	T31,T32,T28	INPUT
cored_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_valid	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	INPUT
irq_software_i	Yes	Yes	T28,T253,T110	Yes	T28,T253,T110	INPUT
irq_timer_i	Yes	Yes	T28,T254,T255	Yes	T28,T254,T255	INPUT
irq_external_i	Yes	Yes	T17,T20,T21	Yes	T17,T20,T21	INPUT
esc_tx_i.esc_n	Yes	Yes	T20,T38,T131	Yes	T20,T38,T131	INPUT
esc_tx_i.esc_p	Yes	Yes	T20,T38,T131	Yes	T20,T38,T131	INPUT
esc_rx_o.resp_n	Yes	Yes	T20,T38,T131	Yes	T20,T38,T131	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T20,T38,T131	Yes	T20,T38,T131	OUTPUT
nmi_wdog_i	Yes	Yes	T28,T20,T256	Yes	T28,T20,T256	INPUT
debug_req_i	Yes	Yes	T257,T258,T259	Yes	T257,T258,T259	INPUT
crash_dump_o.current.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_valid	Unreachable	Unreachable		Unreachable		OUTPUT
lc_cpu_en_i[3:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
pwrmgr_cpu_en_i[3:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
pwrmgr_o.core_sleeping	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.d_ready	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	INPUT
cfg_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	INPUT
cfg_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	INPUT
cfg_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	INPUT
cfg_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_data[31:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	INPUT
cfg_tl_d_i.a_mask[3:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	INPUT
cfg_tl_d_i.a_address[7:0]	Yes	Yes	T31,T32,*T28	Yes	T31,T32,T28	INPUT
cfg_tl_d_i.a_address[15:8]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[20:16]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	INPUT
cfg_tl_d_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[24]	Yes	Yes	*T31,*T32,*T28	Yes	T31,T32,T28	INPUT
cfg_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[30]	Yes	Yes	*T31,*T32,*T28	Yes	T31,T32,T28	INPUT
cfg_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_source[5:0]	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	INPUT
cfg_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_size[1:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	INPUT
cfg_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_opcode[2:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	INPUT
cfg_tl_d_i.a_valid	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	INPUT
cfg_tl_d_o.a_ready	Yes	Yes	T32,T28,T54	Yes	T31,T32,T28	OUTPUT
cfg_tl_d_o.d_error	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	OUTPUT
cfg_tl_d_o.d_data[31:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	OUTPUT
cfg_tl_d_o.d_sink	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	OUTPUT
cfg_tl_d_o.d_source[5:0]	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	OUTPUT
cfg_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_size[1:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	OUTPUT
cfg_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_opcode[0]	Yes	Yes	*T31,*T32,*T28	Yes	T31,T32,T28	OUTPUT
cfg_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_valid	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	OUTPUT
edn_o.edn_req	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T17,T18,T20	Yes	T17,T18,T20	INPUT
edn_i.edn_fips	Yes	Yes	T260,T261,T262	Yes	T89,T263,T264	INPUT
edn_i.edn_ack	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
clk_otp_i	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
rst_otp_ni	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
icache_otp_key_o.req	Yes	Yes	T225,T226,T229	Yes	T225,T226,T229	OUTPUT
icache_otp_key_i.seed_valid	Yes	Yes	T18,T19,T20	Yes	T17,T18,T19	INPUT
icache_otp_key_i.nonce[127:0]	Yes	Yes	T17,T18,T7	Yes	T17,T18,T7	INPUT
icache_otp_key_i.key[127:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
icache_otp_key_i.ack	Yes	Yes	T225,T226,T229	Yes	T225,T226,T229	INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T28,T56,T22	Yes	T28,T56,T22	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T56,T57,T58	Yes	T56,T57,T140	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T56,T57,T140	Yes	T56,T57,T58	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T28,T44,T56	Yes	T28,T44,T56	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T56,T138,T57	Yes	T56,T138,T57	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T56,T138,T57	Yes	T56,T138,T57	INPUT
alert_rx_i[2].ack_n	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T28,T91,T74	Yes	T28,T91,T74	INPUT
alert_rx_i[2].ping_n	Yes	Yes	T56,T57,T58	Yes	T56,T57,T58	INPUT
alert_rx_i[2].ping_p	Yes	Yes	T56,T57,T58	Yes	T56,T57,T58	INPUT
alert_rx_i[3].ack_n	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T28,T56,T138	Yes	T28,T56,T138	INPUT
alert_rx_i[3].ping_n	Yes	Yes	T56,T138,T57	Yes	T56,T138,T57	INPUT
alert_rx_i[3].ping_p	Yes	Yes	T56,T138,T57	Yes	T56,T138,T57	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T28,T56,T22	Yes	T28,T56,T22	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T28,T44,T56	Yes	T28,T44,T56	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T28,T91,T74	Yes	T28,T91,T74	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T28,T56,T138	Yes	T28,T56,T138	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rv_core_ibex

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	348	2	2	100.00
IF	488	2	2	100.00
IF	514	3	3	100.00
IF	793	3	3	100.00
IF	805	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	348	(fatal_core_err) ? 

Branches:

-1-	Status	Tests
1	Covered	T77,T145,T44
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	488	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	514	if ((!rst_ni))
-2-:	518	if (double_fault)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T248,T249,T250
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	793	if (reg2hw.rnd_data.re)
-2-:	797	if ((edn_req && edn_ack))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T20,T7,T35
0	1	Covered	T17,T18,T19
0	0	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	805	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rv_core_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	15	78.95
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	15	78.95

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmIbexFetchEnable0_A	398552666	6	0	0
FpvSecCmIbexFetchEnable1_A	398552666	22944851	0	74
FpvSecCmIbexFetchEnable2_A	398552666	61252951	0	80
FpvSecCmIbexFetchEnable3Rev_A	398552666	332851766	0	1890
FpvSecCmIbexFetchEnable3_A	398552666	332853495	0	1803
FpvSecCmIbexInstrIntgErrCheck_A	398552666	152	0	0
FpvSecCmIbexLoadRespIntgErrCheck_A	398552666	588	0	0
FpvSecCmIbexPcMismatchCheck_A	398552666	0	0	0
FpvSecCmIbexRfEccErrCheck_A	398552666	0	0	0
FpvSecCmIbexStoreRespIntgErrCheck_A	398552666	0	0	0
FpvSecCmRegWeOnehotCheck_A	398552666	7	0	0
FpvSecCmRvCoreRegWeOnehotCheck_A	398552666	0	0	0
g_instr_intg_err_assert_signals.AssertConnected_A	956	956	0	0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A	956	956	0	0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A	956	956	0	0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A	956	956	0	0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A	956	956	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A	398552666	159	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A	398552666	200	0	0

FpvSecCmIbexFetchEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	6	0	0
T82	148232	0	0	0
T160	406640	0	0	0
T206	339998	0	0	0
T214	229968	0	0	0
T248	208385	1	0	0
T249	0	1	0	0
T250	0	1	0	0
T265	0	1	0	0
T266	0	1	0	0
T267	0	1	0	0
T268	104440	0	0	0
T269	140846	0	0	0
T270	72661	0	0	0
T271	268178	0	0	0
T272	287554	0	0	0

FpvSecCmIbexFetchEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	22944851	0	74
T1	186530	19312	0	2
T2	150751	19421	0	2
T3	149602	19363	0	2
T59	164173	19362	0	2
T60	150374	19454	0	2
T61	170845	19311	0	2
T62	173049	19377	0	2
T63	200999	19324	0	2
T64	172317	19328	0	2
T65	141742	19325	0	2

FpvSecCmIbexFetchEnable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	61252951	0	80
T1	186530	69676	0	2
T2	150751	69781	0	2
T3	149602	69719	0	2
T59	164173	69730	0	2
T60	150374	69826	0	2
T61	170845	69675	0	2
T62	173049	69749	0	2
T63	200999	69692	0	2
T64	172317	69680	0	2
T65	141742	69677	0	2

FpvSecCmIbexFetchEnable3Rev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	332851766	0	1890
T1	186530	116675	0	2
T2	150751	80798	0	2
T3	149602	79701	0	2
T59	164173	94275	0	2
T60	150374	80384	0	2
T61	170845	100987	0	2
T62	173049	103124	0	2
T63	200999	131131	0	2
T64	172317	102454	0	2
T65	141742	71882	0	2

FpvSecCmIbexFetchEnable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	332853495	0	1803
T1	186530	116677	0	0
T2	150751	80800	0	0
T3	149602	79703	0	0
T7	0	0	0	2
T17	0	0	0	2
T19	0	0	0	2
T20	0	0	0	2
T21	0	0	0	2
T35	0	0	0	2
T45	0	0	0	2
T59	164173	94277	0	0
T60	150374	80385	0	0
T61	170845	100989	0	0
T62	173049	103126	0	0
T63	200999	131133	0	0
T64	172317	102456	0	0
T65	141742	71884	0	0
T77	0	0	0	2
T79	0	0	0	2
T86	0	0	0	2

FpvSecCmIbexInstrIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	152	0	0
T104	145144	0	0	0
T262	728234	0	0	0
T273	287934	76	0	0
T274	0	76	0	0
T275	264213	0	0	0
T276	130202	0	0	0
T277	161065	0	0	0
T278	266283	0	0	0
T279	806026	0	0	0
T280	126918	0	0	0
T281	68593	0	0	0

FpvSecCmIbexLoadRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	588	0	0
T39	220360	0	0	0
T55	153740	0	0	0
T70	479188	0	0	0
T71	376850	0	0	0
T72	152011	0	0	0
T73	338607	0	0	0
T74	0	32	0	0
T91	164553	32	0	0
T92	148778	0	0	0
T131	129839	0	0	0
T247	0	99	0	0
T282	0	32	0	0
T283	0	1	0	0
T284	0	32	0	0
T285	0	32	0	0
T286	0	1	0	0
T287	0	32	0	0
T288	0	100	0	0
T289	669424	0	0	0

FpvSecCmIbexPcMismatchCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	0	0	0

FpvSecCmIbexRfEccErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	0	0	0

FpvSecCmIbexStoreRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	7	0	0
T44	223571	0	0	0
T75	258621	1	0	0
T76	63344	0	0	0
T117	256058	0	0	0
T146	164597	0	0	0
T251	159462	1	0	0
T252	0	1	0	0
T290	0	1	0	0
T291	0	1	0	0
T292	0	1	0	0
T293	0	1	0	0
T294	153980	0	0	0
T295	634888	0	0	0
T296	74500	0	0	0
T297	143768	0	0	0

FpvSecCmRvCoreRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	0	0	0

g_instr_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	159	0	0
T101	151067	0	0	0
T110	178635	0	0	0
T132	287116	0	0	0
T162	357914	0	0	0
T211	272759	0	0	0
T225	87844	29	0	0
T226	0	41	0	0
T227	226551	0	0	0
T228	150954	0	0	0
T229	0	38	0	0
T230	0	18	0	0
T231	0	16	0	0
T232	0	17	0	0
T233	125966	0	0	0
T234	94274	0	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	200	0	0
T101	151067	0	0	0
T110	178635	0	0	0
T132	287116	0	0	0
T156	0	16	0	0
T162	357914	0	0	0
T211	272759	0	0	0
T225	87844	7	0	0
T226	0	10	0	0
T227	226551	0	0	0
T228	150954	0	0	0
T229	0	9	0	0
T230	0	42	0	0
T231	0	42	0	0
T232	0	42	0	0
T233	125966	0	0	0
T234	94274	0	0	0
T298	0	16	0	0
T299	0	16	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Line No.	Total	Covered	Percent
TOTAL		85	82	96.47
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
ALWAYS	488	3	3	100.00
CONT_ASSIGN	508	1	1	100.00
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
ALWAYS	514	8	8	100.00
CONT_ASSIGN	699	1	1	100.00
CONT_ASSIGN	699	1	1	100.00
CONT_ASSIGN	700	1	1	100.00
CONT_ASSIGN	700	1	1	100.00
CONT_ASSIGN	701	1	1	100.00
CONT_ASSIGN	701	1	1	100.00
CONT_ASSIGN	705	1	1	100.00
CONT_ASSIGN	705	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	707	1	1	100.00
CONT_ASSIGN	707	1	1	100.00
CONT_ASSIGN	714	1	1	100.00
CONT_ASSIGN	715	1	1	100.00
CONT_ASSIGN	716	1	1	100.00
CONT_ASSIGN	719	1	1	100.00
CONT_ASSIGN	721	1	1	100.00
CONT_ASSIGN	723	1	1	100.00
CONT_ASSIGN	725	1	1	100.00
CONT_ASSIGN	732	1	1	100.00
CONT_ASSIGN	734	1	1	100.00
CONT_ASSIGN	736	1	1	100.00
CONT_ASSIGN	738	1	1	100.00
CONT_ASSIGN	748	1	1	100.00
CONT_ASSIGN	749	1	1	100.00
CONT_ASSIGN	750	1	1	100.00
CONT_ASSIGN	751	1	1	100.00
CONT_ASSIGN	754	1	1	100.00
CONT_ASSIGN	757	1	1	100.00
ALWAYS	789	11	11	100.00
ALWAYS	805	7	7	100.00
CONT_ASSIGN	816	1	1	100.00
CONT_ASSIGN	835	1	1	100.00
CONT_ASSIGN	836	1	1	100.00
CONT_ASSIGN	837	1	1	100.00
CONT_ASSIGN	840	1	0	0.00
CONT_ASSIGN	844	0	0
CONT_ASSIGN	883	1	1	100.00
ALWAYS	936	0	0
CONT_ASSIGN	977	1	0	0.00
CONT_ASSIGN	979	1	0	0.00
CONT_ASSIGN	981	1	1	100.00
CONT_ASSIGN	983	1	1	100.00
CONT_ASSIGN	985	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
202	1	1
203	1	1
216	1	1
217	1	1
218	1	1
225	1	1
263	1	1
265	1	1
268	1	1
342	1	1
348	1	1
363	1	1
488	1	1
489	1	1
491	1	1
508	1	1
509	1	1
510	1	1
511	1	1
514	1	1
515	1	1
516	1	1
517	1	1
518	1	1
519	1	1
520	1	1
521	1	1
			MISSING_ELSE
699	2	2
700	2	2
701	2	2
705	2	2
706	2	2
707	2	2
714	1	1
715	1	1
716	1	1
719	1	1
721	1	1
723	1	1
725	1	1
732	1	1
734	1	1
736	1	1
738	1	1
748	1	1
749	1	1
750	1	1
751	1	1
754	1	1
757	1	1
789	1	1
790	1	1
791	1	1
793	1	1
794	1	1
795	1	1
796	1	1
797	1	1
798	1	1
799	1	1
800	1	1
			MISSING_ELSE
805	1	1
806	1	1
807	1	1
808	1	1
810	1	1
811	1	1
812	1	1
816	1	1
835	1	1
836	1	1
837	1	1
840	0	1
844		unreachable
883	1	1
936		unreachable
937		unreachable
938		unreachable
939		unreachable
			==> MISSING_ELSE
977	0	1
979	0	1
981	1	1
983	1	1
985	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Covered	Percent
Conditions	28	25	89.29
Logical	28	25	89.29
Non-Logical	0	0
Event	0	0

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T91,T74,T247
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T248,T249,T250
1	0	Covered	T77,T145,T44

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T77,T145,T44

 LINE       732
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T44,T22,T175
1	0	Covered	T17,T18,T19
1	1	Covered	T22,T8,T23

 LINE       734
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T22,T8,T23
1	0	Covered	T17,T18,T19
1	1	Covered	T44,T22,T175

 LINE       736
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T44,T22,T8
1	0	Covered	T17,T18,T19
1	1	Covered	T22,T23,T24

 LINE       738
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T44,T22,T175
1	0	Covered	T17,T18,T19
1	1	Covered	T22,T8,T23

 LINE       750
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T77,T145,T44
0	1	0	Covered	T91,T74,T247
1	0	0	Covered	T75,T251,T252

 LINE       797
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T18,T19,T20
1	1	Covered	T17,T18,T19

---

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Covered	Percent
Totals	117	117	100.00
Total Bits	1604	1604	100.00
Total Bits 0->1	802	802	100.00
Total Bits 1->0	802	802	100.00

Ports	117	117	100.00
Port Bits	1604	1604	100.00
Port Bits 0->1	802	802	100.00
Port Bits 1->0	802	802	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
rst_ni	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
clk_edn_i	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
rst_edn_ni	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
clk_esc_i	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
rst_esc_ni	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
rst_cpu_n_o	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_o.d_ready	Yes	Yes	T32,T54,T221	Yes	T31,T32,T53	OUTPUT
corei_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	OUTPUT
corei_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T53,T54,T223	Yes	T53,T54,T223	OUTPUT
corei_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_data[31:0]	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	OUTPUT
corei_tl_h_o.a_mask[3:0]	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	OUTPUT
corei_tl_h_o.a_address[31:0]	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	OUTPUT
corei_tl_h_o.a_source[5:0]	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	OUTPUT
corei_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_size[1:0]	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	OUTPUT
corei_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_opcode[2:0]	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	OUTPUT
corei_tl_h_o.a_valid	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	OUTPUT
corei_tl_h_i.a_ready	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	INPUT
corei_tl_h_i.d_error	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	INPUT
corei_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	INPUT
corei_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	INPUT
corei_tl_h_i.d_data[31:0]	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	INPUT
corei_tl_h_i.d_sink	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	INPUT
corei_tl_h_i.d_source[5:0]	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	INPUT
corei_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_size[1:0]	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	INPUT
corei_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_opcode[0]	Yes	Yes	*T31,*T32,*T53	Yes	T31,T32,T53	INPUT
corei_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_valid	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	INPUT
cored_tl_h_o.d_ready	Yes	Yes	T32,T28,T54	Yes	T31,T32,T28	OUTPUT
cored_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	OUTPUT
cored_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T32,T28,T53	Yes	T32,T28,T53	OUTPUT
cored_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_data[31:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	OUTPUT
cored_tl_h_o.a_mask[3:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	OUTPUT
cored_tl_h_o.a_address[31:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	OUTPUT
cored_tl_h_o.a_source[5:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	OUTPUT
cored_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_size[1:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	OUTPUT
cored_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_opcode[2:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	OUTPUT
cored_tl_h_o.a_valid	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	OUTPUT
cored_tl_h_i.a_ready	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	INPUT
cored_tl_h_i.d_error	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	INPUT
cored_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	INPUT
cored_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	INPUT
cored_tl_h_i.d_data[31:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	INPUT
cored_tl_h_i.d_sink	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	INPUT
cored_tl_h_i.d_source[5:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	INPUT
cored_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_size[1:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	INPUT
cored_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_opcode[0]	Yes	Yes	*T31,*T32,*T28	Yes	T31,T32,T28	INPUT
cored_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_valid	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	INPUT
irq_software_i	Yes	Yes	T28,T253,T110	Yes	T28,T253,T110	INPUT
irq_timer_i	Yes	Yes	T28,T254,T255	Yes	T28,T254,T255	INPUT
irq_external_i	Yes	Yes	T17,T20,T21	Yes	T17,T20,T21	INPUT
esc_tx_i.esc_n	Yes	Yes	T20,T38,T131	Yes	T20,T38,T131	INPUT
esc_tx_i.esc_p	Yes	Yes	T20,T38,T131	Yes	T20,T38,T131	INPUT
esc_rx_o.resp_n	Yes	Yes	T20,T38,T131	Yes	T20,T38,T131	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T20,T38,T131	Yes	T20,T38,T131	OUTPUT
nmi_wdog_i	Yes	Yes	T28,T20,T256	Yes	T28,T20,T256	INPUT
debug_req_i	Yes	Yes	T257,T258,T259	Yes	T257,T258,T259	INPUT
crash_dump_o.current.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_valid	Unreachable	Unreachable		Unreachable		OUTPUT
lc_cpu_en_i[3:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
pwrmgr_cpu_en_i[3:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
pwrmgr_o.core_sleeping	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.d_ready	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	INPUT
cfg_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	INPUT
cfg_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	INPUT
cfg_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	INPUT
cfg_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_data[31:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	INPUT
cfg_tl_d_i.a_mask[3:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	INPUT
cfg_tl_d_i.a_address[7:0]	Yes	Yes	T31,T32,*T28	Yes	T31,T32,T28	INPUT
cfg_tl_d_i.a_address[15:8]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[20:16]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	INPUT
cfg_tl_d_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[24]	Yes	Yes	*T31,*T32,*T28	Yes	T31,T32,T28	INPUT
cfg_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[30]	Yes	Yes	*T31,*T32,*T28	Yes	T31,T32,T28	INPUT
cfg_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_source[5:0]	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	INPUT
cfg_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_size[1:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	INPUT
cfg_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_opcode[2:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	INPUT
cfg_tl_d_i.a_valid	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	INPUT
cfg_tl_d_o.a_ready	Yes	Yes	T32,T28,T54	Yes	T31,T32,T28	OUTPUT
cfg_tl_d_o.d_error	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	OUTPUT
cfg_tl_d_o.d_data[31:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	OUTPUT
cfg_tl_d_o.d_sink	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	OUTPUT
cfg_tl_d_o.d_source[5:0]	Yes	Yes	T31,T32,T53	Yes	T31,T32,T53	OUTPUT
cfg_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_size[1:0]	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	OUTPUT
cfg_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_opcode[0]	Yes	Yes	*T31,*T32,*T28	Yes	T31,T32,T28	OUTPUT
cfg_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_valid	Yes	Yes	T31,T32,T28	Yes	T31,T32,T28	OUTPUT
edn_o.edn_req	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T17,T18,T20	Yes	T17,T18,T20	INPUT
edn_i.edn_fips	Yes	Yes	T260,T261,T262	Yes	T89,T263,T264	INPUT
edn_i.edn_ack	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
clk_otp_i	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
rst_otp_ni	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
icache_otp_key_o.req	Yes	Yes	T225,T226,T229	Yes	T225,T226,T229	OUTPUT
icache_otp_key_i.seed_valid	Yes	Yes	T18,T19,T20	Yes	T17,T18,T19	INPUT
icache_otp_key_i.nonce[127:0]	Yes	Yes	T17,T18,T7	Yes	T17,T18,T7	INPUT
icache_otp_key_i.key[127:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
icache_otp_key_i.ack	Yes	Yes	T225,T226,T229	Yes	T225,T226,T229	INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T28,T56,T22	Yes	T28,T56,T22	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T56,T57,T58	Yes	T56,T57,T140	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T56,T57,T140	Yes	T56,T57,T58	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T28,T44,T56	Yes	T28,T44,T56	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T56,T138,T57	Yes	T56,T138,T57	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T56,T138,T57	Yes	T56,T138,T57	INPUT
alert_rx_i[2].ack_n	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T28,T91,T74	Yes	T28,T91,T74	INPUT
alert_rx_i[2].ping_n	Yes	Yes	T56,T57,T58	Yes	T56,T57,T58	INPUT
alert_rx_i[2].ping_p	Yes	Yes	T56,T57,T58	Yes	T56,T57,T58	INPUT
alert_rx_i[3].ack_n	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T28,T56,T138	Yes	T28,T56,T138	INPUT
alert_rx_i[3].ping_n	Yes	Yes	T56,T138,T57	Yes	T56,T138,T57	INPUT
alert_rx_i[3].ping_p	Yes	Yes	T56,T138,T57	Yes	T56,T138,T57	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T28,T56,T22	Yes	T28,T56,T22	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T28,T44,T56	Yes	T28,T44,T56	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T28,T91,T74	Yes	T28,T91,T74	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T28,T56,T138	Yes	T28,T56,T138	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	348	2	2	100.00
IF	488	2	2	100.00
IF	514	3	3	100.00
IF	793	3	3	100.00
IF	805	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	348	(fatal_core_err) ? 

Branches:

-1-	Status	Tests
1	Covered	T77,T145,T44
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	488	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	514	if ((!rst_ni))
-2-:	518	if (double_fault)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T248,T249,T250
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	793	if (reg2hw.rnd_data.re)
-2-:	797	if ((edn_req && edn_ack))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T20,T7,T35
0	1	Covered	T17,T18,T19
0	0	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	805	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	15	78.95
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	15	78.95

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmIbexFetchEnable0_A	398552666	6	0	0
FpvSecCmIbexFetchEnable1_A	398552666	22944851	0	74
FpvSecCmIbexFetchEnable2_A	398552666	61252951	0	80
FpvSecCmIbexFetchEnable3Rev_A	398552666	332851766	0	1890
FpvSecCmIbexFetchEnable3_A	398552666	332853495	0	1803
FpvSecCmIbexInstrIntgErrCheck_A	398552666	152	0	0
FpvSecCmIbexLoadRespIntgErrCheck_A	398552666	588	0	0
FpvSecCmIbexPcMismatchCheck_A	398552666	0	0	0
FpvSecCmIbexRfEccErrCheck_A	398552666	0	0	0
FpvSecCmIbexStoreRespIntgErrCheck_A	398552666	0	0	0
FpvSecCmRegWeOnehotCheck_A	398552666	7	0	0
FpvSecCmRvCoreRegWeOnehotCheck_A	398552666	0	0	0
g_instr_intg_err_assert_signals.AssertConnected_A	956	956	0	0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A	956	956	0	0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A	956	956	0	0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A	956	956	0	0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A	956	956	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A	398552666	159	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A	398552666	200	0	0

FpvSecCmIbexFetchEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	6	0	0
T82	148232	0	0	0
T160	406640	0	0	0
T206	339998	0	0	0
T214	229968	0	0	0
T248	208385	1	0	0
T249	0	1	0	0
T250	0	1	0	0
T265	0	1	0	0
T266	0	1	0	0
T267	0	1	0	0
T268	104440	0	0	0
T269	140846	0	0	0
T270	72661	0	0	0
T271	268178	0	0	0
T272	287554	0	0	0

FpvSecCmIbexFetchEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	22944851	0	74
T1	186530	19312	0	2
T2	150751	19421	0	2
T3	149602	19363	0	2
T59	164173	19362	0	2
T60	150374	19454	0	2
T61	170845	19311	0	2
T62	173049	19377	0	2
T63	200999	19324	0	2
T64	172317	19328	0	2
T65	141742	19325	0	2

FpvSecCmIbexFetchEnable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	61252951	0	80
T1	186530	69676	0	2
T2	150751	69781	0	2
T3	149602	69719	0	2
T59	164173	69730	0	2
T60	150374	69826	0	2
T61	170845	69675	0	2
T62	173049	69749	0	2
T63	200999	69692	0	2
T64	172317	69680	0	2
T65	141742	69677	0	2

FpvSecCmIbexFetchEnable3Rev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	332851766	0	1890
T1	186530	116675	0	2
T2	150751	80798	0	2
T3	149602	79701	0	2
T59	164173	94275	0	2
T60	150374	80384	0	2
T61	170845	100987	0	2
T62	173049	103124	0	2
T63	200999	131131	0	2
T64	172317	102454	0	2
T65	141742	71882	0	2

FpvSecCmIbexFetchEnable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	332853495	0	1803
T1	186530	116677	0	0
T2	150751	80800	0	0
T3	149602	79703	0	0
T7	0	0	0	2
T17	0	0	0	2
T19	0	0	0	2
T20	0	0	0	2
T21	0	0	0	2
T35	0	0	0	2
T45	0	0	0	2
T59	164173	94277	0	0
T60	150374	80385	0	0
T61	170845	100989	0	0
T62	173049	103126	0	0
T63	200999	131133	0	0
T64	172317	102456	0	0
T65	141742	71884	0	0
T77	0	0	0	2
T79	0	0	0	2
T86	0	0	0	2

FpvSecCmIbexInstrIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	152	0	0
T104	145144	0	0	0
T262	728234	0	0	0
T273	287934	76	0	0
T274	0	76	0	0
T275	264213	0	0	0
T276	130202	0	0	0
T277	161065	0	0	0
T278	266283	0	0	0
T279	806026	0	0	0
T280	126918	0	0	0
T281	68593	0	0	0

FpvSecCmIbexLoadRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	588	0	0
T39	220360	0	0	0
T55	153740	0	0	0
T70	479188	0	0	0
T71	376850	0	0	0
T72	152011	0	0	0
T73	338607	0	0	0
T74	0	32	0	0
T91	164553	32	0	0
T92	148778	0	0	0
T131	129839	0	0	0
T247	0	99	0	0
T282	0	32	0	0
T283	0	1	0	0
T284	0	32	0	0
T285	0	32	0	0
T286	0	1	0	0
T287	0	32	0	0
T288	0	100	0	0
T289	669424	0	0	0

FpvSecCmIbexPcMismatchCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	0	0	0

FpvSecCmIbexRfEccErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	0	0	0

FpvSecCmIbexStoreRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	7	0	0
T44	223571	0	0	0
T75	258621	1	0	0
T76	63344	0	0	0
T117	256058	0	0	0
T146	164597	0	0	0
T251	159462	1	0	0
T252	0	1	0	0
T290	0	1	0	0
T291	0	1	0	0
T292	0	1	0	0
T293	0	1	0	0
T294	153980	0	0	0
T295	634888	0	0	0
T296	74500	0	0	0
T297	143768	0	0	0

FpvSecCmRvCoreRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	0	0	0

g_instr_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	159	0	0
T101	151067	0	0	0
T110	178635	0	0	0
T132	287116	0	0	0
T162	357914	0	0	0
T211	272759	0	0	0
T225	87844	29	0	0
T226	0	41	0	0
T227	226551	0	0	0
T228	150954	0	0	0
T229	0	38	0	0
T230	0	18	0	0
T231	0	16	0	0
T232	0	17	0	0
T233	125966	0	0	0
T234	94274	0	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	200	0	0
T101	151067	0	0	0
T110	178635	0	0	0
T132	287116	0	0	0
T156	0	16	0	0
T162	357914	0	0	0
T211	272759	0	0	0
T225	87844	7	0	0
T226	0	10	0	0
T227	226551	0	0	0
T228	150954	0	0	0
T229	0	9	0	0
T230	0	42	0	0
T231	0	42	0	0
T232	0	42	0	0
T233	125966	0	0	0
T234	94274	0	0	0
T298	0	16	0	0
T299	0	16	0	0