Unified Coverage Report :: Module :: prim_sync_reqack_data

Module : prim_sync_reqack_data

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data	100.00	100.00					100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.94	96.47	89.29	100.00		100.00	78.95	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	91.67	100.00	66.67			100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	84.62			100.00	100.00	u_edn_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	91.67	100.00	66.67			100.00	100.00

Line Coverage for Module : prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Module : prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	797105332	3775	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	797105332	3775	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	797105332	3775	0	0
T7	164873	3	0	0
T17	141104	1	0	0
T18	218812	2	0	0
T19	221362	2	0	0
T20	503319	10	0	0
T35	602063	11	0	0
T45	186945	1	0	0
T77	505796	5	0	0
T78	148944	2	0	0
T86	478708	3	0	0
T101	151067	0	0	0
T110	178635	0	0	0
T132	287116	0	0	0
T162	357914	0	0	0
T211	272759	0	0	0
T225	87844	7	0	0
T226	0	10	0	0
T227	226551	0	0	0
T228	150954	0	0	0
T229	0	9	0	0
T230	0	4	0	0
T231	0	4	0	0
T232	0	4	0	0
T233	125966	0	0	0
T234	94274	0	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	797105332	3775	0	0
T7	164873	3	0	0
T17	141104	1	0	0
T18	218812	2	0	0
T19	221362	2	0	0
T20	503319	10	0	0
T35	602063	11	0	0
T45	186945	1	0	0
T77	505796	5	0	0
T78	148944	2	0	0
T86	478708	3	0	0
T101	151067	0	0	0
T110	178635	0	0	0
T132	287116	0	0	0
T162	357914	0	0	0
T211	272759	0	0	0
T225	87844	7	0	0
T226	0	10	0	0
T227	226551	0	0	0
T228	150954	0	0	0
T229	0	9	0	0
T230	0	4	0	0
T231	0	4	0	0
T232	0	4	0	0
T233	125966	0	0	0
T234	94274	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	398552666	38	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	398552666	38	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	38	0	0
T101	151067	0	0	0
T110	178635	0	0	0
T132	287116	0	0	0
T162	357914	0	0	0
T211	272759	0	0	0
T225	87844	7	0	0
T226	0	10	0	0
T227	226551	0	0	0
T228	150954	0	0	0
T229	0	9	0	0
T230	0	4	0	0
T231	0	4	0	0
T232	0	4	0	0
T233	125966	0	0	0
T234	94274	0	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	38	0	0
T101	151067	0	0	0
T110	178635	0	0	0
T132	287116	0	0	0
T162	357914	0	0	0
T211	272759	0	0	0
T225	87844	7	0	0
T226	0	10	0	0
T227	226551	0	0	0
T228	150954	0	0	0
T229	0	9	0	0
T230	0	4	0	0
T231	0	4	0	0
T232	0	4	0	0
T233	125966	0	0	0
T234	94274	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	398552666	3737	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	398552666	3737	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	3737	0	0
T7	164873	3	0	0
T17	141104	1	0	0
T18	218812	2	0	0
T19	221362	2	0	0
T20	503319	10	0	0
T35	602063	11	0	0
T45	186945	1	0	0
T77	505796	5	0	0
T78	148944	2	0	0
T86	478708	3	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	398552666	3737	0	0
T7	164873	3	0	0
T17	141104	1	0	0
T18	218812	2	0	0
T19	221362	2	0	0
T20	503319	10	0	0
T35	602063	11	0	0
T45	186945	1	0	0
T77	505796	5	0	0
T78	148944	2	0	0
T86	478708	3	0	0