Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_pwm_aon.u_reg.u_cfg_cdc

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.71	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.71	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.71	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.71	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.71	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.71	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.71	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.71	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.71	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.71	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.71	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.71	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.71	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.71	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.71	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.71	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T28
0	1	Unreachable
1	0	Covered	T28,T340,T352

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T28,T8,T10
1	-	Covered	T12,T14,T15

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T29,T30
0	1	Unreachable
1	0	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T29,T30
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119920069	96023	0	0
DstReqKnown_A	1533793	1327044	0	0
SrcAckBusyChk_A	119920069	244	0	0
SrcBusyKnown_A	119920069	119138494	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	96023	0	0
T8	439239	465	0	0
T10	0	269	0	0
T12	0	754	0	0
T14	0	768	0	0
T15	0	784	0	0
T112	0	266	0	0
T113	0	4728	0	0
T252	38535	0	0	0
T300	0	829	0	0
T302	0	728	0	0
T319	58877	0	0	0
T342	0	306	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1533793	1327044	0	0
T1	452	229	0	0
T2	309	84	0	0
T3	394	168	0	0
T28	391	166	0	0
T29	554	329	0	0
T30	783	433	0	0
T59	340	115	0	0
T60	291	69	0	0
T61	391	166	0	0
T122	1413	927	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	244	0	0
T8	439239	1	0	0
T10	0	1	0	0
T12	0	2	0	0
T14	0	2	0	0
T15	0	2	0	0
T112	0	1	0	0
T113	0	12	0	0
T252	38535	0	0	0
T300	0	2	0	0
T302	0	2	0	0
T319	58877	0	0	0
T342	0	1	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	119138494	0	0
T1	9760	9228	0	0
T2	10651	9393	0	0
T3	10145	9377	0	0
T28	18936	17686	0	0
T29	31558	30875	0	0
T30	29696	27702	0	0
T59	10335	9395	0	0
T60	11039	9502	0	0
T61	9790	9103	0	0
T122	49564	47907	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T28
0	1	Unreachable
1	0	Covered	T28,T7,T8

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T7,T8
1	1	Covered	T28,T7,T8

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T28,T7,T8
1	-	Covered	T7,T9

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T29,T30
0	1	Unreachable
1	0	Covered	T28,T7,T8

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T28,T7,T8
1	1	Covered	T28,T7,T8

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T29,T30
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T7,T8
0	0	1	Covered	T28,T7,T8
0	0	0	Covered	T28,T29,T30

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T7,T8
0	0	1	Covered	T28,T7,T8
0	0	0	Covered	T28,T29,T30

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119920069	93994	0	0
DstReqKnown_A	1533793	1327044	0	0
SrcAckBusyChk_A	119920069	237	0	0
SrcBusyKnown_A	119920069	119138494	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	93994	0	0
T7	41798	797	0	0
T8	0	399	0	0
T9	0	901	0	0
T10	0	298	0	0
T21	64181	0	0	0
T35	291302	0	0	0
T36	25293	0	0	0
T45	62966	0	0	0
T77	123929	0	0	0
T78	37602	0	0	0
T79	27029	0	0	0
T80	20955	0	0	0
T81	29177	0	0	0
T112	0	301	0	0
T113	0	2266	0	0
T300	0	4056	0	0
T302	0	692	0	0
T342	0	259	0	0
T343	0	763	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1533793	1327044	0	0
T1	452	229	0	0
T2	309	84	0	0
T3	394	168	0	0
T28	391	166	0	0
T29	554	329	0	0
T30	783	433	0	0
T59	340	115	0	0
T60	291	69	0	0
T61	391	166	0	0
T122	1413	927	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	237	0	0
T7	41798	2	0	0
T8	0	1	0	0
T9	0	2	0	0
T10	0	1	0	0
T21	64181	0	0	0
T35	291302	0	0	0
T36	25293	0	0	0
T45	62966	0	0	0
T77	123929	0	0	0
T78	37602	0	0	0
T79	27029	0	0	0
T80	20955	0	0	0
T81	29177	0	0	0
T112	0	1	0	0
T113	0	6	0	0
T300	0	10	0	0
T302	0	2	0	0
T342	0	1	0	0
T343	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	119138494	0	0
T1	9760	9228	0	0
T2	10651	9393	0	0
T3	10145	9377	0	0
T28	18936	17686	0	0
T29	31558	30875	0	0
T30	29696	27702	0	0
T59	10335	9395	0	0
T60	11039	9502	0	0
T61	9790	9103	0	0
T122	49564	47907	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T28
0	1	Unreachable
1	0	Covered	T28,T352,T8

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T28,T8,T10
1	-	Covered	T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T29,T30
0	1	Unreachable
1	0	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T29,T30
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119920069	99745	0	0
DstReqKnown_A	1533793	1327044	0	0
SrcAckBusyChk_A	119920069	250	0	0
SrcBusyKnown_A	119920069	119138494	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	99745	0	0
T8	439239	443	0	0
T10	0	292	0	0
T13	0	1073	0	0
T112	0	328	0	0
T113	0	349	0	0
T252	38535	0	0	0
T300	0	5600	0	0
T302	0	689	0	0
T319	58877	0	0	0
T342	0	266	0	0
T343	0	692	0	0
T344	0	656	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1533793	1327044	0	0
T1	452	229	0	0
T2	309	84	0	0
T3	394	168	0	0
T28	391	166	0	0
T29	554	329	0	0
T30	783	433	0	0
T59	340	115	0	0
T60	291	69	0	0
T61	391	166	0	0
T122	1413	927	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	250	0	0
T8	439239	1	0	0
T10	0	1	0	0
T13	0	2	0	0
T112	0	1	0	0
T113	0	1	0	0
T252	38535	0	0	0
T300	0	14	0	0
T302	0	2	0	0
T319	58877	0	0	0
T342	0	1	0	0
T343	0	2	0	0
T344	0	2	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	119138494	0	0
T1	9760	9228	0	0
T2	10651	9393	0	0
T3	10145	9377	0	0
T28	18936	17686	0	0
T29	31558	30875	0	0
T30	29696	27702	0	0
T59	10335	9395	0	0
T60	11039	9502	0	0
T61	9790	9103	0	0
T122	49564	47907	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	0	1
145	0	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T28
0	1	Unreachable
1	0	Covered	T28,T339,T8

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T28,T8,T10
1	-	Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T29,T30
0	1	Unreachable
1	0	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T29,T30
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119920069	80287	0	0
DstReqKnown_A	1533793	1327044	0	0
SrcAckBusyChk_A	119920069	205	0	0
SrcBusyKnown_A	119920069	119138494	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	80287	0	0
T8	439239	421	0	0
T10	0	302	0	0
T112	0	327	0	0
T113	0	1443	0	0
T252	38535	0	0	0
T300	0	2664	0	0
T301	0	25736	0	0
T302	0	691	0	0
T319	58877	0	0	0
T342	0	314	0	0
T343	0	753	0	0
T344	0	673	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1533793	1327044	0	0
T1	452	229	0	0
T2	309	84	0	0
T3	394	168	0	0
T28	391	166	0	0
T29	554	329	0	0
T30	783	433	0	0
T59	340	115	0	0
T60	291	69	0	0
T61	391	166	0	0
T122	1413	927	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	205	0	0
T8	439239	1	0	0
T10	0	1	0	0
T112	0	1	0	0
T113	0	4	0	0
T252	38535	0	0	0
T300	0	7	0	0
T301	0	62	0	0
T302	0	2	0	0
T319	58877	0	0	0
T342	0	1	0	0
T343	0	2	0	0
T344	0	2	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	119138494	0	0
T1	9760	9228	0	0
T2	10651	9393	0	0
T3	10145	9377	0	0
T28	18936	17686	0	0
T29	31558	30875	0	0
T30	29696	27702	0	0
T59	10335	9395	0	0
T60	11039	9502	0	0
T61	9790	9103	0	0
T122	49564	47907	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	0	1
145	0	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T28
0	1	Unreachable
1	0	Covered	T28,T8,T10

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T28,T8,T10
1	-	Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T29,T30
0	1	Unreachable
1	0	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T29,T30
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119920069	100800	0	0
DstReqKnown_A	1533793	1327044	0	0
SrcAckBusyChk_A	119920069	254	0	0
SrcBusyKnown_A	119920069	119138494	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	100800	0	0
T8	439239	406	0	0
T10	0	267	0	0
T112	0	321	0	0
T113	0	3166	0	0
T252	38535	0	0	0
T300	0	2294	0	0
T301	0	25742	0	0
T302	0	689	0	0
T319	58877	0	0	0
T342	0	252	0	0
T343	0	719	0	0
T344	0	791	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1533793	1327044	0	0
T1	452	229	0	0
T2	309	84	0	0
T3	394	168	0	0
T28	391	166	0	0
T29	554	329	0	0
T30	783	433	0	0
T59	340	115	0	0
T60	291	69	0	0
T61	391	166	0	0
T122	1413	927	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	254	0	0
T8	439239	1	0	0
T10	0	1	0	0
T112	0	1	0	0
T113	0	8	0	0
T252	38535	0	0	0
T300	0	6	0	0
T301	0	62	0	0
T302	0	2	0	0
T319	58877	0	0	0
T342	0	1	0	0
T343	0	2	0	0
T344	0	2	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	119138494	0	0
T1	9760	9228	0	0
T2	10651	9393	0	0
T3	10145	9377	0	0
T28	18936	17686	0	0
T29	31558	30875	0	0
T30	29696	27702	0	0
T59	10335	9395	0	0
T60	11039	9502	0	0
T61	9790	9103	0	0
T122	49564	47907	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	0	1
145	0	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T28
0	1	Unreachable
1	0	Covered	T28,T8,T10

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T28,T8,T10
1	-	Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T29,T30
0	1	Unreachable
1	0	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T29,T30
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119920069	106919	0	0
DstReqKnown_A	1533793	1327044	0	0
SrcAckBusyChk_A	119920069	269	0	0
SrcBusyKnown_A	119920069	119138494	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	106919	0	0
T8	439239	448	0	0
T10	0	323	0	0
T112	0	270	0	0
T113	0	1452	0	0
T252	38535	0	0	0
T300	0	7763	0	0
T301	0	25690	0	0
T302	0	737	0	0
T319	58877	0	0	0
T342	0	343	0	0
T343	0	662	0	0
T344	0	677	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1533793	1327044	0	0
T1	452	229	0	0
T2	309	84	0	0
T3	394	168	0	0
T28	391	166	0	0
T29	554	329	0	0
T30	783	433	0	0
T59	340	115	0	0
T60	291	69	0	0
T61	391	166	0	0
T122	1413	927	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	269	0	0
T8	439239	1	0	0
T10	0	1	0	0
T112	0	1	0	0
T113	0	4	0	0
T252	38535	0	0	0
T300	0	19	0	0
T301	0	62	0	0
T302	0	2	0	0
T319	58877	0	0	0
T342	0	1	0	0
T343	0	2	0	0
T344	0	2	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	119138494	0	0
T1	9760	9228	0	0
T2	10651	9393	0	0
T3	10145	9377	0	0
T28	18936	17686	0	0
T29	31558	30875	0	0
T30	29696	27702	0	0
T59	10335	9395	0	0
T60	11039	9502	0	0
T61	9790	9103	0	0
T122	49564	47907	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	0	1
145	0	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T28
0	1	Unreachable
1	0	Covered	T28,T8,T10

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T28,T8,T10
1	-	Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T29,T30
0	1	Unreachable
1	0	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T29,T30
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119920069	88771	0	0
DstReqKnown_A	1533793	1327044	0	0
SrcAckBusyChk_A	119920069	225	0	0
SrcBusyKnown_A	119920069	119138494	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	88771	0	0
T8	439239	449	0	0
T10	0	336	0	0
T112	0	286	0	0
T113	0	1436	0	0
T252	38535	0	0	0
T300	0	5727	0	0
T301	0	25708	0	0
T302	0	742	0	0
T319	58877	0	0	0
T342	0	322	0	0
T343	0	705	0	0
T344	0	734	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1533793	1327044	0	0
T1	452	229	0	0
T2	309	84	0	0
T3	394	168	0	0
T28	391	166	0	0
T29	554	329	0	0
T30	783	433	0	0
T59	340	115	0	0
T60	291	69	0	0
T61	391	166	0	0
T122	1413	927	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	225	0	0
T8	439239	1	0	0
T10	0	1	0	0
T112	0	1	0	0
T113	0	4	0	0
T252	38535	0	0	0
T300	0	14	0	0
T301	0	62	0	0
T302	0	2	0	0
T319	58877	0	0	0
T342	0	1	0	0
T343	0	2	0	0
T344	0	2	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	119138494	0	0
T1	9760	9228	0	0
T2	10651	9393	0	0
T3	10145	9377	0	0
T28	18936	17686	0	0
T29	31558	30875	0	0
T30	29696	27702	0	0
T59	10335	9395	0	0
T60	11039	9502	0	0
T61	9790	9103	0	0
T122	49564	47907	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	0	1
145	0	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T28
0	1	Unreachable
1	0	Covered	T28,T340,T8

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T28,T8,T10
1	-	Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T29,T30
0	1	Unreachable
1	0	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T29,T30
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119920069	102130	0	0
DstReqKnown_A	1533793	1327044	0	0
SrcAckBusyChk_A	119920069	255	0	0
SrcBusyKnown_A	119920069	119138494	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	102130	0	0
T8	439239	421	0	0
T10	0	344	0	0
T112	0	278	0	0
T113	0	1169	0	0
T252	38535	0	0	0
T300	0	4879	0	0
T301	0	25696	0	0
T302	0	731	0	0
T319	58877	0	0	0
T342	0	340	0	0
T343	0	829	0	0
T344	0	773	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1533793	1327044	0	0
T1	452	229	0	0
T2	309	84	0	0
T3	394	168	0	0
T28	391	166	0	0
T29	554	329	0	0
T30	783	433	0	0
T59	340	115	0	0
T60	291	69	0	0
T61	391	166	0	0
T122	1413	927	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	255	0	0
T8	439239	1	0	0
T10	0	1	0	0
T112	0	1	0	0
T113	0	3	0	0
T252	38535	0	0	0
T300	0	12	0	0
T301	0	62	0	0
T302	0	2	0	0
T319	58877	0	0	0
T342	0	1	0	0
T343	0	2	0	0
T344	0	2	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	119138494	0	0
T1	9760	9228	0	0
T2	10651	9393	0	0
T3	10145	9377	0	0
T28	18936	17686	0	0
T29	31558	30875	0	0
T30	29696	27702	0	0
T59	10335	9395	0	0
T60	11039	9502	0	0
T61	9790	9103	0	0
T122	49564	47907	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T28
0	1	Unreachable
1	0	Covered	T31,T28,T337

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T29,T30
0	1	Unreachable
1	0	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T29,T30
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119920069	113848	0	0
DstReqKnown_A	1533793	1327044	0	0
SrcAckBusyChk_A	119920069	287	0	0
SrcBusyKnown_A	119920069	119138494	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	113848	0	0
T8	439239	390	0	0
T10	0	250	0	0
T12	0	258	0	0
T14	0	395	0	0
T15	0	289	0	0
T112	0	321	0	0
T113	0	3131	0	0
T252	38535	0	0	0
T300	0	4796	0	0
T302	0	643	0	0
T319	58877	0	0	0
T342	0	342	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1533793	1327044	0	0
T1	452	229	0	0
T2	309	84	0	0
T3	394	168	0	0
T28	391	166	0	0
T29	554	329	0	0
T30	783	433	0	0
T59	340	115	0	0
T60	291	69	0	0
T61	391	166	0	0
T122	1413	927	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	287	0	0
T8	439239	1	0	0
T10	0	1	0	0
T12	0	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T112	0	1	0	0
T113	0	8	0	0
T252	38535	0	0	0
T300	0	12	0	0
T302	0	2	0	0
T319	58877	0	0	0
T342	0	1	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	119138494	0	0
T1	9760	9228	0	0
T2	10651	9393	0	0
T3	10145	9377	0	0
T28	18936	17686	0	0
T29	31558	30875	0	0
T30	29696	27702	0	0
T59	10335	9395	0	0
T60	11039	9502	0	0
T61	9790	9103	0	0
T122	49564	47907	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T28
0	1	Unreachable
1	0	Covered	T28,T340,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T7,T8
1	1	Covered	T28,T7,T8

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T29,T30
0	1	Unreachable
1	0	Covered	T28,T7,T8

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T28,T7,T8
1	1	Covered	T28,T7,T8

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T29,T30
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T7,T8
0	0	1	Covered	T28,T7,T8
0	0	0	Covered	T28,T29,T30

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T7,T8
0	0	1	Covered	T28,T7,T8
0	0	0	Covered	T28,T29,T30

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119920069	102882	0	0
DstReqKnown_A	1533793	1327044	0	0
SrcAckBusyChk_A	119920069	259	0	0
SrcBusyKnown_A	119920069	119138494	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	102882	0	0
T7	41798	260	0	0
T8	0	414	0	0
T9	0	367	0	0
T10	0	284	0	0
T21	64181	0	0	0
T35	291302	0	0	0
T36	25293	0	0	0
T45	62966	0	0	0
T77	123929	0	0	0
T78	37602	0	0	0
T79	27029	0	0	0
T80	20955	0	0	0
T81	29177	0	0	0
T112	0	287	0	0
T113	0	4112	0	0
T300	0	2366	0	0
T302	0	692	0	0
T342	0	286	0	0
T343	0	659	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1533793	1327044	0	0
T1	452	229	0	0
T2	309	84	0	0
T3	394	168	0	0
T28	391	166	0	0
T29	554	329	0	0
T30	783	433	0	0
T59	340	115	0	0
T60	291	69	0	0
T61	391	166	0	0
T122	1413	927	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	259	0	0
T7	41798	1	0	0
T8	0	1	0	0
T9	0	1	0	0
T10	0	1	0	0
T21	64181	0	0	0
T35	291302	0	0	0
T36	25293	0	0	0
T45	62966	0	0	0
T77	123929	0	0	0
T78	37602	0	0	0
T79	27029	0	0	0
T80	20955	0	0	0
T81	29177	0	0	0
T112	0	1	0	0
T113	0	10	0	0
T300	0	6	0	0
T302	0	2	0	0
T342	0	1	0	0
T343	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	119138494	0	0
T1	9760	9228	0	0
T2	10651	9393	0	0
T3	10145	9377	0	0
T28	18936	17686	0	0
T29	31558	30875	0	0
T30	29696	27702	0	0
T59	10335	9395	0	0
T60	11039	9502	0	0
T61	9790	9103	0	0
T122	49564	47907	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T28
0	1	Unreachable
1	0	Covered	T28,T352,T338

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T29,T30
0	1	Unreachable
1	0	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T29,T30
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119920069	109959	0	0
DstReqKnown_A	1533793	1327044	0	0
SrcAckBusyChk_A	119920069	275	0	0
SrcBusyKnown_A	119920069	119138494	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	109959	0	0
T8	439239	468	0	0
T10	0	301	0	0
T13	0	419	0	0
T112	0	327	0	0
T113	0	1531	0	0
T252	38535	0	0	0
T300	0	6532	0	0
T302	0	738	0	0
T319	58877	0	0	0
T342	0	339	0	0
T343	0	642	0	0
T344	0	748	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1533793	1327044	0	0
T1	452	229	0	0
T2	309	84	0	0
T3	394	168	0	0
T28	391	166	0	0
T29	554	329	0	0
T30	783	433	0	0
T59	340	115	0	0
T60	291	69	0	0
T61	391	166	0	0
T122	1413	927	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	275	0	0
T8	439239	1	0	0
T10	0	1	0	0
T13	0	1	0	0
T112	0	1	0	0
T113	0	4	0	0
T252	38535	0	0	0
T300	0	16	0	0
T302	0	2	0	0
T319	58877	0	0	0
T342	0	1	0	0
T343	0	2	0	0
T344	0	2	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	119138494	0	0
T1	9760	9228	0	0
T2	10651	9393	0	0
T3	10145	9377	0	0
T28	18936	17686	0	0
T29	31558	30875	0	0
T30	29696	27702	0	0
T59	10335	9395	0	0
T60	11039	9502	0	0
T61	9790	9103	0	0
T122	49564	47907	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T28
0	1	Unreachable
1	0	Covered	T28,T8,T10

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T29,T30
0	1	Unreachable
1	0	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T29,T30
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119920069	92767	0	0
DstReqKnown_A	1533793	1327044	0	0
SrcAckBusyChk_A	119920069	235	0	0
SrcBusyKnown_A	119920069	119138494	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	92767	0	0
T8	439239	394	0	0
T10	0	293	0	0
T112	0	320	0	0
T113	0	1799	0	0
T252	38535	0	0	0
T300	0	5148	0	0
T301	0	26452	0	0
T302	0	711	0	0
T319	58877	0	0	0
T342	0	350	0	0
T343	0	715	0	0
T344	0	718	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1533793	1327044	0	0
T1	452	229	0	0
T2	309	84	0	0
T3	394	168	0	0
T28	391	166	0	0
T29	554	329	0	0
T30	783	433	0	0
T59	340	115	0	0
T60	291	69	0	0
T61	391	166	0	0
T122	1413	927	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	235	0	0
T8	439239	1	0	0
T10	0	1	0	0
T112	0	1	0	0
T113	0	5	0	0
T252	38535	0	0	0
T300	0	13	0	0
T301	0	64	0	0
T302	0	2	0	0
T319	58877	0	0	0
T342	0	1	0	0
T343	0	2	0	0
T344	0	2	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	119138494	0	0
T1	9760	9228	0	0
T2	10651	9393	0	0
T3	10145	9377	0	0
T28	18936	17686	0	0
T29	31558	30875	0	0
T30	29696	27702	0	0
T59	10335	9395	0	0
T60	11039	9502	0	0
T61	9790	9103	0	0
T122	49564	47907	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T28
0	1	Unreachable
1	0	Covered	T28,T8,T10

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T29,T30
0	1	Unreachable
1	0	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T29,T30
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119920069	92268	0	0
DstReqKnown_A	1533793	1327044	0	0
SrcAckBusyChk_A	119920069	232	0	0
SrcBusyKnown_A	119920069	119138494	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	92268	0	0
T8	439239	399	0	0
T10	0	325	0	0
T112	0	287	0	0
T113	0	757	0	0
T252	38535	0	0	0
T300	0	5283	0	0
T301	0	26520	0	0
T302	0	765	0	0
T319	58877	0	0	0
T342	0	328	0	0
T343	0	620	0	0
T344	0	805	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1533793	1327044	0	0
T1	452	229	0	0
T2	309	84	0	0
T3	394	168	0	0
T28	391	166	0	0
T29	554	329	0	0
T30	783	433	0	0
T59	340	115	0	0
T60	291	69	0	0
T61	391	166	0	0
T122	1413	927	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	232	0	0
T8	439239	1	0	0
T10	0	1	0	0
T112	0	1	0	0
T113	0	2	0	0
T252	38535	0	0	0
T300	0	13	0	0
T301	0	64	0	0
T302	0	2	0	0
T319	58877	0	0	0
T342	0	1	0	0
T343	0	2	0	0
T344	0	2	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	119138494	0	0
T1	9760	9228	0	0
T2	10651	9393	0	0
T3	10145	9377	0	0
T28	18936	17686	0	0
T29	31558	30875	0	0
T30	29696	27702	0	0
T59	10335	9395	0	0
T60	11039	9502	0	0
T61	9790	9103	0	0
T122	49564	47907	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T28
0	1	Unreachable
1	0	Covered	T28,T340,T352

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T29,T30
0	1	Unreachable
1	0	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T29,T30
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119920069	97267	0	0
DstReqKnown_A	1533793	1327044	0	0
SrcAckBusyChk_A	119920069	246	0	0
SrcBusyKnown_A	119920069	119138494	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	97267	0	0
T8	439239	445	0	0
T10	0	329	0	0
T112	0	331	0	0
T113	0	4792	0	0
T252	38535	0	0	0
T300	0	8118	0	0
T301	0	26459	0	0
T302	0	694	0	0
T319	58877	0	0	0
T342	0	291	0	0
T343	0	671	0	0
T344	0	750	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1533793	1327044	0	0
T1	452	229	0	0
T2	309	84	0	0
T3	394	168	0	0
T28	391	166	0	0
T29	554	329	0	0
T30	783	433	0	0
T59	340	115	0	0
T60	291	69	0	0
T61	391	166	0	0
T122	1413	927	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	246	0	0
T8	439239	1	0	0
T10	0	1	0	0
T112	0	1	0	0
T113	0	12	0	0
T252	38535	0	0	0
T300	0	20	0	0
T301	0	64	0	0
T302	0	2	0	0
T319	58877	0	0	0
T342	0	1	0	0
T343	0	2	0	0
T344	0	2	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	119138494	0	0
T1	9760	9228	0	0
T2	10651	9393	0	0
T3	10145	9377	0	0
T28	18936	17686	0	0
T29	31558	30875	0	0
T30	29696	27702	0	0
T59	10335	9395	0	0
T60	11039	9502	0	0
T61	9790	9103	0	0
T122	49564	47907	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T28
0	1	Unreachable
1	0	Covered	T28,T8,T10

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T29,T30
0	1	Unreachable
1	0	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T29,T30
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119920069	102036	0	0
DstReqKnown_A	1533793	1327044	0	0
SrcAckBusyChk_A	119920069	257	0	0
SrcBusyKnown_A	119920069	119138494	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	102036	0	0
T8	439239	369	0	0
T10	0	244	0	0
T112	0	360	0	0
T113	0	1801	0	0
T252	38535	0	0	0
T300	0	1981	0	0
T301	0	26476	0	0
T302	0	715	0	0
T319	58877	0	0	0
T342	0	253	0	0
T343	0	691	0	0
T344	0	764	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1533793	1327044	0	0
T1	452	229	0	0
T2	309	84	0	0
T3	394	168	0	0
T28	391	166	0	0
T29	554	329	0	0
T30	783	433	0	0
T59	340	115	0	0
T60	291	69	0	0
T61	391	166	0	0
T122	1413	927	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	257	0	0
T8	439239	1	0	0
T10	0	1	0	0
T112	0	1	0	0
T113	0	5	0	0
T252	38535	0	0	0
T300	0	5	0	0
T301	0	64	0	0
T302	0	2	0	0
T319	58877	0	0	0
T342	0	1	0	0
T343	0	2	0	0
T344	0	2	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	119138494	0	0
T1	9760	9228	0	0
T2	10651	9393	0	0
T3	10145	9377	0	0
T28	18936	17686	0	0
T29	31558	30875	0	0
T30	29696	27702	0	0
T59	10335	9395	0	0
T60	11039	9502	0	0
T61	9790	9103	0	0
T122	49564	47907	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T28
0	1	Unreachable
1	0	Covered	T28,T352,T8

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T29,T30
0	1	Unreachable
1	0	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T29,T30
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119920069	85157	0	0
DstReqKnown_A	1533793	1327044	0	0
SrcAckBusyChk_A	119920069	216	0	0
SrcBusyKnown_A	119920069	119138494	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	85157	0	0
T8	439239	367	0	0
T10	0	258	0	0
T112	0	286	0	0
T113	0	2335	0	0
T252	38535	0	0	0
T300	0	3670	0	0
T301	0	26556	0	0
T302	0	658	0	0
T319	58877	0	0	0
T342	0	249	0	0
T343	0	728	0	0
T344	0	693	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1533793	1327044	0	0
T1	452	229	0	0
T2	309	84	0	0
T3	394	168	0	0
T28	391	166	0	0
T29	554	329	0	0
T30	783	433	0	0
T59	340	115	0	0
T60	291	69	0	0
T61	391	166	0	0
T122	1413	927	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	216	0	0
T8	439239	1	0	0
T10	0	1	0	0
T112	0	1	0	0
T113	0	6	0	0
T252	38535	0	0	0
T300	0	9	0	0
T301	0	64	0	0
T302	0	2	0	0
T319	58877	0	0	0
T342	0	1	0	0
T343	0	2	0	0
T344	0	2	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	119138494	0	0
T1	9760	9228	0	0
T2	10651	9393	0	0
T3	10145	9377	0	0
T28	18936	17686	0	0
T29	31558	30875	0	0
T30	29696	27702	0	0
T59	10335	9395	0	0
T60	11039	9502	0	0
T61	9790	9103	0	0
T122	49564	47907	0	0