Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.25	100.00	89.01			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc	93.88	90.91	84.62			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc	93.88	90.91	84.62			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc	93.88	90.91	84.62			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc	93.88	90.91	84.62			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc	93.88	90.91	84.62			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc	98.08	100.00	92.31			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc	98.08	100.00	92.31			100.00	100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc	98.08	100.00	92.31			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=2,ResetVal=0,BitMask=3,DstWrReq=0,TxnWidth=3 + DataWidth=10,ResetVal=0,BitMask=769,DstWrReq=1,TxnWidth=3 + DataWidth=4,ResetVal,BitMask=15,DstWrReq=1,TxnWidth=3 + DataWidth=20,ResetVal,BitMask=1048575,DstWrReq=0,TxnWidth=3 + DataWidth=18,ResetVal=118010,BitMask=262143,DstWrReq=0,TxnWidth=3 + DataWidth=16,ResetVal,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=12,ResetVal=0,BitMask=4095,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=0,TxnWidth=3 + DataWidth=17,ResetVal=2000,BitMask=131071,DstWrReq=0,TxnWidth=3 + DataWidth=7,ResetVal=0,BitMask=119,DstWrReq=0,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal,BitMask,DstWrReq=0,TxnWidth=3 + DataWidth=4,ResetVal=0,BitMask=15,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=1,TxnWidth=3 + DataWidth=28,ResetVal=0,BitMask=268374015,DstWrReq=1,TxnWidth=3 + DataWidth=8,ResetVal=0,BitMask=255,DstWrReq=1,TxnWidth=3 + DataWidth=6,ResetVal=0,BitMask=63,DstWrReq=0,TxnWidth=3 + DataWidth=13,ResetVal=0,BitMask=8191,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
97.73	90.91

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

SCORE	COND
97.73	90.91

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

SCORE	COND
97.73	90.91

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

SCORE	COND
97.73	90.91

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

SCORE	COND
97.73	90.91

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

SCORE	COND
97.73	90.91

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

SCORE	COND
97.73	90.91

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

SCORE	COND
97.73	90.91

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

SCORE	COND
97.73	90.91

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

SCORE	COND
97.73	90.91

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

SCORE	COND
97.73	90.91

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

SCORE	COND
97.73	90.91

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

SCORE	COND
97.73	90.91

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

SCORE	COND
97.73	90.91

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

SCORE	COND
97.73	90.91

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

SCORE	COND
97.73	90.91

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

SCORE	COND
96.43	85.71

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T28
0	1	Unreachable
1	0	Covered	T28,T337,T338

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T7,T8
1	1	Covered	T28,T7,T8

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T29,T30
0	1	Covered	T7,T9,T12
1	0	Covered	T28,T7,T8

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T28,T7,T8
1	1	Covered	T28,T7,T8

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T29,T30
1	0	Not Covered
1	1	Covered	T7,T9,T12

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 + DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
98.08	92.31

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

SCORE	COND
98.08	92.31

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

SCORE	COND
98.08	92.31

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

SCORE	COND
93.88	84.62

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

SCORE	COND
93.88	84.62

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

SCORE	COND
93.88	84.62

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

SCORE	COND
93.88	84.62

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

SCORE	COND
93.88	84.62

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T28
0	1	Unreachable
1	0	Covered	T28,T339,T340

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T7,T8
1	1	Covered	T28,T7,T8

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T28,T7,T8
1	-	Covered	T7,T9,T12

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T29,T30
0	1	Unreachable
1	0	Covered	T28,T7,T8

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T28,T7,T8
1	1	Covered	T28,T7,T8

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T29,T30
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T7,T8
0	0	1	Covered	T28,T7,T8
0	0	0	Covered	T28,T29,T30

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T7,T8
0	0	1	Covered	T28,T7,T8
0	0	0	Covered	T28,T29,T30

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	2430106	0	0
DstReqKnown_A	38344825	33176100	0	0
SrcAckBusyChk_A	2147483647	6073	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2430106	0	0
T7	83596	1057	0	0
T8	10102497	10506	0	0
T9	0	1268	0	0
T10	0	7584	0	0
T11	0	266	0	0
T12	0	3793	0	0
T13	0	1492	0	0
T14	0	2742	0	0
T15	0	1710	0	0
T16	0	319	0	0
T21	128362	0	0	0
T35	582604	0	0	0
T36	50586	0	0	0
T45	125932	0	0	0
T77	247858	0	0	0
T78	75204	0	0	0
T79	54058	0	0	0
T80	41910	0	0	0
T81	58354	0	0	0
T112	0	7541	0	0
T113	0	57580	0	0
T252	886305	0	0	0
T300	0	109445	0	0
T301	0	446758	0	0
T302	0	17806	0	0
T319	1354171	0	0	0
T341	0	312	0	0
T342	0	7575	0	0
T343	0	14863	0	0
T344	0	13754	0	0
T345	3886563	0	0	0
T346	1320430	0	0	0
T347	842904	0	0	0
T348	761047	0	0	0
T349	3755440	0	0	0
T350	956892	0	0	0
T351	1442215	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38344825	33176100	0	0
T1	11300	5725	0	0
T2	7725	2100	0	0
T3	9850	4200	0	0
T28	9775	4150	0	0
T29	13850	8225	0	0
T30	19575	10825	0	0
T59	8500	2875	0	0
T60	7275	1725	0	0
T61	9775	4150	0	0
T122	35325	23175	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6073	0	0
T7	83596	3	0	0
T8	10102497	25	0	0
T9	0	3	0	0
T10	0	25	0	0
T11	0	1	0	0
T12	0	9	0	0
T13	0	3	0	0
T14	0	6	0	0
T15	0	4	0	0
T16	0	1	0	0
T21	128362	0	0	0
T35	582604	0	0	0
T36	50586	0	0	0
T45	125932	0	0	0
T77	247858	0	0	0
T78	75204	0	0	0
T79	54058	0	0	0
T80	41910	0	0	0
T81	58354	0	0	0
T112	0	25	0	0
T113	0	148	0	0
T252	886305	0	0	0
T300	0	269	0	0
T301	0	1078	0	0
T302	0	50	0	0
T319	1354171	0	0	0
T342	0	25	0	0
T343	0	44	0	0
T344	0	38	0	0
T345	3886563	0	0	0
T346	1320430	0	0	0
T347	842904	0	0	0
T348	761047	0	0	0
T349	3755440	0	0	0
T350	956892	0	0	0
T351	1442215	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	244000	230700	0	0
T2	266275	234825	0	0
T3	253625	234425	0	0
T28	473400	442150	0	0
T29	788950	771875	0	0
T30	742400	692550	0	0
T59	258375	234875	0	0
T60	275975	237550	0	0
T61	244750	227575	0	0
T122	1239100	1197675	0	0