Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.71	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.71	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.71	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.71	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.71	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.71	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.71	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.71	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.68	96.99	84.51			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.23	99.71	97.20			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T28
0	1	Unreachable
1	0	Covered	T28,T8,T10

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T29,T30
0	1	Unreachable
1	0	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T29,T30
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119920069	83657	0	0
DstReqKnown_A	1533793	1327044	0	0
SrcAckBusyChk_A	119920069	212	0	0
SrcBusyKnown_A	119920069	119138494	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	83657	0	0
T8	439239	434	0	0
T10	0	246	0	0
T112	0	332	0	0
T113	0	2305	0	0
T252	38535	0	0	0
T300	0	2360	0	0
T301	0	26571	0	0
T302	0	736	0	0
T319	58877	0	0	0
T342	0	261	0	0
T343	0	688	0	0
T344	0	666	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1533793	1327044	0	0
T1	452	229	0	0
T2	309	84	0	0
T3	394	168	0	0
T28	391	166	0	0
T29	554	329	0	0
T30	783	433	0	0
T59	340	115	0	0
T60	291	69	0	0
T61	391	166	0	0
T122	1413	927	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	212	0	0
T8	439239	1	0	0
T10	0	1	0	0
T112	0	1	0	0
T113	0	6	0	0
T252	38535	0	0	0
T300	0	6	0	0
T301	0	64	0	0
T302	0	2	0	0
T319	58877	0	0	0
T342	0	1	0	0
T343	0	2	0	0
T344	0	2	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	119138494	0	0
T1	9760	9228	0	0
T2	10651	9393	0	0
T3	10145	9377	0	0
T28	18936	17686	0	0
T29	31558	30875	0	0
T30	29696	27702	0	0
T59	10335	9395	0	0
T60	11039	9502	0	0
T61	9790	9103	0	0
T122	49564	47907	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T28
0	1	Unreachable
1	0	Covered	T28,T337,T338

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T29,T30
0	1	Unreachable
1	0	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T29,T30
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119920069	106003	0	0
DstReqKnown_A	1533793	1327044	0	0
SrcAckBusyChk_A	119920069	268	0	0
SrcBusyKnown_A	119920069	119138494	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	106003	0	0
T8	439239	438	0	0
T10	0	359	0	0
T11	0	266	0	0
T16	0	319	0	0
T112	0	279	0	0
T113	0	3139	0	0
T252	38535	0	0	0
T300	0	9715	0	0
T302	0	701	0	0
T319	58877	0	0	0
T341	0	312	0	0
T342	0	358	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1533793	1327044	0	0
T1	452	229	0	0
T2	309	84	0	0
T3	394	168	0	0
T28	391	166	0	0
T29	554	329	0	0
T30	783	433	0	0
T59	340	115	0	0
T60	291	69	0	0
T61	391	166	0	0
T122	1413	927	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	268	0	0
T8	439239	1	0	0
T10	0	1	0	0
T11	0	1	0	0
T16	0	1	0	0
T112	0	1	0	0
T113	0	8	0	0
T252	38535	0	0	0
T300	0	24	0	0
T302	0	2	0	0
T319	58877	0	0	0
T342	0	1	0	0
T343	0	2	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	119138494	0	0
T1	9760	9228	0	0
T2	10651	9393	0	0
T3	10145	9377	0	0
T28	18936	17686	0	0
T29	31558	30875	0	0
T30	29696	27702	0	0
T59	10335	9395	0	0
T60	11039	9502	0	0
T61	9790	9103	0	0
T122	49564	47907	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T28
0	1	Unreachable
1	0	Covered	T28,T338,T8

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T29,T30
0	1	Unreachable
1	0	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T29,T30
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119920069	92639	0	0
DstReqKnown_A	1533793	1327044	0	0
SrcAckBusyChk_A	119920069	234	0	0
SrcBusyKnown_A	119920069	119138494	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	92639	0	0
T8	439239	397	0	0
T10	0	354	0	0
T112	0	257	0	0
T113	0	2282	0	0
T252	38535	0	0	0
T300	0	4064	0	0
T301	0	26466	0	0
T302	0	783	0	0
T319	58877	0	0	0
T342	0	315	0	0
T343	0	791	0	0
T344	0	748	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1533793	1327044	0	0
T1	452	229	0	0
T2	309	84	0	0
T3	394	168	0	0
T28	391	166	0	0
T29	554	329	0	0
T30	783	433	0	0
T59	340	115	0	0
T60	291	69	0	0
T61	391	166	0	0
T122	1413	927	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	234	0	0
T8	439239	1	0	0
T10	0	1	0	0
T112	0	1	0	0
T113	0	6	0	0
T252	38535	0	0	0
T300	0	10	0	0
T301	0	64	0	0
T302	0	2	0	0
T319	58877	0	0	0
T342	0	1	0	0
T343	0	2	0	0
T344	0	2	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	119138494	0	0
T1	9760	9228	0	0
T2	10651	9393	0	0
T3	10145	9377	0	0
T28	18936	17686	0	0
T29	31558	30875	0	0
T30	29696	27702	0	0
T59	10335	9395	0	0
T60	11039	9502	0	0
T61	9790	9103	0	0
T122	49564	47907	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T28
0	1	Unreachable
1	0	Covered	T28,T8,T10

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T29,T30
0	1	Unreachable
1	0	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T29,T30
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119920069	83063	0	0
DstReqKnown_A	1533793	1327044	0	0
SrcAckBusyChk_A	119920069	210	0	0
SrcBusyKnown_A	119920069	119138494	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	83063	0	0
T8	439239	444	0	0
T10	0	348	0	0
T112	0	346	0	0
T113	0	741	0	0
T252	38535	0	0	0
T300	0	2741	0	0
T301	0	26553	0	0
T302	0	673	0	0
T319	58877	0	0	0
T342	0	246	0	0
T343	0	688	0	0
T344	0	753	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1533793	1327044	0	0
T1	452	229	0	0
T2	309	84	0	0
T3	394	168	0	0
T28	391	166	0	0
T29	554	329	0	0
T30	783	433	0	0
T59	340	115	0	0
T60	291	69	0	0
T61	391	166	0	0
T122	1413	927	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	210	0	0
T8	439239	1	0	0
T10	0	1	0	0
T112	0	1	0	0
T113	0	2	0	0
T252	38535	0	0	0
T300	0	7	0	0
T301	0	64	0	0
T302	0	2	0	0
T319	58877	0	0	0
T342	0	1	0	0
T343	0	2	0	0
T344	0	2	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	119138494	0	0
T1	9760	9228	0	0
T2	10651	9393	0	0
T3	10145	9377	0	0
T28	18936	17686	0	0
T29	31558	30875	0	0
T30	29696	27702	0	0
T59	10335	9395	0	0
T60	11039	9502	0	0
T61	9790	9103	0	0
T122	49564	47907	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T28
0	1	Unreachable
1	0	Covered	T28,T8,T10

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T29,T30
0	1	Unreachable
1	0	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T29,T30
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119920069	98788	0	0
DstReqKnown_A	1533793	1327044	0	0
SrcAckBusyChk_A	119920069	251	0	0
SrcBusyKnown_A	119920069	119138494	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	98788	0	0
T8	439239	425	0	0
T10	0	315	0	0
T112	0	297	0	0
T113	0	2669	0	0
T252	38535	0	0	0
T300	0	4867	0	0
T301	0	26560	0	0
T302	0	799	0	0
T319	58877	0	0	0
T342	0	317	0	0
T343	0	679	0	0
T344	0	662	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1533793	1327044	0	0
T1	452	229	0	0
T2	309	84	0	0
T3	394	168	0	0
T28	391	166	0	0
T29	554	329	0	0
T30	783	433	0	0
T59	340	115	0	0
T60	291	69	0	0
T61	391	166	0	0
T122	1413	927	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	251	0	0
T8	439239	1	0	0
T10	0	1	0	0
T112	0	1	0	0
T113	0	7	0	0
T252	38535	0	0	0
T300	0	12	0	0
T301	0	64	0	0
T302	0	2	0	0
T319	58877	0	0	0
T342	0	1	0	0
T343	0	2	0	0
T344	0	2	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	119138494	0	0
T1	9760	9228	0	0
T2	10651	9393	0	0
T3	10145	9377	0	0
T28	18936	17686	0	0
T29	31558	30875	0	0
T30	29696	27702	0	0
T59	10335	9395	0	0
T60	11039	9502	0	0
T61	9790	9103	0	0
T122	49564	47907	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T28
0	1	Unreachable
1	0	Covered	T28,T8,T10

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T29,T30
0	1	Unreachable
1	0	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T29,T30
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119920069	98866	0	0
DstReqKnown_A	1533793	1327044	0	0
SrcAckBusyChk_A	119920069	248	0	0
SrcBusyKnown_A	119920069	119138494	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	98866	0	0
T8	439239	464	0	0
T10	0	330	0	0
T112	0	342	0	0
T113	0	4440	0	0
T252	38535	0	0	0
T300	0	4800	0	0
T301	0	26501	0	0
T302	0	694	0	0
T319	58877	0	0	0
T342	0	273	0	0
T343	0	762	0	0
T344	0	740	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1533793	1327044	0	0
T1	452	229	0	0
T2	309	84	0	0
T3	394	168	0	0
T28	391	166	0	0
T29	554	329	0	0
T30	783	433	0	0
T59	340	115	0	0
T60	291	69	0	0
T61	391	166	0	0
T122	1413	927	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	248	0	0
T8	439239	1	0	0
T10	0	1	0	0
T112	0	1	0	0
T113	0	11	0	0
T252	38535	0	0	0
T300	0	12	0	0
T301	0	64	0	0
T302	0	2	0	0
T319	58877	0	0	0
T342	0	1	0	0
T343	0	2	0	0
T344	0	2	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	119138494	0	0
T1	9760	9228	0	0
T2	10651	9393	0	0
T3	10145	9377	0	0
T28	18936	17686	0	0
T29	31558	30875	0	0
T30	29696	27702	0	0
T59	10335	9395	0	0
T60	11039	9502	0	0
T61	9790	9103	0	0
T122	49564	47907	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T28
0	1	Unreachable
1	0	Covered	T28,T353,T8

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T29,T30
0	1	Unreachable
1	0	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T29,T30
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119920069	90122	0	0
DstReqKnown_A	1533793	1327044	0	0
SrcAckBusyChk_A	119920069	228	0	0
SrcBusyKnown_A	119920069	119138494	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	90122	0	0
T8	439239	364	0	0
T10	0	305	0	0
T112	0	275	0	0
T113	0	3586	0	0
T252	38535	0	0	0
T300	0	751	0	0
T301	0	26561	0	0
T302	0	706	0	0
T319	58877	0	0	0
T342	0	348	0	0
T343	0	607	0	0
T344	0	725	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1533793	1327044	0	0
T1	452	229	0	0
T2	309	84	0	0
T3	394	168	0	0
T28	391	166	0	0
T29	554	329	0	0
T30	783	433	0	0
T59	340	115	0	0
T60	291	69	0	0
T61	391	166	0	0
T122	1413	927	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	228	0	0
T8	439239	1	0	0
T10	0	1	0	0
T112	0	1	0	0
T113	0	9	0	0
T252	38535	0	0	0
T300	0	2	0	0
T301	0	64	0	0
T302	0	2	0	0
T319	58877	0	0	0
T342	0	1	0	0
T343	0	2	0	0
T344	0	2	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	119138494	0	0
T1	9760	9228	0	0
T2	10651	9393	0	0
T3	10145	9377	0	0
T28	18936	17686	0	0
T29	31558	30875	0	0
T30	29696	27702	0	0
T59	10335	9395	0	0
T60	11039	9502	0	0
T61	9790	9103	0	0
T122	49564	47907	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T28
0	1	Unreachable
1	0	Covered	T28,T53,T8

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T29,T30
0	1	Unreachable
1	0	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T29,T30
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119920069	90893	0	0
DstReqKnown_A	1533793	1327044	0	0
SrcAckBusyChk_A	119920069	228	0	0
SrcBusyKnown_A	119920069	119138494	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	90893	0	0
T8	439239	398	0	0
T10	0	286	0	0
T112	0	267	0	0
T113	0	782	0	0
T252	38535	0	0	0
T300	0	2346	0	0
T301	0	26511	0	0
T302	0	639	0	0
T319	58877	0	0	0
T342	0	275	0	0
T343	0	799	0	0
T344	0	678	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1533793	1327044	0	0
T1	452	229	0	0
T2	309	84	0	0
T3	394	168	0	0
T28	391	166	0	0
T29	554	329	0	0
T30	783	433	0	0
T59	340	115	0	0
T60	291	69	0	0
T61	391	166	0	0
T122	1413	927	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	228	0	0
T8	439239	1	0	0
T10	0	1	0	0
T112	0	1	0	0
T113	0	2	0	0
T252	38535	0	0	0
T300	0	6	0	0
T301	0	64	0	0
T302	0	2	0	0
T319	58877	0	0	0
T342	0	1	0	0
T343	0	2	0	0
T344	0	2	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	119138494	0	0
T1	9760	9228	0	0
T2	10651	9393	0	0
T3	10145	9377	0	0
T28	18936	17686	0	0
T29	31558	30875	0	0
T30	29696	27702	0	0
T59	10335	9395	0	0
T60	11039	9502	0	0
T61	9790	9103	0	0
T122	49564	47907	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T31,T32,T28
0	1	Unreachable
1	0	Covered	T28,T8,T10

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T28
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T29,T30
0	1	Covered	T7,T9,T12
1	0	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T28,T8,T10
1	1	Covered	T28,T8,T10

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T29,T30
1	0	Not Covered
1	1	Covered	T7,T9,T12

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T8,T10
0	0	0	Covered	T28,T29,T30

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T28,T29,T30
0	1	-	Covered	T28,T8,T10
0	0	1	Covered	T28,T7,T8
0	0	0	Covered	T28,T29,T30

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	119920069	121222	0	0
DstReqKnown_A	1533793	1327044	0	0
SrcAckBusyChk_A	119920069	248	0	0
SrcBusyKnown_A	119920069	119138494	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	121222	0	0
T8	439239	444	0	0
T10	0	326	0	0
T12	0	2781	0	0
T14	0	1579	0	0
T15	0	637	0	0
T112	0	250	0	0
T113	0	1369	0	0
T252	38535	0	0	0
T300	0	6095	0	0
T302	0	760	0	0
T319	58877	0	0	0
T342	0	342	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1533793	1327044	0	0
T1	452	229	0	0
T2	309	84	0	0
T3	394	168	0	0
T28	391	166	0	0
T29	554	329	0	0
T30	783	433	0	0
T59	340	115	0	0
T60	291	69	0	0
T61	391	166	0	0
T122	1413	927	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	248	0	0
T8	439239	1	0	0
T10	0	1	0	0
T12	0	6	0	0
T14	0	3	0	0
T15	0	1	0	0
T112	0	1	0	0
T113	0	3	0	0
T252	38535	0	0	0
T300	0	12	0	0
T302	0	2	0	0
T319	58877	0	0	0
T342	0	1	0	0
T345	168981	0	0	0
T346	57410	0	0	0
T347	36648	0	0	0
T348	33089	0	0	0
T349	163280	0	0	0
T350	41604	0	0	0
T351	62705	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	119920069	119138494	0	0
T1	9760	9228	0	0
T2	10651	9393	0	0
T3	10145	9377	0	0
T28	18936	17686	0	0
T29	31558	30875	0	0
T30	29696	27702	0	0
T59	10335	9395	0	0
T60	11039	9502	0	0
T61	9790	9103	0	0
T122	49564	47907	0	0