CHIP Simulation Results

Wednesday January 17 2024 20:02:30 UTC

GitHub Revision: `4d88b9516c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 3635458896929517279689574864899235923834879224879080668186365324190153451241

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	4.533m	3.053ms	3	3	100.00
		chip_sw_example_rom	2.180m	2.258ms	3	3	100.00
		chip_sw_example_manufacturer	4.543m	3.095ms	3	3	100.00
		chip_sw_example_concurrency	5.591m	3.194ms	3	3	100.00
		chip_sw_uart_smoketest_signed	34.954m	8.209ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset	7.080m	7.676ms	5	5	100.00
V1	csr_rw	chip_csr_rw	10.185m	5.902ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	1.698h	61.484ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	2.962h	73.088ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	7.222m	10.077ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	2.962h	73.088ms	5	5	100.00
		chip_csr_rw	10.185m	5.902ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	10.510s	251.692us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	10.079m	4.340ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	10.079m	4.340ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	10.079m	4.340ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	17.161m	5.773ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	17.161m	5.773ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	18.625m	5.481ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	18.757m	5.946ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	16.779m	5.545ms	5	5	100.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.089h	22.517ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	50.272m	13.428ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	28.303m	14.261ms	5	5	100.00
V1		TOTAL			223	223	100.00
V2	chip_pin_mux	chip_padctrl_attributes	5.338m	5.921ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	5.338m	5.921ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	6.792m	3.567ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	10.085m	5.275ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	6.138m	3.877ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	28.954m	16.899ms	5	5	100.00
		chip_tap_straps_testunlock0	6.131m	4.159ms	5	5	100.00
		chip_tap_straps_rma	18.671m	8.557ms	5	5	100.00
		chip_tap_straps_prod	13.567m	7.686ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	6.093m	3.060ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	27.747m	7.985ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	14.358m	4.660ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	14.358m	4.660ms	6	6	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	5.924m	2.735ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	6.654m	3.526ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	12.716m	3.898ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	30.564m	24.194ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_sysrst_ctrl_reset	30.564m	24.194ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	30.564m	24.194ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	55.521m	20.507ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	55.521m	20.507ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	10.033m	6.092ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.604m	19.290ms	3	3	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	19.886m	8.067ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	11.704m	11.722ms	3	3	100.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	16.643m	5.001ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	17.538m	6.339ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	57.175m	19.038ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.200m	2.943ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	18.147m	4.788ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	6.306m	3.187ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.091m	4.785ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.359m	2.889ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.350m	4.727ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.786m	3.203ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	5.318m	2.953ms	1	1	100.00
V2	chip_sw_ast_alerts	chip_sw_sensor_ctrl_alert	19.362m	8.967ms	5	5	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	19.362m	8.967ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	7.894m	4.754ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	4.223m	2.952ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	7.894m	4.754ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	3.989m	2.740ms	3	3	100.00
		chip_sw_aes_smoketest	5.431m	2.598ms	3	3	100.00
		chip_sw_aon_timer_smoketest	6.551m	2.984ms	3	3	100.00
		chip_sw_clkmgr_smoketest	4.726m	2.904ms	3	3	100.00
		chip_sw_csrng_smoketest	5.454m	2.758ms	3	3	100.00
		chip_sw_entropy_src_smoketest	8.379m	3.343ms	3	3	100.00
		chip_sw_gpio_smoketest	5.218m	2.719ms	3	3	100.00
		chip_sw_hmac_smoketest	6.467m	3.068ms	3	3	100.00
		chip_sw_kmac_smoketest	6.042m	3.361ms	3	3	100.00
		chip_sw_otbn_smoketest	36.506m	9.736ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	4.532m	3.162ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	10.014m	5.135ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	8.749m	5.461ms	3	3	100.00
		chip_sw_rv_plic_smoketest	4.506m	2.911ms	3	3	100.00
		chip_sw_rv_timer_smoketest	3.987m	2.796ms	3	3	100.00
		chip_sw_rstmgr_smoketest	5.388m	2.849ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	4.307m	2.790ms	3	3	100.00
		chip_sw_uart_smoketest	6.125m	3.484ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	11.979m	4.140ms	3	3	100.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	34.954m	8.209ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.485h	73.808ms	3	3	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	38.235m	8.996ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	33.947m	15.814ms	3	3	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	12.835m	4.766ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	13.382m	10.403ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	2.837h	59.582ms	3	3	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.101h	67.114ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	7.412m	4.993ms	30	30	100.00
V2	tl_d_illegal_access	chip_tl_errors	7.412m	4.993ms	30	30	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	2.962h	73.088ms	5	5	100.00
		chip_same_csr_outstanding	1.211h	29.314ms	20	20	100.00
		chip_csr_hw_reset	7.080m	7.676ms	5	5	100.00
		chip_csr_rw	10.185m	5.902ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	2.962h	73.088ms	5	5	100.00
		chip_same_csr_outstanding	1.211h	29.314ms	20	20	100.00
		chip_csr_hw_reset	7.080m	7.676ms	5	5	100.00
		chip_csr_rw	10.185m	5.902ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.623m	2.427ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.160s	58.800us	100	100	100.00
		xbar_smoke_large_delays	1.907m	10.391ms	100	100	100.00
		xbar_smoke_slow_rsp	1.995m	7.143ms	100	100	100.00
		xbar_random_zero_delays	58.060s	603.450us	100	100	100.00
		xbar_random_large_delays	22.104m	110.600ms	100	100	100.00
		xbar_random_slow_rsp	21.330m	70.176ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.020m	1.496ms	99	100	99.00
		xbar_error_and_unmapped_addr	56.150s	1.362ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.425m	2.516ms	100	100	100.00
		xbar_error_and_unmapped_addr	56.150s	1.362ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.982m	3.968ms	100	100	100.00
		xbar_access_same_device_slow_rsp	52.972m	153.249ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.363m	2.785ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	13.054m	22.549ms	100	100	100.00
		xbar_stress_all_with_error	12.853m	19.170ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	17.762m	25.098ms	100	100	100.00
		xbar_stress_all_with_reset_error	15.347m	19.602ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	38.235m	8.996ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	45.433m	21.884ms	2	3	66.67
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	34.355m	9.480ms	3	3	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	24.580m	6.782ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	35.524m	8.737ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	33.565m	8.540ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	37.105m	8.718ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	36.084m	8.245ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	24.382m	6.711ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	35.120m	8.450ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	36.481m	8.667ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	32.699m	8.860ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	32.931m	8.939ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	46.010m	9.871ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	52.966m	11.939ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	45.118m	12.187ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	52.285m	11.838ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	46.539m	11.924ms	1	1	100.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	38.705m	9.902ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	44.116m	12.209ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	45.715m	11.759ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	52.733m	12.484ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	41.265m	11.863ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	26.082m	7.108ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	29.451m	8.291ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	34.157m	8.753ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	28.416m	7.878ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	32.141m	8.045ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	24.517m	7.451ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	33.092m	8.286ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	32.338m	8.400ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	30.489m	8.634ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	31.980m	8.329ms	1	1	100.00
V2	rom_e2e_sigverify_mod_exp	rom_e2e_sigverify_mod_exp_test_unlocked0_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_sw			0	3	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	27.271m	6.740ms	3	3	100.00
		rom_e2e_asm_init_dev	33.531m	8.384ms	3	3	100.00
		rom_e2e_asm_init_prod	31.054m	8.850ms	3	3	100.00
		rom_e2e_asm_init_prod_end	32.076m	9.082ms	3	3	100.00
		rom_e2e_asm_init_rma	38.100m	8.713ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas			0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	42.027m	10.697ms	3	3	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	5.001m	3.592ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.200m	2.943ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	5.224m	3.661ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.709m	2.837ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	11.969m	4.182ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.604m	19.290ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	11.604m	19.290ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	7.894m	3.447ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	10.014m	5.135ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	7.894m	3.447ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	16.376m	10.396ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	16.376m	10.396ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	9.073m	6.386ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	11.934m	5.591ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	12.096m	5.551ms	3	3	100.00
		chip_sw_aes_idle	4.709m	2.837ms	3	3	100.00
		chip_sw_hmac_enc_idle	5.707m	3.006ms	3	3	100.00
		chip_sw_kmac_idle	5.445m	3.320ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	8.465m	4.941ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	12.091m	5.692ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	9.964m	5.229ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	9.677m	4.075ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	24.881m	9.667ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.725m	4.562ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.013m	5.036ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.246m	4.175ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.143m	4.895ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.167m	4.262ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.072m	4.564ms	3	3	100.00
		chip_sw_ast_clk_outputs	19.886m	8.067ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	15.859m	13.137ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.246m	4.175ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.143m	4.895ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	16.643m	5.001ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	17.538m	6.339ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	57.175m	19.038ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.200m	2.943ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	18.147m	4.788ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	6.306m	3.187ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.091m	4.785ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.359m	2.889ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.350m	4.727ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.786m	3.203ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.907m	2.864ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	17.312m	5.698ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	18.617m	7.213ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	58.534m	24.380ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	5.234m	2.951ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	5.441m	2.667ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	9.347m	5.799ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	5.786m	3.016ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	9.207m	5.313ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	30.830m	20.324ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	37.405m	11.869ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	19.886m	8.067ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	11.098m	5.110ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	8.026m	3.419ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	14.192m	5.434ms	97	100	97.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	35.085m	9.149ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	27.269m	6.917ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	7.967m	3.995ms	3	3	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	15.026m	7.780ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.540m	2.585ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	57.750m	14.338ms	3	3	100.00
		chip_sw_entropy_src_ast_rng_req	3.976m	3.171ms	3	3	100.00
		chip_sw_edn_entropy_reqs	17.129m	5.207ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	3.976m	3.171ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	27.269m	6.917ms	3	3	100.00
V2	chip_sw_entropy_src_fuse_en_fw_read	chip_sw_entropy_src_fuse_en_fw_read_test	10.490m	4.560ms	3	3	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	4.029m	2.577ms	3	3	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	33.703m	20.098ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	18.076m	5.559ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	17.538m	6.339ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	16.417m	4.555ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	16.643m	5.001ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.320h	45.157ms	1	3	33.33
V2	chip_sw_flash_scramble	chip_sw_flash_init	33.703m	20.098ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	7.139m	3.919ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	12.373m	5.031ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	12.512m	6.051ms	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.320h	45.157ms	1	3	33.33
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	12.512m	6.051ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	12.512m	6.051ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	12.512m	6.051ms	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	12.512m	6.051ms	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	14.192m	5.434ms	97	100	97.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	7.078m	9.590ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	18.784m	5.927ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	14.111m	4.483ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	5.722m	3.231ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	6.306m	3.187ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.707m	3.006ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	18.529m	5.794ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	16.231m	5.188ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	19.406m	5.575ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	11.474m	3.892ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	12.373m	5.031ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.091m	4.785ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	9.661m	4.067ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	11.969m	4.182ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.122h	16.577ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	5.086m	2.860ms	3	3	100.00
		chip_sw_kmac_mode_kmac	6.187m	3.312ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.359m	2.889ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	12.373m	5.031ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	19.703m	10.497ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	4.994m	2.674ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	4.490m	2.773ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	5.445m	3.320ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	8.559m	5.293ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	28.954m	16.899ms	5	5	100.00
		chip_tap_straps_rma	18.671m	8.557ms	5	5	100.00
		chip_tap_straps_prod	13.567m	7.686ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	5.638m	3.402ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	19.703m	10.497ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	19.703m	10.497ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	19.703m	10.497ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	9.418m	5.265ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	12.512m	6.051ms	3	3	100.00
		chip_sw_flash_rma_unlocked	1.320h	45.157ms	1	3	33.33
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.691m	4.108ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	22.089m	8.183ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	26.724m	7.934ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	26.943m	7.532ms	3	3	100.00
		chip_sw_lc_ctrl_transition	19.703m	10.497ms	15	15	100.00
		chip_sw_keymgr_key_derivation	12.373m	5.031ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	8.705m	9.142ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	16.188m	8.008ms	3	3	100.00
		chip_prim_tl_access	7.078m	9.590ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	15.859m	13.137ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.725m	4.562ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.013m	5.036ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.246m	4.175ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.143m	4.895ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.167m	4.262ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	10.072m	4.564ms	3	3	100.00
		chip_tap_straps_dev	28.954m	16.899ms	5	5	100.00
		chip_tap_straps_rma	18.671m	8.557ms	5	5	100.00
		chip_tap_straps_prod	13.567m	7.686ms	5	5	100.00
		chip_rv_dm_lc_disabled	6.334m	9.660ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.895m	3.636ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.996m	3.047ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.061m	3.279ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	5.689m	3.916ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	45.245m	36.289ms	3	3	100.00
		chip_rv_dm_lc_disabled	6.334m	9.660ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.488h	47.634ms	1	3	33.33
		chip_sw_lc_walkthrough_prod			0	3	0.00
		chip_sw_lc_walkthrough_prodend	20.289m	10.355ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	1.308h	45.343ms	1	3	33.33
		chip_sw_lc_walkthrough_testunlocks	45.245m	36.289ms	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	6.655m	4.244ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	5.917m	3.980ms	3	3	100.00
		rom_volatile_raw_unlock	29.803m	9.605ms	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	19.703m	10.497ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	33.703m	20.098ms	3	3	100.00
		chip_sw_otbn_mem_scramble	10.181m	3.732ms	3	3	100.00
		chip_sw_keymgr_key_derivation	12.373m	5.031ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	14.408m	4.510ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.790m	3.104ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	33.703m	20.098ms	3	3	100.00
		chip_sw_otbn_mem_scramble	10.181m	3.732ms	3	3	100.00
		chip_sw_keymgr_key_derivation	12.373m	5.031ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	14.408m	4.510ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.790m	3.104ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	19.703m	10.497ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	8.061m	5.449ms	3	3	100.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	5.638m	3.402ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.691m	4.108ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	22.089m	8.183ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	26.724m	7.934ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	26.943m	7.532ms	3	3	100.00
		chip_sw_lc_ctrl_transition	19.703m	10.497ms	15	15	100.00
		chip_prim_tl_access	7.078m	9.590ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	7.078m	9.590ms	3	3	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	8.670m	6.792ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	10.010m	9.797ms	0	3	0.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	6.447m	6.661ms	0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	12.449m	7.221ms	1	3	33.33
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	11.670m	7.469ms	2	3	66.67
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	14.050m	11.301ms	0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	30.945m	13.116ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	16.376m	10.396ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	24.161m	11.013ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	11.544m	4.979ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	8.670m	6.792ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	10.102m	5.381ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	1.003h	30.921ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	8.201m	7.216ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	10.777m	5.294ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	38.524m	22.543ms	3	3	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	47.198m	12.943ms	2	3	66.67
		chip_sw_pwrmgr_all_reset_reqs	30.625m	14.383ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	45.187m	21.225ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	4.739m	2.805ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	14.192m	5.434ms	97	100	97.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	8.705m	9.142ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	8.705m	9.142ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	30.625m	14.383ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	38.524m	22.543ms	3	3	100.00
		chip_sw_pwrmgr_wdog_reset	11.544m	4.979ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	10.014m	5.135ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	7.541m	5.066ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	13.023m	5.637ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	8.046m	3.741ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	32.079m	12.668ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.859m	2.643ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	14.192m	5.434ms	97	100	97.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	30.450m	8.631ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	21.099m	5.883ms	3	3	100.00
		chip_plic_all_irqs_10	11.331m	4.366ms	3	3	100.00
		chip_plic_all_irqs_20	13.948m	5.280ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	5.266m	2.574ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	4.956m	2.720ms	3	3	100.00
V2	chip_sw_spi_device_tx_rx	chip_sw_spi_device_tx_rx	6.814m	3.908ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	3.485h	73.808ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	18.218m	8.078ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	9.373m	4.208ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	6.454m	3.876ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	4.779m	2.734ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	14.408m	4.510ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.350m	4.727ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	13.661m	6.289ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	17.791m	9.011ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	16.188m	8.008ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	14.192m	5.434ms	97	100	97.00
		chip_sw_data_integrity_escalation	14.358m	4.660ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	4.037m	3.186ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	4.944m	2.898ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup			0	0	--
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	10.769m	4.549ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host			0	0	--
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.867h	31.259ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	45.315m	12.083ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	5.175m	3.473ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	8.559m	5.293ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	14.192m	5.434ms	97	100	97.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	6.412m	3.493ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	32.079m	12.668ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	9.224m	5.509ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	8.503m	4.130ms	88	90	97.78
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	22.869m	11.027ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	35.085m	9.149ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	30.450m	8.631ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.677h	255.767ms	3	3	100.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	38.640m	20.306ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	25.083m	13.734ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	7.541m	5.066ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	10.127m	4.958ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	9.927m	5.906ms	3	3	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	18.671m	8.557ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	6.334m	9.660ms	3	3	100.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			2593	2661	97.44
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.920m	2.628ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark	2.759h	50.247ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus			0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	1.854m	2.419ms	0	1	0.00
		rom_e2e_jtag_debug_dev	2.105m	2.439ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.650m	2.084ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	1.013h	60.000ms	0	1	0.00
		rom_e2e_jtag_inject_dev	1.328h	60.000ms	0	1	0.00
		rom_e2e_jtag_inject_rma	54.294m	51.577ms	0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash	35.019m	10.515ms	0	3	0.00
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	7.631m	3.459ms	3	3	100.00
V3	chip_sw_sysrst_ctrl_combo_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	47.198m	12.943ms	2	3	66.67
		chip_sw_sysrst_ctrl_reset	30.564m	24.194ms	3	3	100.00
V3	chip_sw_sysrst_ctrl_input	chip_sw_sysrst_ctrl_inputs	5.924m	2.735ms	3	3	100.00
V3	chip_sw_sysrst_ctrl_input_interrupt	chip_sw_sysrst_ctrl_in_irq	12.716m	3.898ms	3	3	100.00
V3	chip_sw_sysrst_ctrl_ulp_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	10.033m	6.092ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	10.051m	2.861ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	35.835m	8.882ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	42.297m	10.797ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	10.121m	3.042ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_memory_protection			0	0	--
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	chip_sw_i2c_override			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	3.013m	3.340ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	12.652m	12.964ms	0	1	0.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	6.593m	13.159ms	0	3	0.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	10.682m	5.042ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	30.625m	14.383ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	14.192m	5.434ms	97	100	97.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	chip_sw_spi_device_pass_through_flash_model			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	chip_sw_spi_host_pass_through			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_watermarks			0	0	--
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.152h	18.477ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	1.854m	2.419ms	0	1	0.00
		rom_e2e_jtag_debug_dev	2.105m	2.439ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.650m	2.084ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	9.147m	5.226ms	3	3	100.00
V3		TOTAL			26	45	57.78
	Unmapped tests	chip_sival_flash_info_access	8.958m	3.079ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	13.720m	4.602ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	54.191m	17.195ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	18.065m	5.419ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	15.788m	5.225ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	5.930m	3.076ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	5.987m	3.246ms	3	3	100.00
		TOTAL			2866	2953	97.05

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	7	7	7	100.00
V1	19	19	19	100.00
V2	290	276	249	85.86
V2S	1	1	1	100.00
V3	92	21	10	10.87

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.78	95.37	94.46	98.06	--	95.24	97.93	99.61

Failure Buckets

Exit reason: Error: User command failed Job returned non-zero exit code has 40 failures:

Test rom_e2e_keymgr_init_rom_ext_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_meas.81676298332114107094882919844548883377737370079599121143283389635442983596990
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

  (16:36:11) Loading:
  (16:36:12) Loading:
  (16:36:12) Loading: 4 packages loaded
  (16:36:12) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:36:12) WARNING: Target pattern parsing failed.
  (16:36:12) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:36:12) INFO: Elapsed time: 38.298s
  (16:36:12) INFO: 0 processes.
  (16:36:12) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_meas.13071683834771808470433849576152218282207628006033849755028651592823052963819
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

  (16:46:14) Loading:
  (16:46:15) Loading:
  (16:46:15) Loading: 4 packages loaded
  (16:46:15) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:46:15) WARNING: Target pattern parsing failed.
  (16:46:15) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:46:15) INFO: Elapsed time: 25.600s
  (16:46:15) INFO: 0 processes.
  (16:46:15) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_no_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_no_meas.54584666136383961875452481620313550007696002049851938114411864329719341735621
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

  (16:36:49) Loading:
  (16:36:50) Loading:
  (16:36:50) Loading: 4 packages loaded
  (16:36:50) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:36:50) WARNING: Target pattern parsing failed.
  (16:36:50) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:36:50) INFO: Elapsed time: 42.900s
  (16:36:50) INFO: 0 processes.
  (16:36:50) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_no_meas.10083542129830780610084873093563809657997916904184368811253466425563902210763
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

  (16:46:06) Loading:
  (16:46:06) Loading:
  (16:46:06) Loading: 4 packages loaded
  (16:46:06) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:46:06) WARNING: Target pattern parsing failed.
  (16:46:06) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:46:06) INFO: Elapsed time: 18.570s
  (16:46:06) INFO: 0 processes.
  (16:46:06) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_invalid_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_invalid_meas.115585233452782095449833408019461279805476406463030167869092756755644957408275
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

  (16:36:12) Loading:
  (16:36:13) Loading:
  (16:36:13) Loading: 4 packages loaded
  (16:36:13) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:36:13) WARNING: Target pattern parsing failed.
  (16:36:13) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:36:13) INFO: Elapsed time: 38.281s
  (16:36:13) INFO: 0 processes.
  (16:36:13) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_invalid_meas.70412587823625163460336076099736133007636264641652016653510103925386083564122
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

  (16:46:06) Loading:
  (16:46:06) Loading:
  (16:46:06) Loading: 4 packages loaded
  (16:46:07) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:46:07) WARNING: Target pattern parsing failed.
  (16:46:07) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:46:07) INFO: Elapsed time: 17.575s
  (16:46:07) INFO: 0 processes.
  (16:46:07) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_sigverify_mod_exp_test_unlocked0_otbn has 3 failures.

0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.101276280127403249206351044107230396077212035961924836005393215178768224560631
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

  (16:36:05) Loading:
  (16:36:06) Loading:
  (16:36:06) Loading: 4 packages loaded
  (16:36:06) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (16:36:06) WARNING: Target pattern parsing failed.
  (16:36:06) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (16:36:06) INFO: Elapsed time: 18.940s
  (16:36:06) INFO: 0 processes.
  (16:36:06) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.97410121612125281008011063715354901375443137577820371348199730272060534629025
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

  (16:46:09) Loading:
  (16:46:10) Loading:
  (16:46:10) Loading: 4 packages loaded
  (16:46:10) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (16:46:10) WARNING: Target pattern parsing failed.
  (16:46:10) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (16:46:10) INFO: Elapsed time: 18.723s
  (16:46:10) INFO: 0 processes.
  (16:46:10) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_sigverify_mod_exp_test_unlocked0_sw has 3 failures.

0.rom_e2e_sigverify_mod_exp_test_unlocked0_sw.64606613618390214776855355062145527290332503774838108691676034160304521472484
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_test_unlocked0_sw/latest/run.log

  (16:36:31) Loading:
  (16:36:32) Loading:
  (16:36:32) Loading: 4 packages loaded
  (16:36:32) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (16:36:32) WARNING: Target pattern parsing failed.
  (16:36:32) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (16:36:32) INFO: Elapsed time: 28.570s
  (16:36:32) INFO: 0 processes.
  (16:36:32) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_sigverify_mod_exp_test_unlocked0_sw.34443466700505259635958443015210446440732094681205816005381588443453136079508
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_test_unlocked0_sw/latest/run.log

  (16:46:33) Loading:
  (16:46:33) Loading:
  (16:46:33) Loading: 4 packages loaded
  (16:46:34) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (16:46:34) WARNING: Target pattern parsing failed.
  (16:46:34) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (16:46:34) INFO: Elapsed time: 23.048s
  (16:46:34) INFO: 0 processes.
  (16:46:34) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

... and 9 more tests.

Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 15 failures:
- Test chip_sw_lc_walkthrough_dev has 2 failures.
  - 0.chip_sw_lc_walkthrough_dev.27155099924694271203012729620150997298801285090539388224189015667425629418822
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_dev/latest/run.log
```
  Job ID: smart:c50f2003-b207-4263-89cd-1537623cb52a
```
  - 1.chip_sw_lc_walkthrough_dev.8420203050460007093835541672563846200976733106524026127864528712594186886688
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_dev/latest/run.log
```
  Job ID: smart:9f588bf4-5983-45ad-b87e-084cd056d003
```
- Test chip_sw_lc_walkthrough_prod has 3 failures.
  - 0.chip_sw_lc_walkthrough_prod.37607360491809532955702365805897164629321461408050572539377479983382221639074
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prod/latest/run.log
```
  Job ID: smart:f884b379-38db-455e-b318-2868ddc8d924
```
  - 1.chip_sw_lc_walkthrough_prod.58335886316834736301571122706281083734406091615427746708304926668260422206056
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_prod/latest/run.log
```
  Job ID: smart:82c3770e-bc28-4551-83fa-19281d77df6d
```
  - ... and 1 more failures.
- Test chip_sw_lc_walkthrough_rma has 2 failures.
  - 0.chip_sw_lc_walkthrough_rma.105489739190634905472889542144882134461702494298638328645785399030212450594530
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_rma/latest/run.log
```
  Job ID: smart:c48fb656-13fd-42ee-9124-2c38614b5ba9
```
  - 1.chip_sw_lc_walkthrough_rma.52903706830405051628012679315615011502356165729016305389498210687229038644876
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_rma/latest/run.log
```
  Job ID: smart:7b4f91f5-b100-4415-92b0-c6b87b60deb5
```
- Test chip_sw_rv_timer_systick_test has 3 failures.
  - 0.chip_sw_rv_timer_systick_test.88302013862947741049330504428815047077731256951245982280300633468809184045053
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:93a06c2a-9e69-4335-9ac4-0725b9e9b578
```
  - 1.chip_sw_rv_timer_systick_test.13509726460936389925953476119182987695041911139012974210559698849709190131361
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:5a02ec1c-ca1e-4a89-9bae-6286e4893c0a
```
  - ... and 1 more failures.
- Test chip_sw_power_virus has 3 failures.
  - 0.chip_sw_power_virus.5190109431610800616153047503976106094321054305413353444141085514002467253212
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:53359ac6-5f3d-43a3-b537-6b0e1fd06435
```
  - 1.chip_sw_power_virus.21555262580412164256086504595606588492977791461413492606745414613002722475600
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:9a39accc-cbde-4782-84a7-624d635fbabf
```
  - ... and 1 more failures.
- ... and 1 more tests.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:303) virtual_sequencer [chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:
- Test chip_sw_pwrmgr_normal_sleep_por_reset has 1 failures.
  - 0.chip_sw_pwrmgr_normal_sleep_por_reset.48490971388712226243241910870321640041554902946101012262525808831567205142112
    Line 779, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest/run.log
```
  UVM_ERROR @ 17076.745104 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 17076.745104 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_pwrmgr_deep_sleep_por_reset has 2 failures.
  - 1.chip_sw_pwrmgr_deep_sleep_por_reset.113949781082686664870709462875963557482205096935433717318819101542499061976479
    Line 789, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log
```
  UVM_ERROR @ 17219.986777 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 17219.986777 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 2.chip_sw_pwrmgr_deep_sleep_por_reset.68338559526347699361106005377517674467459208746754415966674984274078555319967
    Line 795, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log
```
  UVM_ERROR @ 16393.858821 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 16393.858821 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:249)] CHECK-fail: Expected bit * set in irq causes has 3 failures:
- Test chip_sw_pwrmgr_normal_sleep_all_wake_ups has 3 failures.
  - 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.115163028852984050136240594736315954557936216935476067428128554226667206876606
    Line 759, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log
```
  UVM_ERROR @ 6005.335896 us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:249)] CHECK-fail: Expected bit 5 set in irq causes
  UVM_INFO @ 6005.335896 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.82283722533556460376746665360406745180023010106014329489688586848440725530615
    Line 792, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest/run.log
```
  UVM_ERROR @ 6092.318592 us: (sw_logger_if.sv:526) [pwrmgr_normal_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:249)] CHECK-fail: Expected bit 5 set in irq causes
  UVM_INFO @ 6092.318592 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_deep_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:249)] CHECK-fail: Expected bit * set in irq causes has 3 failures:
- Test chip_sw_pwrmgr_deep_sleep_all_wake_ups has 3 failures.
  - 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.60571551712118551390948859796469286027916703638105787469743705873733923961913
    Line 799, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest/run.log
```
  UVM_ERROR @ 11300.938484 us: (sw_logger_if.sv:526) [pwrmgr_deep_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:249)] CHECK-fail: Expected bit 5 set in irq causes
  UVM_INFO @ 11300.938484 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.17918278981363083216725387733717270984133613658370433380579184032335238140756
    Line 792, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest/run.log
```
  UVM_ERROR @ 9990.587764 us: (sw_logger_if.sv:526) [pwrmgr_deep_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:249)] CHECK-fail: Expected bit 5 set in irq causes
  UVM_INFO @ 9990.587764 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_random_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:249)] CHECK-fail: Expected bit * set in irq causes has 3 failures:
- Test chip_sw_pwrmgr_random_sleep_all_wake_ups has 3 failures.
  - 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.76928304276442611921008372656565064633587297639569171780666472412454070930245
    Line 775, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest/run.log
```
  UVM_ERROR @ 7593.800640 us: (sw_logger_if.sv:526) [pwrmgr_random_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:249)] CHECK-fail: Expected bit 5 set in irq causes
  UVM_INFO @ 7593.800640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.78520064879256251176858087325985571403728040953008757826057736385638446856024
    Line 790, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest/run.log
```
  UVM_ERROR @ 9796.575312 us: (sw_logger_if.sv:526) [pwrmgr_random_sleep_all_wake_ups_sim_dv(sw/device/tests/sim_dv/pwrmgr_sleep_all_wake_ups_impl.c:249)] CHECK-fail: Expected bit 5 set in irq causes
  UVM_INFO @ 9796.575312 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq.sv:20) [chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq] Timed out waiting for wake up sensor_ctrl sleep has 3 failures:
- Test chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up has 3 failures.
  - 0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.82876117547170243191717642900226634289964223755676754235774924187133764238223
    Line 814, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log
```
  UVM_FATAL @ 13349.149226 us: (chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq.sv:20) [uvm_test_top.env.virtual_sequencer.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq] Timed out waiting for wake up sensor_ctrl sleep
  UVM_INFO @ 13349.149226 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.20632219708853503537291029949930281717902244789747392210442076162518524307387
    Line 762, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest/run.log
```
  UVM_FATAL @ 13158.801260 us: (chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq.sv:20) [uvm_test_top.env.virtual_sequencer.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq] Timed out waiting for wake up sensor_ctrl sleep
  UVM_INFO @ 13158.801260 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:270) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.23543868804113855258825191293747171105543555275492136342866666999514994602704
    Line 738, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 2418.533500 us: (dv_utils_pkg.sv:270) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2418.533500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.60680176609439309536048682755338780396083531316904001803096688288964108823554
    Line 730, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 2438.657500 us: (dv_utils_pkg.sv:270) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2438.657500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.98468289959391707825235821441678435721511935940541862702069223160129385360384
    Line 720, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 2083.927000 us: (dv_utils_pkg.sv:270) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2083.927000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(sw/device/silicon_creator/rom/e2e/rom_e2e_self_hash_test.c:80)] CHECK-fail: (uint8_t *)output.dataM hash not self-checked for this device type: *x%xmatches (uint8_t *)kSimDvGoldenRomHash has 3 failures:

Test rom_e2e_self_hash has 3 failures.

0.rom_e2e_self_hash.23292903206742994794033621724035843986928039038525766641871613862267178229888
Line 778, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  UVM_ERROR @ 10514.998234 us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(sw/device/silicon_creator/rom/e2e/rom_e2e_self_hash_test.c:80)] CHECK-fail: (uint8_t *)output.dataM hash not self-checked for this device type: 0x%xmatches (uint8_t *)kSimDvGoldenRomHash
  UVM_INFO @ 10514.998234 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.rom_e2e_self_hash.99711587023358357491788893847665991884566212510033466297245939776023649813839
Line 756, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_self_hash/latest/run.log

  UVM_ERROR @ 9958.790312 us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(sw/device/silicon_creator/rom/e2e/rom_e2e_self_hash_test.c:80)] CHECK-fail: (uint8_t *)output.dataM hash not self-checked for this device type: 0x%xmatches (uint8_t *)kSimDvGoldenRomHash
  UVM_INFO @ 9958.790312 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 3 failures:
- Test chip_sw_all_escalation_resets has 3 failures.
  - 4.chip_sw_all_escalation_resets.88333698858082388927981682957357630781909417939869536699921418157844110989828
    Line 769, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/4.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2643.923490 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 2643.923490 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 56.chip_sw_all_escalation_resets.65481361860118131640910370650697651729639510055544471131194833875376320962637
    Line 757, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/56.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3225.389912 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 3225.389912 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * us hit, indicating a probable testbench issue has 2 failures:
- Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_inject_test_unlocked0.84682390933401660640828370928475622063177520259499882615916152216893935075007
    Line 780, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 60000.000000 us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 60000.000000 us hit, indicating a probable testbench issue
  UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_dev has 1 failures.
  - 0.rom_e2e_jtag_inject_dev.55262040877641378253820223113125710136046451851840856433208740259915166366797
    Line 733, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log
```
  UVM_FATAL @ 60000.000000 us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 60000.000000 us hit, indicating a probable testbench issue
  UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 2 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 2 failures.
  - 23.chip_sw_alert_handler_lpg_sleep_mode_alerts.65880430143595042050248376973760118802238325353918093891685486046908439629329
    Line 823, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3968.290456 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003a12 MTVAL=40600800
  UVM_INFO @ 3968.290456 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2742830111414826909882084324434091899776834436669771429917708930883439955626
    Line 773, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 4129.847464 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003a12 MTVAL=40600800
  UVM_INFO @ 4129.847464 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_otp_ctrl_escalation_vseq.sv:38) [chip_sw_otp_ctrl_escalation_vseq] Timeout waiting for OTP_CTRL error injection done. has 1 failures:
- Test chip_sw_otp_ctrl_escalation has 1 failures.
  - 0.chip_sw_otp_ctrl_escalation.103941551442876992264103976584245822185314023503729188504264035969500528271624
    Line 792, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
```
  UVM_FATAL @ 12963.695464 us: (chip_sw_otp_ctrl_escalation_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.chip_sw_otp_ctrl_escalation_vseq] Timeout waiting for OTP_CTRL error injection done.
  UVM_INFO @ 12963.695464 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_sysrst_ctrl_test_sim_dv(sw/device/tests/sim_dv/pwrmgr_sysrst_ctrl_test.c:78)] CHECK-fail: Timeout waiting for sysrst reset! has 1 failures:
- Test chip_sw_pwrmgr_sysrst_ctrl_reset has 1 failures.
  - 0.chip_sw_pwrmgr_sysrst_ctrl_reset.81938126729432977929251144540743500303992662124229374190875342763350255160206
    Line 738, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest/run.log
```
  UVM_ERROR @ 12942.982270 us: (sw_logger_if.sv:526) [pwrmgr_sysrst_ctrl_test_sim_dv(sw/device/tests/sim_dv/pwrmgr_sysrst_ctrl_test.c:78)] CHECK-fail: Timeout waiting for sysrst reset!
  UVM_INFO @ 12942.982270 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 1 failures:
- Test rom_e2e_jtag_inject_rma has 1 failures.
  - 0.rom_e2e_jtag_inject_rma.25974570626781439065260122080449179932583061664895776587844331536633636602217
    Line 781, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log
```
  UVM_FATAL @ 51576.914260 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 51576.914260 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(pend_req[h2d.a_source].pend == *)' has 1 failures:
- Test rom_e2e_shutdown_output has 1 failures.
  - 1.rom_e2e_shutdown_output.18438283497150023277499681974369091349876102171966071646454315364824633630861
    Line 942, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_shutdown_output/latest/run.log
```
      Offending '(pend_req[h2d.a_source].pend == 0)'
  UVM_ERROR @ 25675.424036 us: (tlul_assert.sv:263) [ASSERT FAILED] pendingReqPerSrc_M
  UVM_INFO @ 25675.424036 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```