Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo	75.00	50.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	120988025	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	20856	20856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	120988025	0	0
T1	365962	17721	0	0
T2	305754	8308	0	0
T3	382264	19792	0	0
T7	294490	9578	0	0
T17	1091288	22675	0	0
T18	3232456	96160	0	0
T19	1526536	47383	0	0
T20	1467416	36896	0	0
T67	333940	15718	0	0
T68	393066	20397	0	0
T69	331518	15388	0	0
T70	332970	15973	0	0
T71	327634	15644	0	0
T72	278954	6733	0	0
T98	2549392	75546	0	0
T99	1259752	38873	0	0
T100	2090864	43710	0	0
T145	1138432	35069	0	0
T147	1931496	34773	0	0
T148	672896	14471	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1829810	1828130	0	0
T2	1528770	1527020	0	0
T3	1911320	1909790	0	0
T7	1472450	1470700	0	0
T28	1493862	1491438	0	0
T67	1669700	1667960	0	0
T68	1965330	1963690	0	0
T69	1657590	1655910	0	0
T70	1664850	1663140	0	0
T71	1638170	1636450	0	0
T72	557908	557252	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1829810	1828130	0	0
T2	1528770	1527020	0	0
T3	1911320	1909790	0	0
T7	1472450	1470700	0	0
T28	1493862	1491438	0	0
T67	1669700	1667960	0	0
T68	1965330	1963690	0	0
T69	1657590	1655910	0	0
T70	1664850	1663140	0	0
T71	1638170	1636450	0	0
T72	557908	557252	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1829810	1828130	0	0
T2	1528770	1527020	0	0
T3	1911320	1909790	0	0
T7	1472450	1470700	0	0
T28	1493862	1491438	0	0
T67	1669700	1667960	0	0
T68	1965330	1963690	0	0
T69	1657590	1655910	0	0
T70	1664850	1663140	0	0
T71	1638170	1636450	0	0
T72	557908	557252	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	20856	20856	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T7	4	4	0	0
T29	6	6	0	0
T30	6	6	0	0
T31	6	6	0	0
T59	6	6	0	0
T60	6	6	0	0
T61	6	6	0	0
T67	4	4	0	0
T68	4	4	0	0
T69	4	4	0	0
T70	4	4	0	0
T71	4	4	0	0
T72	4	4	0	0
T131	6	6	0	0
T188	6	6	0	0
T313	6	6	0	0
T314	6	6	0	0