Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329258549	39442828	0	0
DepthKnown_A	329258549	329160609	0	0
RvalidKnown_A	329258549	329160609	0	0
WreadyKnown_A	329258549	329160609	0	0
gen_passthru_fifo.paramCheckPass	942	942	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	39442828	0	0
T17	136411	13374	0	0
T18	404057	51496	0	0
T19	190817	24930	0	0
T20	183427	20371	0	0
T98	318674	40171	0	0
T99	157469	22270	0	0
T100	261358	23589	0	0
T145	142304	20368	0	0
T147	241437	18830	0	0
T148	84112	8290	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	329160609	0	0
T1	182981	182813	0	0
T2	152877	152702	0	0
T3	191132	190979	0	0
T7	147245	147070	0	0
T67	166970	166796	0	0
T68	196533	196369	0	0
T69	165759	165591	0	0
T70	166485	166314	0	0
T71	163817	163645	0	0
T72	139477	139313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	329160609	0	0
T1	182981	182813	0	0
T2	152877	152702	0	0
T3	191132	190979	0	0
T7	147245	147070	0	0
T67	166970	166796	0	0
T68	196533	196369	0	0
T69	165759	165591	0	0
T70	166485	166314	0	0
T71	163817	163645	0	0
T72	139477	139313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	329160609	0	0
T1	182981	182813	0	0
T2	152877	152702	0	0
T3	191132	190979	0	0
T7	147245	147070	0	0
T67	166970	166796	0	0
T68	196533	196369	0	0
T69	165759	165591	0	0
T70	166485	166314	0	0
T71	163817	163645	0	0
T72	139477	139313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	942	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0
T72	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329258549	28938193	0	0
DepthKnown_A	329258549	329160609	0	0
RvalidKnown_A	329258549	329160609	0	0
WreadyKnown_A	329258549	329160609	0	0
gen_passthru_fifo.paramCheckPass	942	942	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	28938193	0	0
T17	136411	9193	0	0
T18	404057	42924	0	0
T19	190817	22141	0	0
T20	183427	16409	0	0
T98	318674	35083	0	0
T99	157469	16499	0	0
T100	261358	19909	0	0
T145	142304	14597	0	0
T147	241437	15007	0	0
T148	84112	6129	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	329160609	0	0
T1	182981	182813	0	0
T2	152877	152702	0	0
T3	191132	190979	0	0
T7	147245	147070	0	0
T67	166970	166796	0	0
T68	196533	196369	0	0
T69	165759	165591	0	0
T70	166485	166314	0	0
T71	163817	163645	0	0
T72	139477	139313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	329160609	0	0
T1	182981	182813	0	0
T2	152877	152702	0	0
T3	191132	190979	0	0
T7	147245	147070	0	0
T67	166970	166796	0	0
T68	196533	196369	0	0
T69	165759	165591	0	0
T70	166485	166314	0	0
T71	163817	163645	0	0
T72	139477	139313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	329160609	0	0
T1	182981	182813	0	0
T2	152877	152702	0	0
T3	191132	190979	0	0
T7	147245	147070	0	0
T67	166970	166796	0	0
T68	196533	196369	0	0
T69	165759	165591	0	0
T70	166485	166314	0	0
T71	163817	163645	0	0
T72	139477	139313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	942	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0
T72	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329258549	28777029	0	0
DepthKnown_A	329258549	329160609	0	0
RvalidKnown_A	329258549	329160609	0	0
WreadyKnown_A	329258549	329160609	0	0
gen_passthru_fifo.paramCheckPass	942	942	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	28777029	0	0
T1	182981	3556	0	0
T2	152877	5146	0	0
T3	191132	4062	0	0
T7	147245	6426	0	0
T67	166970	3249	0	0
T68	196533	4120	0	0
T69	165759	3286	0	0
T70	166485	3513	0	0
T71	163817	3210	0	0
T72	139477	4055	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	329160609	0	0
T1	182981	182813	0	0
T2	152877	152702	0	0
T3	191132	190979	0	0
T7	147245	147070	0	0
T67	166970	166796	0	0
T68	196533	196369	0	0
T69	165759	165591	0	0
T70	166485	166314	0	0
T71	163817	163645	0	0
T72	139477	139313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	329160609	0	0
T1	182981	182813	0	0
T2	152877	152702	0	0
T3	191132	190979	0	0
T7	147245	147070	0	0
T67	166970	166796	0	0
T68	196533	196369	0	0
T69	165759	165591	0	0
T70	166485	166314	0	0
T71	163817	163645	0	0
T72	139477	139313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	329160609	0	0
T1	182981	182813	0	0
T2	152877	152702	0	0
T3	191132	190979	0	0
T7	147245	147070	0	0
T67	166970	166796	0	0
T68	196533	196369	0	0
T69	165759	165591	0	0
T70	166485	166314	0	0
T71	163817	163645	0	0
T72	139477	139313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	942	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0
T72	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	329258549	23437543	0	0
DepthKnown_A	329258549	329160609	0	0
RvalidKnown_A	329258549	329160609	0	0
WreadyKnown_A	329258549	329160609	0	0
gen_passthru_fifo.paramCheckPass	942	942	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	23437543	0	0
T1	182981	14165	0	0
T2	152877	3162	0	0
T3	191132	15730	0	0
T7	147245	3152	0	0
T67	166970	12469	0	0
T68	196533	16277	0	0
T69	165759	12102	0	0
T70	166485	12460	0	0
T71	163817	12434	0	0
T72	139477	2678	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	329160609	0	0
T1	182981	182813	0	0
T2	152877	152702	0	0
T3	191132	190979	0	0
T7	147245	147070	0	0
T67	166970	166796	0	0
T68	196533	196369	0	0
T69	165759	165591	0	0
T70	166485	166314	0	0
T71	163817	163645	0	0
T72	139477	139313	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	329160609	0	0
T1	182981	182813	0	0
T2	152877	152702	0	0
T3	191132	190979	0	0
T7	147245	147070	0	0
T67	166970	166796	0	0
T68	196533	196369	0	0
T69	165759	165591	0	0
T70	166485	166314	0	0
T71	163817	163645	0	0
T72	139477	139313	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	329160609	0	0
T1	182981	182813	0	0
T2	152877	152702	0	0
T3	191132	190979	0	0
T7	147245	147070	0	0
T67	166970	166796	0	0
T68	196533	196369	0	0
T69	165759	165591	0	0
T70	166485	166314	0	0
T71	163817	163645	0	0
T72	139477	139313	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	942	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0
T72	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	404821390	96693	0	0
DepthKnown_A	404821390	404707683	0	0
RvalidKnown_A	404821390	404707683	0	0
WreadyKnown_A	404821390	404707683	0	0
gen_passthru_fifo.paramCheckPass	2848	2848	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404821390	96693	0	0
T17	136411	27	0	0
T18	404057	435	0	0
T19	190817	78	0	0
T20	183427	29	0	0
T98	318674	73	0	0
T99	157469	26	0	0
T100	261358	53	0	0
T145	142304	26	0	0
T147	241437	234	0	0
T148	84112	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404821390	404707683	0	0
T1	182981	182813	0	0
T2	152877	152702	0	0
T3	191132	190979	0	0
T7	147245	147070	0	0
T28	248977	248573	0	0
T67	166970	166796	0	0
T68	196533	196369	0	0
T69	165759	165591	0	0
T70	166485	166314	0	0
T71	163817	163645	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404821390	404707683	0	0
T1	182981	182813	0	0
T2	152877	152702	0	0
T3	191132	190979	0	0
T7	147245	147070	0	0
T28	248977	248573	0	0
T67	166970	166796	0	0
T68	196533	196369	0	0
T69	165759	165591	0	0
T70	166485	166314	0	0
T71	163817	163645	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404821390	404707683	0	0
T1	182981	182813	0	0
T2	152877	152702	0	0
T3	191132	190979	0	0
T7	147245	147070	0	0
T28	248977	248573	0	0
T67	166970	166796	0	0
T68	196533	196369	0	0
T69	165759	165591	0	0
T70	166485	166314	0	0
T71	163817	163645	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2848	2848	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T131	1	1	0	0
T188	1	1	0	0
T313	1	1	0	0
T314	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	404821390	99523	0	0
DepthKnown_A	404821390	404707683	0	0
RvalidKnown_A	404821390	404707683	0	0
WreadyKnown_A	404821390	404707683	0	0
gen_passthru_fifo.paramCheckPass	2848	2848	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404821390	99523	0	0
T17	136411	27	0	0
T18	404057	435	0	0
T19	190817	78	0	0
T20	183427	29	0	0
T98	318674	73	0	0
T99	157469	26	0	0
T100	261358	53	0	0
T145	142304	26	0	0
T147	241437	234	0	0
T148	84112	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404821390	404707683	0	0
T1	182981	182813	0	0
T2	152877	152702	0	0
T3	191132	190979	0	0
T7	147245	147070	0	0
T28	248977	248573	0	0
T67	166970	166796	0	0
T68	196533	196369	0	0
T69	165759	165591	0	0
T70	166485	166314	0	0
T71	163817	163645	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404821390	404707683	0	0
T1	182981	182813	0	0
T2	152877	152702	0	0
T3	191132	190979	0	0
T7	147245	147070	0	0
T28	248977	248573	0	0
T67	166970	166796	0	0
T68	196533	196369	0	0
T69	165759	165591	0	0
T70	166485	166314	0	0
T71	163817	163645	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404821390	404707683	0	0
T1	182981	182813	0	0
T2	152877	152702	0	0
T3	191132	190979	0	0
T7	147245	147070	0	0
T28	248977	248573	0	0
T67	166970	166796	0	0
T68	196533	196369	0	0
T69	165759	165591	0	0
T70	166485	166314	0	0
T71	163817	163645	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2848	2848	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T131	1	1	0	0
T188	1	1	0	0
T313	1	1	0	0
T314	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	404821390	47044	0	0
DepthKnown_A	404821390	404707683	0	0
RvalidKnown_A	404821390	404707683	0	0
WreadyKnown_A	404821390	404707683	0	0
gen_passthru_fifo.paramCheckPass	2848	2848	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404821390	47044	0	0
T17	136411	25	0	0
T18	404057	432	0	0
T19	190817	77	0	0
T20	183427	27	0	0
T98	318674	61	0	0
T99	157469	23	0	0
T100	261358	52	0	0
T145	142304	23	0	0
T147	241437	231	0	0
T148	84112	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404821390	404707683	0	0
T1	182981	182813	0	0
T2	152877	152702	0	0
T3	191132	190979	0	0
T7	147245	147070	0	0
T28	248977	248573	0	0
T67	166970	166796	0	0
T68	196533	196369	0	0
T69	165759	165591	0	0
T70	166485	166314	0	0
T71	163817	163645	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404821390	404707683	0	0
T1	182981	182813	0	0
T2	152877	152702	0	0
T3	191132	190979	0	0
T7	147245	147070	0	0
T28	248977	248573	0	0
T67	166970	166796	0	0
T68	196533	196369	0	0
T69	165759	165591	0	0
T70	166485	166314	0	0
T71	163817	163645	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404821390	404707683	0	0
T1	182981	182813	0	0
T2	152877	152702	0	0
T3	191132	190979	0	0
T7	147245	147070	0	0
T28	248977	248573	0	0
T67	166970	166796	0	0
T68	196533	196369	0	0
T69	165759	165591	0	0
T70	166485	166314	0	0
T71	163817	163645	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2848	2848	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T131	1	1	0	0
T188	1	1	0	0
T313	1	1	0	0
T314	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	404821390	47044	0	0
DepthKnown_A	404821390	404707683	0	0
RvalidKnown_A	404821390	404707683	0	0
WreadyKnown_A	404821390	404707683	0	0
gen_passthru_fifo.paramCheckPass	2848	2848	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404821390	47044	0	0
T17	136411	25	0	0
T18	404057	432	0	0
T19	190817	77	0	0
T20	183427	27	0	0
T98	318674	61	0	0
T99	157469	23	0	0
T100	261358	52	0	0
T145	142304	23	0	0
T147	241437	231	0	0
T148	84112	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404821390	404707683	0	0
T1	182981	182813	0	0
T2	152877	152702	0	0
T3	191132	190979	0	0
T7	147245	147070	0	0
T28	248977	248573	0	0
T67	166970	166796	0	0
T68	196533	196369	0	0
T69	165759	165591	0	0
T70	166485	166314	0	0
T71	163817	163645	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404821390	404707683	0	0
T1	182981	182813	0	0
T2	152877	152702	0	0
T3	191132	190979	0	0
T7	147245	147070	0	0
T28	248977	248573	0	0
T67	166970	166796	0	0
T68	196533	196369	0	0
T69	165759	165591	0	0
T70	166485	166314	0	0
T71	163817	163645	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404821390	404707683	0	0
T1	182981	182813	0	0
T2	152877	152702	0	0
T3	191132	190979	0	0
T7	147245	147070	0	0
T28	248977	248573	0	0
T67	166970	166796	0	0
T68	196533	196369	0	0
T69	165759	165591	0	0
T70	166485	166314	0	0
T71	163817	163645	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2848	2848	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T131	1	1	0	0
T188	1	1	0	0
T313	1	1	0	0
T314	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	404821390	49649	0	0
DepthKnown_A	404821390	404707683	0	0
RvalidKnown_A	404821390	404707683	0	0
WreadyKnown_A	404821390	404707683	0	0
gen_passthru_fifo.paramCheckPass	2848	2848	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404821390	49649	0	0
T17	136411	2	0	0
T18	404057	3	0	0
T19	190817	1	0	0
T20	183427	2	0	0
T98	318674	12	0	0
T99	157469	3	0	0
T100	261358	1	0	0
T145	142304	3	0	0
T147	241437	3	0	0
T148	84112	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404821390	404707683	0	0
T1	182981	182813	0	0
T2	152877	152702	0	0
T3	191132	190979	0	0
T7	147245	147070	0	0
T28	248977	248573	0	0
T67	166970	166796	0	0
T68	196533	196369	0	0
T69	165759	165591	0	0
T70	166485	166314	0	0
T71	163817	163645	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404821390	404707683	0	0
T1	182981	182813	0	0
T2	152877	152702	0	0
T3	191132	190979	0	0
T7	147245	147070	0	0
T28	248977	248573	0	0
T67	166970	166796	0	0
T68	196533	196369	0	0
T69	165759	165591	0	0
T70	166485	166314	0	0
T71	163817	163645	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404821390	404707683	0	0
T1	182981	182813	0	0
T2	152877	152702	0	0
T3	191132	190979	0	0
T7	147245	147070	0	0
T28	248977	248573	0	0
T67	166970	166796	0	0
T68	196533	196369	0	0
T69	165759	165591	0	0
T70	166485	166314	0	0
T71	163817	163645	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2848	2848	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T131	1	1	0	0
T188	1	1	0	0
T313	1	1	0	0
T314	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	404821390	52479	0	0
DepthKnown_A	404821390	404707683	0	0
RvalidKnown_A	404821390	404707683	0	0
WreadyKnown_A	404821390	404707683	0	0
gen_passthru_fifo.paramCheckPass	2848	2848	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404821390	52479	0	0
T17	136411	2	0	0
T18	404057	3	0	0
T19	190817	1	0	0
T20	183427	2	0	0
T98	318674	12	0	0
T99	157469	3	0	0
T100	261358	1	0	0
T145	142304	3	0	0
T147	241437	3	0	0
T148	84112	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404821390	404707683	0	0
T1	182981	182813	0	0
T2	152877	152702	0	0
T3	191132	190979	0	0
T7	147245	147070	0	0
T28	248977	248573	0	0
T67	166970	166796	0	0
T68	196533	196369	0	0
T69	165759	165591	0	0
T70	166485	166314	0	0
T71	163817	163645	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404821390	404707683	0	0
T1	182981	182813	0	0
T2	152877	152702	0	0
T3	191132	190979	0	0
T7	147245	147070	0	0
T28	248977	248573	0	0
T67	166970	166796	0	0
T68	196533	196369	0	0
T69	165759	165591	0	0
T70	166485	166314	0	0
T71	163817	163645	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	404821390	404707683	0	0
T1	182981	182813	0	0
T2	152877	152702	0	0
T3	191132	190979	0	0
T7	147245	147070	0	0
T28	248977	248573	0	0
T67	166970	166796	0	0
T68	196533	196369	0	0
T69	165759	165591	0	0
T70	166485	166314	0	0
T71	163817	163645	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2848	2848	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T131	1	1	0	0
T188	1	1	0	0
T313	1	1	0	0
T314	1	1	0	0