Unified Coverage Report :: Module :: prim_sync_reqack_data

Module : prim_sync_reqack_data

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data	100.00	100.00					100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.44	96.47	89.29	100.00		100.00	71.43	u_rv_core_ibex

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	91.67	100.00	66.67			100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	66.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	84.62			100.00	100.00	u_edn_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	91.67	100.00	66.67			100.00	100.00

Line Coverage for Module : prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Module : prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	658517098	3693	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	658517098	3693	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	658517098	3693	0	0
T17	136411	2	0	0
T18	404057	2	0	0
T19	190817	1	0	0
T20	183427	2	0	0
T86	88937	4	0	0
T87	216178	0	0	0
T88	315146	0	0	0
T89	148744	0	0	0
T90	275251	0	0	0
T91	274640	0	0	0
T92	157040	0	0	0
T93	251925	0	0	0
T98	318674	3	0	0
T99	157469	2	0	0
T100	261358	1	0	0
T145	142304	2	0	0
T147	241437	2	0	0
T148	84112	1	0	0
T199	0	4	0	0
T200	0	5	0	0
T241	0	4	0	0
T242	0	11	0	0
T243	0	4	0	0
T244	90759	0	0	0
T245	116137	0	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	658517098	3693	0	0
T17	136411	2	0	0
T18	404057	2	0	0
T19	190817	1	0	0
T20	183427	2	0	0
T86	88937	4	0	0
T87	216178	0	0	0
T88	315146	0	0	0
T89	148744	0	0	0
T90	275251	0	0	0
T91	274640	0	0	0
T92	157040	0	0	0
T93	251925	0	0	0
T98	318674	3	0	0
T99	157469	2	0	0
T100	261358	1	0	0
T145	142304	2	0	0
T147	241437	2	0	0
T148	84112	1	0	0
T199	0	4	0	0
T200	0	5	0	0
T241	0	4	0	0
T242	0	11	0	0
T243	0	4	0	0
T244	90759	0	0	0
T245	116137	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	329258549	32	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	329258549	32	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	32	0	0
T86	88937	4	0	0
T87	216178	0	0	0
T88	315146	0	0	0
T89	148744	0	0	0
T90	275251	0	0	0
T91	274640	0	0	0
T92	157040	0	0	0
T93	251925	0	0	0
T199	0	4	0	0
T200	0	5	0	0
T241	0	4	0	0
T242	0	11	0	0
T243	0	4	0	0
T244	90759	0	0	0
T245	116137	0	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	32	0	0
T86	88937	4	0	0
T87	216178	0	0	0
T88	315146	0	0	0
T89	148744	0	0	0
T90	275251	0	0	0
T91	274640	0	0	0
T92	157040	0	0	0
T93	251925	0	0	0
T199	0	4	0	0
T200	0	5	0	0
T241	0	4	0	0
T242	0	11	0	0
T243	0	4	0	0
T244	90759	0	0	0
T245	116137	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	153	0	0
CONT_ASSIGN	156	0	0
ALWAYS	159	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
93	1	1
153		unreachable
156		unreachable
159		unreachable
160		unreachable
162		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_edn_if.u_prim_sync_reqack_data

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA	329258549	3661	0	0
gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB	329258549	3661	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcA

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	3661	0	0
T17	136411	2	0	0
T18	404057	2	0	0
T19	190817	1	0	0
T20	183427	2	0	0
T98	318674	3	0	0
T99	157469	2	0	0
T100	261358	1	0	0
T145	142304	2	0	0
T147	241437	2	0	0
T148	84112	1	0	0

gen_assert_data_dst2src.SyncReqAckDataHoldDst2SrcB

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	3661	0	0
T17	136411	2	0	0
T18	404057	2	0	0
T19	190817	1	0	0
T20	183427	2	0	0
T98	318674	3	0	0
T99	157469	2	0	0
T100	261358	1	0	0
T145	142304	2	0	0
T147	241437	2	0	0
T148	84112	1	0	0