Unified Coverage Report :: Module :: rv_core_ibex

Module : rv_core_ibex

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.19	96.47	89.29	98.77		100.00	71.43

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex	91.44	96.47	89.29	100.00		100.00	71.43

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.44	96.47	89.29	100.00		100.00	71.43

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.56	97.60	95.58	98.69		98.13	92.81

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.17	89.96		92.56			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
fifo_d	100.00	100.00	100.00			100.00	100.00
fifo_i	93.75	75.00	100.00			100.00	100.00
gen_alert_senders[0].u_alert_sender	100.00			100.00
gen_alert_senders[1].u_alert_sender	100.00			100.00
gen_alert_senders[2].u_alert_sender	100.00			100.00
gen_alert_senders[3].u_alert_sender	75.00			75.00
tl_adapter_host_d_ibex	92.37	97.67	81.82			90.00	100.00
tl_adapter_host_i_ibex	87.90	90.48	72.22			88.89	100.00
u_alert_nmi_sync	100.00	100.00				100.00
u_core	96.63			96.63
u_core_sleeping_buf	100.00	100.00
u_dbus_trans	97.29	100.00	96.30			100.00	92.86
u_edn_if	89.08	100.00	86.44			94.87	75.00
u_ibus_trans	96.36	100.00	92.59			100.00	92.86
u_intr_timer_sync	100.00	100.00				100.00
u_lc_sync	100.00	100.00				100.00	100.00
u_prim_buf_irq	100.00	100.00
u_prim_esc_receiver	100.00			100.00
u_prim_lc_sender	100.00	100.00				100.00
u_prim_sync_reqack_data	91.67	100.00	66.67			100.00	100.00
u_pwrmgr_sync	100.00	100.00				100.00	100.00
u_reg_cfg	99.28	98.69	98.84			99.58	100.00
u_sim_win_rsp	80.88	77.55	68.18			77.78	100.00
u_tlul_req_buf	100.00	100.00
u_tlul_rsp_buf	100.00	100.00
u_wdog_nmi_sync	100.00	100.00				100.00

Line Coverage for Module : rv_core_ibex

	Line No.	Total	Covered	Percent
TOTAL		85	82	96.47
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
ALWAYS	488	3	3	100.00
CONT_ASSIGN	508	1	1	100.00
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
ALWAYS	514	8	8	100.00
CONT_ASSIGN	698	1	1	100.00
CONT_ASSIGN	698	1	1	100.00
CONT_ASSIGN	699	1	1	100.00
CONT_ASSIGN	699	1	1	100.00
CONT_ASSIGN	700	1	1	100.00
CONT_ASSIGN	700	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	705	1	1	100.00
CONT_ASSIGN	705	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	713	1	1	100.00
CONT_ASSIGN	714	1	1	100.00
CONT_ASSIGN	715	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	720	1	1	100.00
CONT_ASSIGN	722	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	731	1	1	100.00
CONT_ASSIGN	733	1	1	100.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	737	1	1	100.00
CONT_ASSIGN	747	1	1	100.00
CONT_ASSIGN	748	1	1	100.00
CONT_ASSIGN	749	1	1	100.00
CONT_ASSIGN	750	1	1	100.00
CONT_ASSIGN	753	1	1	100.00
CONT_ASSIGN	756	1	1	100.00
ALWAYS	788	11	11	100.00
ALWAYS	804	7	7	100.00
CONT_ASSIGN	815	1	1	100.00
CONT_ASSIGN	834	1	1	100.00
CONT_ASSIGN	835	1	1	100.00
CONT_ASSIGN	836	1	1	100.00
CONT_ASSIGN	839	1	0	0.00
CONT_ASSIGN	843	0	0
CONT_ASSIGN	882	1	1	100.00
ALWAYS	941	0	0
CONT_ASSIGN	982	1	0	0.00
CONT_ASSIGN	984	1	0	0.00
CONT_ASSIGN	986	1	1	100.00
CONT_ASSIGN	988	1	1	100.00
CONT_ASSIGN	990	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
202	1	1
203	1	1
216	1	1
217	1	1
218	1	1
225	1	1
263	1	1
265	1	1
268	1	1
342	1	1
348	1	1
363	1	1
488	1	1
489	1	1
491	1	1
508	1	1
509	1	1
510	1	1
511	1	1
514	1	1
515	1	1
516	1	1
517	1	1
518	1	1
519	1	1
520	1	1
521	1	1
			MISSING_ELSE
698	2	2
699	2	2
700	2	2
704	2	2
705	2	2
706	2	2
713	1	1
714	1	1
715	1	1
718	1	1
720	1	1
722	1	1
724	1	1
731	1	1
733	1	1
735	1	1
737	1	1
747	1	1
748	1	1
749	1	1
750	1	1
753	1	1
756	1	1
788	1	1
789	1	1
790	1	1
792	1	1
793	1	1
794	1	1
795	1	1
796	1	1
797	1	1
798	1	1
799	1	1
			MISSING_ELSE
804	1	1
805	1	1
806	1	1
807	1	1
809	1	1
810	1	1
811	1	1
815	1	1
834	1	1
835	1	1
836	1	1
839	0	1
843		unreachable
882	1	1
941		unreachable
942		unreachable
943		unreachable
944		unreachable
			==> MISSING_ELSE
982	0	1
984	0	1
986	1	1
988	1	1
990	1	1

---

Cond Coverage for Module : rv_core_ibex

	Total	Covered	Percent
Conditions	28	25	89.29
Logical	28	25	89.29
Non-Logical	0	0
Event	0	0

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T42,T105,T107
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T180,T181,T182
1	0	Covered	T183,T184,T167

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T183,T184,T167

 LINE       731
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T185,T21,T186
1	0	Covered	T17,T18,T19
1	1	Covered	T21,T22,T23

 LINE       733
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Covered	T17,T18,T19
1	1	Covered	T185,T21,T186

 LINE       735
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T185,T21,T186
1	0	Covered	T17,T18,T19
1	1	Covered	T21,T22,T23

 LINE       737
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T185,T21,T186
1	0	Covered	T17,T18,T19
1	1	Covered	T21,T22,T23

 LINE       749
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T183,T184,T167
0	1	0	Covered	T42,T105,T107
1	0	0	Covered	T187

 LINE       796
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T17,T18,T20
1	1	Covered	T17,T18,T19

---

Toggle Coverage for Module : rv_core_ibex

	Total	Covered	Percent
Totals	121	117	96.69
Total Bits	1624	1604	98.77
Total Bits 0->1	812	802	98.77
Total Bits 1->0	812	802	98.77

Ports	121	117	96.69
Port Bits	1624	1604	98.77
Port Bits 0->1	812	802	98.77
Port Bits 1->0	812	802	98.77

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	INPUT
rst_ni	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	INPUT
clk_edn_i	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	INPUT
rst_edn_ni	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	INPUT
clk_esc_i	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	INPUT
rst_esc_ni	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	INPUT
rst_cpu_n_o	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_o.d_ready	Yes	Yes	T30,T31,T60	Yes	T29,T30,T31	OUTPUT
corei_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
corei_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T30,T31,T188	Yes	T30,T31,T188	OUTPUT
corei_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_data[31:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
corei_tl_h_o.a_mask[3:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
corei_tl_h_o.a_address[31:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
corei_tl_h_o.a_source[5:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
corei_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_size[1:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
corei_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_opcode[2:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
corei_tl_h_o.a_valid	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
corei_tl_h_i.a_ready	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
corei_tl_h_i.d_error	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
corei_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
corei_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
corei_tl_h_i.d_data[31:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
corei_tl_h_i.d_sink	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
corei_tl_h_i.d_source[5:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
corei_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_size[1:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
corei_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_opcode[0]	Yes	Yes	*T29,*T30,*T31	Yes	T29,T30,T31	INPUT
corei_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_valid	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cored_tl_h_o.d_ready	Yes	Yes	T30,T31,T60	Yes	T29,T30,T31	OUTPUT
cored_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
cored_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T30,T31,T59	Yes	T30,T31,T59	OUTPUT
cored_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_data[31:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
cored_tl_h_o.a_mask[3:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
cored_tl_h_o.a_address[31:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
cored_tl_h_o.a_source[5:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
cored_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_size[1:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
cored_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_opcode[2:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
cored_tl_h_o.a_valid	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
cored_tl_h_i.a_ready	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cored_tl_h_i.d_error	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cored_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cored_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cored_tl_h_i.d_data[31:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cored_tl_h_i.d_sink	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cored_tl_h_i.d_source[5:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cored_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_size[1:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cored_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_opcode[0]	Yes	Yes	*T29,*T30,*T31	Yes	T29,T30,T31	INPUT
cored_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_valid	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
irq_software_i	Yes	Yes	T189,T96,T190	Yes	T189,T96,T190	INPUT
irq_timer_i	Yes	Yes	T140,T191,T192	Yes	T140,T191,T192	INPUT
irq_external_i	Yes	Yes	T18,T147,T145	Yes	T18,T147,T145	INPUT
esc_tx_i.esc_n	Yes	Yes	T145,T99,T193	Yes	T145,T99,T193	INPUT
esc_tx_i.esc_p	Yes	Yes	T145,T99,T193	Yes	T145,T99,T193	INPUT
esc_rx_o.resp_n	Yes	Yes	T145,T99,T193	Yes	T145,T99,T193	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T145,T99,T193	Yes	T145,T99,T193	OUTPUT
nmi_wdog_i	Yes	Yes	T18,T20,T109	Yes	T18,T20,T109	INPUT
debug_req_i	Yes	Yes	T194,T195,T196	Yes	T194,T195,T196	INPUT
crash_dump_o.current.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_valid	Unreachable	Unreachable		Unreachable		OUTPUT
lc_cpu_en_i[3:0]	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	INPUT
pwrmgr_cpu_en_i[3:0]	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	INPUT
pwrmgr_o.core_sleeping	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.d_ready	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cfg_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cfg_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cfg_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cfg_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_data[31:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cfg_tl_d_i.a_mask[3:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cfg_tl_d_i.a_address[7:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cfg_tl_d_i.a_address[15:8]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[20:16]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cfg_tl_d_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[24]	Yes	Yes	*T29,*T30,*T31	Yes	T29,T30,T31	INPUT
cfg_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[30]	Yes	Yes	*T29,*T30,*T31	Yes	T29,T30,T31	INPUT
cfg_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_source[5:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cfg_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_size[1:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cfg_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_opcode[2:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cfg_tl_d_i.a_valid	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cfg_tl_d_o.a_ready	Yes	Yes	T30,T31,T60	Yes	T29,T30,T31	OUTPUT
cfg_tl_d_o.d_error	Yes	Yes	T29,T30,T60	Yes	T29,T30,T59	OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
cfg_tl_d_o.d_data[31:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
cfg_tl_d_o.d_sink	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
cfg_tl_d_o.d_source[5:0]	Yes	Yes	T29,T30,T60	Yes	T29,T30,T31	OUTPUT
cfg_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_size[1:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
cfg_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_opcode[0]	Yes	Yes	*T29,*T30,*T31	Yes	T29,T30,T31	OUTPUT
cfg_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_valid	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
edn_o.edn_req	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T20,T98,T145	Yes	T18,T19,T20	INPUT
edn_i.edn_fips	Yes	Yes	T98,T112,T101	Yes	T98,T197,T198	INPUT
edn_i.edn_ack	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
clk_otp_i	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	INPUT
rst_otp_ni	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	INPUT
icache_otp_key_o.req	Yes	Yes	T179,T86,T199	Yes	T179,T86,T199	OUTPUT
icache_otp_key_i.seed_valid	Yes	Yes	T17,T20,T44	Yes	T17,T18,T19	INPUT
icache_otp_key_i.nonce[127:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T20	INPUT
icache_otp_key_i.key[127:0]	Yes	Yes	T17,T20,T98	Yes	T17,T19,T20	INPUT
icache_otp_key_i.ack	Yes	Yes	T86,T199,T200	Yes	T86,T199,T200	INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T62,T63,T21	Yes	T62,T63,T21	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T62,T63,T185	Yes	T62,T63,T185	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	INPUT
alert_rx_i[2].ack_n	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T42,T105,T62	Yes	T42,T105,T62	INPUT
alert_rx_i[2].ping_n	Yes	Yes	T62,T63,T201	Yes	T62,T63,T201	INPUT
alert_rx_i[2].ping_p	Yes	Yes	T62,T63,T201	Yes	T62,T63,T201	INPUT
alert_rx_i[3].ack_n	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T62,T63,T21	Yes	T62,T63,T21	INPUT
alert_rx_i[3].ping_n	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	INPUT
alert_rx_i[3].ping_p	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T62,T63,T21	Yes	T62,T63,T21	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T62,T63,T185	Yes	T62,T63,T185	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T42,T105,T62	Yes	T42,T105,T62	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T62,T63,T21	Yes	T62,T63,T21	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : rv_core_ibex

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	348	2	2	100.00
IF	488	2	2	100.00
IF	514	3	3	100.00
IF	792	3	3	100.00
IF	804	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	348	(fatal_core_err) ? 

Branches:

-1-	Status	Tests
1	Covered	T183,T184,T167
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	488	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	514	if ((!rst_ni))
-2-:	518	if (double_fault)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T180,T181,T182
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	792	if (reg2hw.rnd_data.re)
-2-:	796	if ((edn_req && edn_ack))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T98,T147
0	1	Covered	T17,T18,T19
0	0	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	804	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : rv_core_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	15	71.43
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	15	71.43

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmIbexFetchEnable0_A	329258549	8	0	0
FpvSecCmIbexFetchEnable1_A	329258549	22499413	0	78
FpvSecCmIbexFetchEnable2_A	329258549	59870975	0	82
FpvSecCmIbexFetchEnable3Rev_A	329258549	264745974	0	1860
FpvSecCmIbexFetchEnable3_A	329258549	264747689	0	1775
FpvSecCmIbexInstrIntgErrCheck_A	329258549	304	0	0
FpvSecCmIbexLoadRespIntgErrCheck_A	329258549	586	0	0
FpvSecCmIbexPcMismatchCheck_A	329258549	0	0	0
FpvSecCmIbexRfEccErrCheck_A	329258549	0	0	0
FpvSecCmIbexStoreRespIntgErrCheck_A	329258549	0	0	0
FpvSecCmRegWeOnehotCheck_A	329258549	1	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A	329258549	0	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A	329258549	0	0	0
FpvSecCmRvCoreRegWeOnehotCheck_A	329258549	0	0	0
g_instr_intg_err_assert_signals.AssertConnected_A	942	942	0	0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A	942	942	0	0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A	942	942	0	0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A	942	942	0	0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A	942	942	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A	329258549	135	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A	329258549	194	0	0

FpvSecCmIbexFetchEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	8	0	0
T51	210265	0	0	0
T136	287052	0	0	0
T180	286695	1	0	0
T181	229110	1	0	0
T182	0	1	0	0
T202	0	1	0	0
T203	0	1	0	0
T204	0	1	0	0
T205	0	1	0	0
T206	0	1	0	0
T207	87578	0	0	0
T208	125954	0	0	0
T209	81791	0	0	0
T210	124703	0	0	0
T211	348616	0	0	0
T212	127081	0	0	0

FpvSecCmIbexFetchEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	22499413	0	78
T1	182981	19457	0	2
T2	152877	19352	0	2
T3	191132	19355	0	2
T7	147245	19400	0	2
T67	166970	19436	0	2
T68	196533	19324	0	2
T69	165759	19324	0	2
T70	166485	19323	0	2
T71	163817	19331	0	2
T72	139477	19401	0	2

FpvSecCmIbexFetchEnable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	59870975	0	82
T1	182981	69817	0	2
T2	152877	69712	0	2
T3	191132	69723	0	2
T7	147245	69756	0	2
T67	166970	69788	0	2
T68	196533	69692	0	2
T69	165759	69684	0	2
T70	166485	69687	0	2
T71	163817	69699	0	2
T72	139477	69765	0	2

FpvSecCmIbexFetchEnable3Rev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	264745974	0	1860
T1	182981	112988	0	2
T2	152877	82982	0	2
T3	191132	121248	0	2
T7	147245	77306	0	2
T67	166970	97000	0	2
T68	196533	126669	0	2
T69	165759	95899	0	2
T70	166485	96619	0	2
T71	163817	93938	0	2
T72	139477	69540	0	2

FpvSecCmIbexFetchEnable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	264747689	0	1775
T1	182981	112990	0	0
T2	152877	82984	0	0
T3	191132	121250	0	0
T7	147245	77308	0	0
T17	0	0	0	2
T18	0	0	0	2
T19	0	0	0	2
T20	0	0	0	2
T67	166970	97002	0	0
T68	196533	126671	0	0
T69	165759	95901	0	0
T70	166485	96621	0	0
T71	163817	93940	0	0
T72	139477	69542	0	0
T98	0	0	0	2
T99	0	0	0	2
T100	0	0	0	2
T145	0	0	0	2
T147	0	0	0	2
T148	0	0	0	2

FpvSecCmIbexInstrIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	304	0	0
T24	121304	0	0	0
T42	296532	76	0	0
T105	159603	0	0	0
T213	252669	76	0	0
T214	0	76	0	0
T215	0	76	0	0
T216	362343	0	0	0
T217	93104	0	0	0
T218	87548	0	0	0
T219	271428	0	0	0
T220	282221	0	0	0
T221	128208	0	0	0

FpvSecCmIbexLoadRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	586	0	0
T24	121304	0	0	0
T105	159603	32	0	0
T107	166643	32	0	0
T168	146461	0	0	0
T222	0	31	0	0
T223	0	1	0	0
T224	0	100	0	0
T225	0	100	0	0
T226	0	98	0	0
T227	0	1	0	0
T228	0	32	0	0
T229	0	32	0	0
T230	60426	0	0	0
T231	142896	0	0	0
T232	194617	0	0	0
T233	170022	0	0	0
T234	224764	0	0	0
T235	121515	0	0	0

FpvSecCmIbexPcMismatchCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	0	0	0

FpvSecCmIbexRfEccErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	0	0	0

FpvSecCmIbexStoreRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	1	0	0
T37	178570	0	0	0
T187	138947	1	0	0
T236	158508	0	0	0
T237	91276	0	0	0
T238	128811	0	0	0
T239	217094	0	0	0
T240	268944	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	0	0	0

FpvSecCmRvCoreRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	0	0	0

g_instr_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	942	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0
T72	1	1	0	0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	942	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0
T72	1	1	0	0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	942	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0
T72	1	1	0	0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	942	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0
T72	1	1	0	0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	942	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0
T72	1	1	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	135	0	0
T86	88937	16	0	0
T87	216178	0	0	0
T88	315146	0	0	0
T89	148744	0	0	0
T90	275251	0	0	0
T91	274640	0	0	0
T92	157040	0	0	0
T93	251925	0	0	0
T199	0	18	0	0
T200	0	22	0	0
T241	0	16	0	0
T242	0	46	0	0
T243	0	17	0	0
T244	90759	0	0	0
T245	116137	0	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	194	0	0
T86	0	42	0	0
T179	277627	16	0	0
T185	260422	0	0	0
T199	0	4	0	0
T200	0	5	0	0
T241	0	42	0	0
T242	0	11	0	0
T243	0	42	0	0
T246	0	16	0	0
T247	0	16	0	0
T248	74563	0	0	0
T249	156383	0	0	0
T250	843532	0	0	0
T251	125392	0	0	0
T252	126502	0	0	0
T253	78039	0	0	0
T254	110584	0	0	0
T255	168972	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Line No.	Total	Covered	Percent
TOTAL		85	82	96.47
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	216	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	218	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
ALWAYS	488	3	3	100.00
CONT_ASSIGN	508	1	1	100.00
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	511	1	1	100.00
ALWAYS	514	8	8	100.00
CONT_ASSIGN	698	1	1	100.00
CONT_ASSIGN	698	1	1	100.00
CONT_ASSIGN	699	1	1	100.00
CONT_ASSIGN	699	1	1	100.00
CONT_ASSIGN	700	1	1	100.00
CONT_ASSIGN	700	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	704	1	1	100.00
CONT_ASSIGN	705	1	1	100.00
CONT_ASSIGN	705	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	713	1	1	100.00
CONT_ASSIGN	714	1	1	100.00
CONT_ASSIGN	715	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	720	1	1	100.00
CONT_ASSIGN	722	1	1	100.00
CONT_ASSIGN	724	1	1	100.00
CONT_ASSIGN	731	1	1	100.00
CONT_ASSIGN	733	1	1	100.00
CONT_ASSIGN	735	1	1	100.00
CONT_ASSIGN	737	1	1	100.00
CONT_ASSIGN	747	1	1	100.00
CONT_ASSIGN	748	1	1	100.00
CONT_ASSIGN	749	1	1	100.00
CONT_ASSIGN	750	1	1	100.00
CONT_ASSIGN	753	1	1	100.00
CONT_ASSIGN	756	1	1	100.00
ALWAYS	788	11	11	100.00
ALWAYS	804	7	7	100.00
CONT_ASSIGN	815	1	1	100.00
CONT_ASSIGN	834	1	1	100.00
CONT_ASSIGN	835	1	1	100.00
CONT_ASSIGN	836	1	1	100.00
CONT_ASSIGN	839	1	0	0.00
CONT_ASSIGN	843	0	0
CONT_ASSIGN	882	1	1	100.00
ALWAYS	941	0	0
CONT_ASSIGN	982	1	0	0.00
CONT_ASSIGN	984	1	0	0.00
CONT_ASSIGN	986	1	1	100.00
CONT_ASSIGN	988	1	1	100.00
CONT_ASSIGN	990	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
202	1	1
203	1	1
216	1	1
217	1	1
218	1	1
225	1	1
263	1	1
265	1	1
268	1	1
342	1	1
348	1	1
363	1	1
488	1	1
489	1	1
491	1	1
508	1	1
509	1	1
510	1	1
511	1	1
514	1	1
515	1	1
516	1	1
517	1	1
518	1	1
519	1	1
520	1	1
521	1	1
			MISSING_ELSE
698	2	2
699	2	2
700	2	2
704	2	2
705	2	2
706	2	2
713	1	1
714	1	1
715	1	1
718	1	1
720	1	1
722	1	1
724	1	1
731	1	1
733	1	1
735	1	1
737	1	1
747	1	1
748	1	1
749	1	1
750	1	1
753	1	1
756	1	1
788	1	1
789	1	1
790	1	1
792	1	1
793	1	1
794	1	1
795	1	1
796	1	1
797	1	1
798	1	1
799	1	1
			MISSING_ELSE
804	1	1
805	1	1
806	1	1
807	1	1
809	1	1
810	1	1
811	1	1
815	1	1
834	1	1
835	1	1
836	1	1
839	0	1
843		unreachable
882	1	1
941		unreachable
942		unreachable
943		unreachable
944		unreachable
			==> MISSING_ELSE
982	0	1
984	0	1
986	1	1
988	1	1
990	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Covered	Percent
Conditions	28	25	89.29
Logical	28	25	89.29
Non-Logical	0	0
Event	0	0

 LINE       216
 EXPRESSION (ibus_intg_err | dbus_intg_err | alert_major_bus)
             ------1------   ------2------   -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T42,T105,T107
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       217
 EXPRESSION (alert_major_internal | double_fault)
             ----------1---------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T180,T181,T182
1	0	Covered	T183,T184,T167

 LINE       348
 EXPRESSION (fatal_core_err ? Off : local_fetch_enable_q)
             -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T183,T184,T167

 LINE       731
 EXPRESSION (reg2hw.alert_test.fatal_sw_err.q & reg2hw.alert_test.fatal_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T185,T21,T186
1	0	Covered	T17,T18,T19
1	1	Covered	T21,T22,T23

 LINE       733
 EXPRESSION (reg2hw.alert_test.recov_sw_err.q & reg2hw.alert_test.recov_sw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T21,T22,T23
1	0	Covered	T17,T18,T19
1	1	Covered	T185,T21,T186

 LINE       735
 EXPRESSION (reg2hw.alert_test.fatal_hw_err.q & reg2hw.alert_test.fatal_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T185,T21,T186
1	0	Covered	T17,T18,T19
1	1	Covered	T21,T22,T23

 LINE       737
 EXPRESSION (reg2hw.alert_test.recov_hw_err.q & reg2hw.alert_test.recov_hw_err.qe)
             ----------------1---------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T185,T21,T186
1	0	Covered	T17,T18,T19
1	1	Covered	T21,T22,T23

 LINE       749
 EXPRESSION (intg_err | fatal_intg_err | fatal_core_err)
             ----1---   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T183,T184,T167
0	1	0	Covered	T42,T105,T107
1	0	0	Covered	T187

 LINE       796
 EXPRESSION (edn_req && edn_ack)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T17,T18,T20
1	1	Covered	T17,T18,T19

---

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Covered	Percent
Totals	117	117	100.00
Total Bits	1604	1604	100.00
Total Bits 0->1	802	802	100.00
Total Bits 1->0	802	802	100.00

Ports	117	117	100.00
Port Bits	1604	1604	100.00
Port Bits 0->1	802	802	100.00
Port Bits 1->0	802	802	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	INPUT
rst_ni	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	INPUT
clk_edn_i	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	INPUT
rst_edn_ni	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	INPUT
clk_esc_i	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	INPUT
rst_esc_ni	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	INPUT
rst_cpu_n_o	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
hart_id_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
boot_addr_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_o.d_ready	Yes	Yes	T30,T31,T60	Yes	T29,T30,T31	OUTPUT
corei_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
corei_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
corei_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T30,T31,T188	Yes	T30,T31,T188	OUTPUT
corei_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_data[31:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
corei_tl_h_o.a_mask[3:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
corei_tl_h_o.a_address[31:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
corei_tl_h_o.a_source[5:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
corei_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_size[1:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
corei_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
corei_tl_h_o.a_opcode[2:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
corei_tl_h_o.a_valid	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
corei_tl_h_i.a_ready	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
corei_tl_h_i.d_error	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
corei_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
corei_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
corei_tl_h_i.d_data[31:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
corei_tl_h_i.d_sink	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
corei_tl_h_i.d_source[5:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
corei_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_size[1:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
corei_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_opcode[0]	Yes	Yes	*T29,*T30,*T31	Yes	T29,T30,T31	INPUT
corei_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
corei_tl_h_i.d_valid	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cored_tl_h_o.d_ready	Yes	Yes	T30,T31,T60	Yes	T29,T30,T31	OUTPUT
cored_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
cored_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
cored_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T30,T31,T59	Yes	T30,T31,T59	OUTPUT
cored_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_data[31:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
cored_tl_h_o.a_mask[3:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
cored_tl_h_o.a_address[31:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
cored_tl_h_o.a_source[5:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
cored_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_size[1:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
cored_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cored_tl_h_o.a_opcode[2:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
cored_tl_h_o.a_valid	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
cored_tl_h_i.a_ready	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cored_tl_h_i.d_error	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cored_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cored_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cored_tl_h_i.d_data[31:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cored_tl_h_i.d_sink	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cored_tl_h_i.d_source[5:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cored_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_size[1:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cored_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_opcode[0]	Yes	Yes	*T29,*T30,*T31	Yes	T29,T30,T31	INPUT
cored_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
cored_tl_h_i.d_valid	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
irq_software_i	Yes	Yes	T189,T96,T190	Yes	T189,T96,T190	INPUT
irq_timer_i	Yes	Yes	T140,T191,T192	Yes	T140,T191,T192	INPUT
irq_external_i	Yes	Yes	T18,T147,T145	Yes	T18,T147,T145	INPUT
esc_tx_i.esc_n	Yes	Yes	T145,T99,T193	Yes	T145,T99,T193	INPUT
esc_tx_i.esc_p	Yes	Yes	T145,T99,T193	Yes	T145,T99,T193	INPUT
esc_rx_o.resp_n	Yes	Yes	T145,T99,T193	Yes	T145,T99,T193	OUTPUT
esc_rx_o.resp_p	Yes	Yes	T145,T99,T193	Yes	T145,T99,T193	OUTPUT
nmi_wdog_i	Yes	Yes	T18,T20,T109	Yes	T18,T20,T109	INPUT
debug_req_i	Yes	Yes	T194,T195,T196	Yes	T194,T195,T196	INPUT
crash_dump_o.current.exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.last_data_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.next_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.current.current_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_addr[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_exception_pc[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
crash_dump_o.prev_valid	Unreachable	Unreachable		Unreachable		OUTPUT
lc_cpu_en_i[3:0]	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	INPUT
pwrmgr_cpu_en_i[3:0]	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	INPUT
pwrmgr_o.core_sleeping	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.d_ready	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cfg_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cfg_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cfg_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cfg_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_data[31:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cfg_tl_d_i.a_mask[3:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cfg_tl_d_i.a_address[7:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cfg_tl_d_i.a_address[15:8]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[20:16]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cfg_tl_d_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[24]	Yes	Yes	*T29,*T30,*T31	Yes	T29,T30,T31	INPUT
cfg_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_address[30]	Yes	Yes	*T29,*T30,*T31	Yes	T29,T30,T31	INPUT
cfg_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_source[5:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cfg_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_size[1:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cfg_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
cfg_tl_d_i.a_opcode[2:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cfg_tl_d_i.a_valid	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	INPUT
cfg_tl_d_o.a_ready	Yes	Yes	T30,T31,T60	Yes	T29,T30,T31	OUTPUT
cfg_tl_d_o.d_error	Yes	Yes	T29,T30,T60	Yes	T29,T30,T59	OUTPUT
cfg_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
cfg_tl_d_o.d_user.rsp_intg[6:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
cfg_tl_d_o.d_data[31:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
cfg_tl_d_o.d_sink	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
cfg_tl_d_o.d_source[5:0]	Yes	Yes	T29,T30,T60	Yes	T29,T30,T31	OUTPUT
cfg_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_size[1:0]	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
cfg_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_opcode[0]	Yes	Yes	*T29,*T30,*T31	Yes	T29,T30,T31	OUTPUT
cfg_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
cfg_tl_d_o.d_valid	Yes	Yes	T29,T30,T31	Yes	T29,T30,T31	OUTPUT
edn_o.edn_req	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	OUTPUT
edn_i.edn_bus[31:0]	Yes	Yes	T20,T98,T145	Yes	T18,T19,T20	INPUT
edn_i.edn_fips	Yes	Yes	T98,T112,T101	Yes	T98,T197,T198	INPUT
edn_i.edn_ack	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
clk_otp_i	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	INPUT
rst_otp_ni	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	INPUT
icache_otp_key_o.req	Yes	Yes	T179,T86,T199	Yes	T179,T86,T199	OUTPUT
icache_otp_key_i.seed_valid	Yes	Yes	T17,T20,T44	Yes	T17,T18,T19	INPUT
icache_otp_key_i.nonce[127:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T20	INPUT
icache_otp_key_i.key[127:0]	Yes	Yes	T17,T20,T98	Yes	T17,T19,T20	INPUT
icache_otp_key_i.ack	Yes	Yes	T86,T199,T200	Yes	T86,T199,T200	INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ack_n	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T62,T63,T21	Yes	T62,T63,T21	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T62,T63,T185	Yes	T62,T63,T185	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	INPUT
alert_rx_i[2].ack_n	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	INPUT
alert_rx_i[2].ack_p	Yes	Yes	T42,T105,T62	Yes	T42,T105,T62	INPUT
alert_rx_i[2].ping_n	Yes	Yes	T62,T63,T201	Yes	T62,T63,T201	INPUT
alert_rx_i[2].ping_p	Yes	Yes	T62,T63,T201	Yes	T62,T63,T201	INPUT
alert_rx_i[3].ack_n	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	INPUT
alert_rx_i[3].ack_p	Yes	Yes	T62,T63,T21	Yes	T62,T63,T21	INPUT
alert_rx_i[3].ping_n	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	INPUT
alert_rx_i[3].ping_p	Yes	Yes	T62,T63,T65	Yes	T62,T63,T65	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T62,T63,T21	Yes	T62,T63,T21	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T62,T63,T185	Yes	T62,T63,T185	OUTPUT
alert_tx_o[2].alert_n	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	OUTPUT
alert_tx_o[2].alert_p	Yes	Yes	T42,T105,T62	Yes	T42,T105,T62	OUTPUT
alert_tx_o[3].alert_n	Yes	Yes	T28,T1,T2	Yes	T28,T1,T2	OUTPUT
alert_tx_o[3].alert_p	Yes	Yes	T62,T63,T21	Yes	T62,T63,T21	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Line No.	Total	Covered	Percent
Branches		12	12	100.00
TERNARY	348	2	2	100.00
IF	488	2	2	100.00
IF	514	3	3	100.00
IF	792	3	3	100.00
IF	804	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv' or '../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	348	(fatal_core_err) ? 

Branches:

-1-	Status	Tests
1	Covered	T183,T184,T167
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	488	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	514	if ((!rst_ni))
-2-:	518	if (double_fault)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T180,T181,T182
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	792	if (reg2hw.rnd_data.re)
-2-:	796	if ((edn_req && edn_ack))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T98,T147
0	1	Covered	T17,T18,T19
0	0	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	804	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	21	21	100.00	15	71.43
Cover properties	0	0		0
Cover sequences	0	0		0
Total	21	21	100.00	15	71.43

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmIbexFetchEnable0_A	329258549	8	0	0
FpvSecCmIbexFetchEnable1_A	329258549	22499413	0	78
FpvSecCmIbexFetchEnable2_A	329258549	59870975	0	82
FpvSecCmIbexFetchEnable3Rev_A	329258549	264745974	0	1860
FpvSecCmIbexFetchEnable3_A	329258549	264747689	0	1775
FpvSecCmIbexInstrIntgErrCheck_A	329258549	304	0	0
FpvSecCmIbexLoadRespIntgErrCheck_A	329258549	586	0	0
FpvSecCmIbexPcMismatchCheck_A	329258549	0	0	0
FpvSecCmIbexRfEccErrCheck_A	329258549	0	0	0
FpvSecCmIbexStoreRespIntgErrCheck_A	329258549	0	0	0
FpvSecCmRegWeOnehotCheck_A	329258549	1	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A	329258549	0	0	0
FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A	329258549	0	0	0
FpvSecCmRvCoreRegWeOnehotCheck_A	329258549	0	0	0
g_instr_intg_err_assert_signals.AssertConnected_A	942	942	0	0
g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A	942	942	0	0
g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A	942	942	0	0
g_pc_mismatch_alert_o_assert_signals.AssertConnected_A	942	942	0	0
g_rf_ecc_err_comb_assert_signals.AssertConnected_A	942	942	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A	329258549	135	0	0
gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A	329258549	194	0	0

FpvSecCmIbexFetchEnable0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	8	0	0
T51	210265	0	0	0
T136	287052	0	0	0
T180	286695	1	0	0
T181	229110	1	0	0
T182	0	1	0	0
T202	0	1	0	0
T203	0	1	0	0
T204	0	1	0	0
T205	0	1	0	0
T206	0	1	0	0
T207	87578	0	0	0
T208	125954	0	0	0
T209	81791	0	0	0
T210	124703	0	0	0
T211	348616	0	0	0
T212	127081	0	0	0

FpvSecCmIbexFetchEnable1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	22499413	0	78
T1	182981	19457	0	2
T2	152877	19352	0	2
T3	191132	19355	0	2
T7	147245	19400	0	2
T67	166970	19436	0	2
T68	196533	19324	0	2
T69	165759	19324	0	2
T70	166485	19323	0	2
T71	163817	19331	0	2
T72	139477	19401	0	2

FpvSecCmIbexFetchEnable2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	59870975	0	82
T1	182981	69817	0	2
T2	152877	69712	0	2
T3	191132	69723	0	2
T7	147245	69756	0	2
T67	166970	69788	0	2
T68	196533	69692	0	2
T69	165759	69684	0	2
T70	166485	69687	0	2
T71	163817	69699	0	2
T72	139477	69765	0	2

FpvSecCmIbexFetchEnable3Rev_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	264745974	0	1860
T1	182981	112988	0	2
T2	152877	82982	0	2
T3	191132	121248	0	2
T7	147245	77306	0	2
T67	166970	97000	0	2
T68	196533	126669	0	2
T69	165759	95899	0	2
T70	166485	96619	0	2
T71	163817	93938	0	2
T72	139477	69540	0	2

FpvSecCmIbexFetchEnable3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	264747689	0	1775
T1	182981	112990	0	0
T2	152877	82984	0	0
T3	191132	121250	0	0
T7	147245	77308	0	0
T17	0	0	0	2
T18	0	0	0	2
T19	0	0	0	2
T20	0	0	0	2
T67	166970	97002	0	0
T68	196533	126671	0	0
T69	165759	95901	0	0
T70	166485	96621	0	0
T71	163817	93940	0	0
T72	139477	69542	0	0
T98	0	0	0	2
T99	0	0	0	2
T100	0	0	0	2
T145	0	0	0	2
T147	0	0	0	2
T148	0	0	0	2

FpvSecCmIbexInstrIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	304	0	0
T24	121304	0	0	0
T42	296532	76	0	0
T105	159603	0	0	0
T213	252669	76	0	0
T214	0	76	0	0
T215	0	76	0	0
T216	362343	0	0	0
T217	93104	0	0	0
T218	87548	0	0	0
T219	271428	0	0	0
T220	282221	0	0	0
T221	128208	0	0	0

FpvSecCmIbexLoadRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	586	0	0
T24	121304	0	0	0
T105	159603	32	0	0
T107	166643	32	0	0
T168	146461	0	0	0
T222	0	31	0	0
T223	0	1	0	0
T224	0	100	0	0
T225	0	100	0	0
T226	0	98	0	0
T227	0	1	0	0
T228	0	32	0	0
T229	0	32	0	0
T230	60426	0	0	0
T231	142896	0	0	0
T232	194617	0	0	0
T233	170022	0	0	0
T234	224764	0	0	0
T235	121515	0	0	0

FpvSecCmIbexPcMismatchCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	0	0	0

FpvSecCmIbexRfEccErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	0	0	0

FpvSecCmIbexStoreRespIntgErrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	1	0	0
T37	178570	0	0	0
T187	138947	1	0	0
T236	158508	0	0	0
T237	91276	0	0	0
T238	128811	0	0	0
T239	217094	0	0	0
T240	268944	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	0	0	0

FpvSecCmRvCoreRegWeOnehotCheckRAddrB_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	0	0	0

FpvSecCmRvCoreRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	0	0	0

g_instr_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	942	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0
T72	1	1	0	0

g_lsu_load_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	942	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0
T72	1	1	0	0

g_lsu_store_resp_intg_err_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	942	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0
T72	1	1	0	0

g_pc_mismatch_alert_o_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	942	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0
T72	1	1	0	0

g_rf_ecc_err_comb_assert_signals.AssertConnected_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	942	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T67	1	1	0	0
T68	1	1	0	0
T69	1	1	0	0
T70	1	1	0	0
T71	1	1	0	0
T72	1	1	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyForwardedToCore_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	135	0	0
T86	88937	16	0	0
T87	216178	0	0	0
T88	315146	0	0	0
T89	148744	0	0	0
T90	275251	0	0	0
T91	274640	0	0	0
T92	157040	0	0	0
T93	251925	0	0	0
T199	0	18	0	0
T200	0	22	0	0
T241	0	16	0	0
T242	0	46	0	0
T243	0	17	0	0
T244	90759	0	0	0
T245	116137	0	0	0

gen_icache_scramble_asserts.IbexIcacheScrambleKeyRequestAfterFenceI_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	329258549	194	0	0
T86	0	42	0	0
T179	277627	16	0	0
T185	260422	0	0	0
T199	0	4	0	0
T200	0	5	0	0
T241	0	42	0	0
T242	0	11	0	0
T243	0	42	0	0
T246	0	16	0	0
T247	0	16	0	0
T248	74563	0	0	0
T249	156383	0	0	0
T250	843532	0	0	0
T251	125392	0	0	0
T252	126502	0	0	0
T253	78039	0	0	0
T254	110584	0	0	0
T255	168972	0	0	0